Supported EDA Tools and Hardware

Cosimulation Requirements

To get started, see Set Up MATLAB-HDL Simulator Connection or Start HDL Simulator for Cosimulation in Simulink.

Cadence Incisive and Xcelium Requirements

MATLAB® and Simulink® support Cadence® verification tools using HDL Verifier™. Only the 64-bit version of Incisive® is supported for cosimulation. Use one of these recommended versions, which have been fully tested against the current release:

  • Xcelium™ 19.03

  • Xcelium 18.03

  • Xcelium 17.0

  • Incisive 15.2

    Note

    Not supported for nclaunch with runmode set to Batch. Set runmode to CLI instead.

The HDL Verifier shared libraries (liblfihdls*.so, liblfihdlc*.so) are built using the gcc included in the Cadence Incisive® simulator platform distribution. Before you link your own applications into the HDL simulator, first try building against this gcc. See the HDL simulator documentation for more details about how to build and link your own applications.

Mentor Graphics Questa and ModelSim Usage Requirements

MATLAB and Simulink support Mentor Graphics® verification tools using HDL Verifier. Use one of the following recommended versions. Each version has been fully tested against the current release:

  • Questa® Core/Prime 10.6b, 2019.1, 2019.4

  • ModelSim® PE 10.6b, 2019.1, 2019.4

FPGA Verification Requirements

Xilinx Usage Requirements

MATLAB and Simulink support Xilinx® design tools using HDL Verifier. Use the FPGA-in-the-loop tools with these recommended versions:

  • Xilinx Vivado® 2019.2

  • Xilinx ISE 14.7

    Note

    Xilinx ISE is required for FPGA boards in the Spartan®-6, Virtex®-4, Virtex-5, and Virtex-6 families.

For tool setup instructions, see Set Up FPGA Design Software Tools.

Intel Quartus Usage Requirements

MATLAB and Simulink support Intel® design tools using HDL Verifier. Use the FPGA-in-the-loop tools with these recommended versions:

  • Intel Quartus® Prime 18.1

  • Intel Quartus Prime Pro 19.4 (supported for Intel Cyclone® 10 GX only)

  • Intel Quartus II 13.1 (supported for Intel Cyclone III boards only)

For tool setup instructions, see Set Up FPGA Design Software Tools.

Microsemi Usage Requirements

MATLAB and Simulink support Microsemi® design tools using HDL Verifier. Use the FPGA-in-the-loop tools with these recommended versions:

  • Microsemi Libero® SoC v12.0

For tool setup instructions, see Set Up FPGA Design Software Tools.

Supported FPGA Board Connections for FIL Simulation

For board support, see Supported FPGA Devices for FPGA Verification.

Additional boards can be custom added with the FPGA Board Manager. See Supported FPGA Device Families for Board Customization.

JTAG Connection

VendorRequired HardwareRequired Software
Intel

USB Blaster I or USB Blaster II download cable

  • USB Blaster I or II driver

  • For Windows® operating systems: Quartus Prime executable directory must be on system path.

  • For Linux® operating systems: versions below Quartus II 13.1 are not supported. Quartus II 14.1 is not supported. Only 64-bit Quartus is supported. Quartus library directory must be on LD_LIBRARY_PATH before starting MATLAB. Prepend the Linux distribution library path before the Quartus library on LD_LIBRARY_PATH. For example, /lib/x86_64-linux-gnu:$QUARTUS_PATH.

Xilinx

Digilent® download cable.

  • If your board has an onboard Digilent USB-JTAG module, use a USB cable.

  • If your board has a standard Xilinx 14 pin JTAG connector, use with HS2 or HS3 cable from Digilent.

  • For Windows operating systems: Xilinx Vivado executable directory must be on system path.

  • For Linux operating systems: Digilent Adept2

FTDI USB-JTAG cable

  • Supported for boards with onboard FT4232H, FT232H, or FT2232H devices implementing USB-to JTAG

Supported for Windows operating systems.

Note

FTDI USB JTAG support is only available for MATLAB as AXI Master and for FPGA Data Capture.

MicrosemiJTAG connection not supported

Note

When simulating your FPGA design through Digilent JTAG cable with Simulink or MATLAB, you cannot use any debugging software that requires access to the JTAG; for example, Vivado Logic Analyzer.

Ethernet Connection

Required HardwareSupported Interfaces[a]Required Software

  • Gigabit Ethernet card

  • Cross-over Ethernet cable

  • FPGA board with supported Ethernet connection

  • Gigabit Ethernet — GMII

  • Gigabit Ethernet — RGMII

  • Gigabit Ethernet — SGMII

  • Ethernet — MII

  • Ethernet — RMII

Note

RMII is supported with Vivado versions older than 2019.2.

There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.

Note

Ethernet connection to Virtex-7 VC707 not supported for Vivado versions older than 2013.4.

[a] The HDL Verifier Support Package for Microsemi FPGA Boards supports only SGMII interfaces.

Supported FPGA Devices for FPGA Verification

HDL Verifier supports FIL simulation on the devices shown in the following table. The board definition files for these boards are in the Download FPGA Board Support Package. You can add other FPGA boards for use with FIL with FPGA board customization (FPGA Board Customization).

Note

AXI Master is supported over Ethernet for Xilinx Zynq®-7000 ZC706, ZedBoard™, Kintex®-7 KC705, and Intel Arrow® MAX® 10 DECA boards.

AXI Master is supported over PCI Express for Intel Arria® 10 GX and Xilinx Kintex UltraScale+™ FPGA KCU116 Evaluation Kit boards.

Device FamilyBoardEthernet (FIL)JTAG (FIL, AXI Master, Data Capture)PCI Express (FIL)[a]Comments

Xilinx Artix®-7

Digilent Nexys™4 Artix-7

xx  
Digilent Arty Board x  

Xilinx Kintex-7

Kintex-7 KC705xxx 

Xilinx Kintex UltraScale™

Kintex UltraScale FPGA KCU105 Evaluation Kit

xx  

Xilinx Kintex UltraScale+

Kintex UltraScale+ FPGA KCU116 Evaluation Kit

 x For more information, see PCI Express MATLAB as AXI Master (HDL Verifier Support Package for Xilinx FPGA Boards).

Xilinx Spartan-6

Spartan-6 SP605x   
Spartan-6 SP601x   
XUP Atlys Spartan-6x   

Xilinx Spartan-7

Digilent Arty S7-25xx  

Xilinx Virtex UltraScale

Virtex UltraScale FPGA VCU108 Evaluation Kit

xx  

Xilinx Virtex UltraScale+

Virtex UltraScale+ FPGA VCU118 Evaluation Kit

 xx 

Xilinx Virtex-7

Virtex-7 VC707xxx 
Virtex-7 VC709 xx 

Xilinx Virtex-6

Virtex-6 ML605x   

Xilinx Virtex-5

Virtex ML505x   
Virtex ML506x   
Virtex ML507x   
Virtex XUPV5–LX110Tx   

XilinxVirtex-4

Virtex ML401x  

Note

Support for Virtex-4 device family will be removed in a future release.

Virtex ML402x  
Virtex ML403x  

Xilinx Zynq

Zynq-7000 ZC702

 x  
Zynq-7000 ZC706  x  
ZedBoard  x Use the USB port marked "PROG" for programming.

ZYBO™ Zynq-7000 Development Board

 x  
PicoZed™ SDR Development Kit x  
MiniZed™  x Supported only for Data Capture and AXI-Master via FTDI JTAG.

Xilinx Zynq UltraScale+

Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

 x  

Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit

 x FIL supported via Digilent HS3 cable only. AXI-Master and Data-Capture are supported via FTDI or HS3 JTAG.

Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

 x FIL supported via Digilent HS3 cable only. AXI-Master and Data-Capture are supported via FTDI or HS3 JTAG.

Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

 x FIL supported via Digilent HS3 cable only. AXI-Master and Data-Capture are supported via FTDI or HS3 JTAG.

Intel Arria II

Arria II GX FPGA Development Kitxx  

Intel Arria V

Arria V SoC Development Kit x  
Arria V Starter Kitxx  

Intel Arria 10

Arria 10 SoC Development Kitxx  
Arria 10 GXxxx

Quartus Prime 18.0 is not recommended for Arria 10 GX over PCI Express®.

Intel Cyclone IV

Cyclone IV GX FPGA Development Kitxx 
DE2-115 Development and Education Boardxx The Altera® DE2-115 FPGA development board has two Ethernet ports. FPGA-in-the-loop uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.
BeMicro SDKxx  

Intel Cyclone III

Cyclone III FPGA Starter Kit x 

Altera Cyclone III boards are supported with Quartus II 13.1

Note

Support for Cyclone III device family will be removed in a future release.

Cyclone III FPGA Development Kitxx 
Altera Nios II Embedded Evaluation Kit, Cyclone III Editionxx 

Intel Cyclone V

Cyclone V GX FPGA Development Kitxx  
Cyclone V SoC Development Kit  x  
Cyclone V GT Development Kitxxx 
Terasic Atlas-SoC Kit / DE0-Nano SoC Kit x  
Arrow SoCKit Development Kit x  

Intel Cyclone 10 LP

Altera Cyclone 10 LP Evaluation Kit

 x  

Intel Cyclone 10 GX

Altera Cyclone 10 GX FPGA Evaluation Kit

 x 

Must be used with Quartus Prime Pro

Intel MAX 10

Arrow MAX 10 DECA

xx  

Intel Stratix® IV

Stratix IV GX FPGA Development Kitxx  

Intel Stratix V

DSP Development Kit, Stratix V Edition
xxx 

Microsemi SmartFusion®2

Microsemi SmartFusion2 SoC FPGA Advanced Development Kit

x  See Installing Microsemi SmartFusion2 SoC FPGA Advanced Development Kit (HDL Verifier Support Package for Microsemi FPGA Boards)

Microsemi Polarfire®

Microsemi Polarfire Evaluation Kit

x  See Installing Microsemi Polarfire Evaluation Kit (HDL Verifier Support Package for Microsemi FPGA Boards)

Microsemi RTG4®

RTG4-DEV-KIT

x   

[a] FIL over PCI Express connection is supported only for 64-bit Windows operating systems.

Limitations

  • For FPGA development boards that have more than one FPGA device, only one such device can be used with FIL.

FPGA Board Support Packages.  The FPGA board support packages contain the definition files for all supported boards. You can download one or more vendor-specific packages. To use FIL, download at least one of these packages, or customize your own board definition file. See Create Custom FPGA Board Definition.

To see the list of HDL Verifier support packages, visit HDL Verifier Supported Hardware. To download an FPGA board support package:

  • On the MATLAB Home tab, in the Environment section, click Add-Ons > Get Hardware Support Packages.

Supported FPGA Device Families for Board Customization

HDL Verifier supports the following FPGA device families for board customization; that is, when you create your own board definition file. See FPGA Board Customization. PCI Express is not a supported connection for board customization.

Note

The HDL Verifier Support Package for Microsemi FPGA Boards does not support board customization.

Device FamilyRestrictions
Xilinx Artix 7 
Kintex 7 

Kintex UltraScale

 

Kintex UltraScale+

 
Spartan 6

Ethernet PHY RGMII is not supported.

Spartan 7 
Virtex 4

Note

Support for Virtex-4 device family will be removed in a future release.

Virtex 5 
Virtex 6 
Virtex 7

Supports Ethernet PHY SGMII only.

Virtex UltraScale

 

Virtex UltraScale+

 
Zynq 7000 

Zynq UltraScale+

 
Intel Arria II 
Arria V 
Arria 10  
Cyclone III

Note

Support for Cyclone III device family will be removed in a future release.

Cyclone IV 
Cyclone V 
Cyclone 10 LP 
Cyclone 10 GX 
MAX 10  
Stratix IV 
Stratix V 

UVM and DPI Component Generation Requirements

UVM and DPI component generation supports the same versions of Cadence Incisive and Mentor Graphics Questa and ModelSim as for cosimulation. You can generate a DPI component for use with either 64-bit or 32-bit Incisive.

In addition, UVM and DPI Component generation also supports:

  • Synopsys® VCS® MX O-2018.09 SP2

Note

When you run a DPI component in ModelSim 10.5b on Debian® 8.3, you may encounter a library incompatibility error:

** Warning: ** Warning: (vsim-7032) The 64-bit glibc RPM 
does not appear to be installed on this machine.  Calls to gcc may fail.
** Fatal: ** Error: (vsim-3827) Could not compile 'STUB_SYMS_OF_fooour.so':
To avoid this issue, on the Code Generation pane in Configuration Parameters, try these options:

  • Set the Build configuration to Faster Runs.

  • Or, set the Build configuration to Specify and specify the compiler flag -O3.

UVM generation also requires a UVM Reference Implementation, available for download from the UVM standard website. This feature is tested with the default shipped version for each supported simulator.

TLM Generation Requirements

With the current release, TLMG includes support for:

  • Compilers:

    • Visual Studio®: VS2008, VS2010, VS2012, VS2013, VS2015, and VS2017

    • Windows 7.1 SDK

    • gcc 6.3

  • SystemC:

    • SystemC 2.3.1 (TLM included)

      You can download SystemC and TLM libraries at https://accellera.org. Consult the Accellera Systems Initiative website for information about how to build these libraries after downloading.

  • System C Modeling Library (SCML):

HDL Verifier Documentation

Support