Generate Multicycle Path Information Files

Overview

HDL Coder™ implements multirate systems in HDL by generating a master clock running at the model's base rate, and generating subrate timing signals from the master clock (see also Code Generation from Multirate Models). The propagation time between two subrate registers can be more than one cycle of the master clock. A multicycle path is a path between two such registers.

When synthesizing HDL code, it is often useful to provide an analysis of multicycle register-to-register paths to the synthesis tool. If the synthesis tool can identify multicycle paths, you may be able to:

Realize higher clock rates from your multirate design.
Reduce the area of your design.
Reduce the execution time of the synthesis tool.

Using the Generate multicycle path information option (or the equivalentMulticyclePathInfo property for makehdl) you can instruct the coder to analyze multicycle paths in the generated code, and generate a multicycle path information file.

A multicycle path information file is a text file that describes one or more multicycle path constraints. A multicycle path constraint is a timing exception – it relaxes the default constraints on the system timing by allowing signals on a given path to have a longer propagation time. When using multiple clock mode, the file also contains clock definitions.

Typically a synthesis tool gives every signal a time budget of exactly 1 clock cycle to propagate from a source register to a destination register. A timing exception defines a path multiplier , N, that informs the synthesis tool that a signal has N clock cycles (N > 1) to propagate from the source to destination register. The path multiplier expresses some number of cycles of a relative clock at either the source or destination register. Where a timing exception is defined for a path, the synthesis tool has more flexibility in meeting the timing requirements for that path and for the system as a whole.

The generated multicycle path information file does not follow the native constraint file format of a particular synthesis tool. The file contains the multicycle path information required by popular synthesis tools. You can manually convert this information to multicycle path constraints in the format required by your synthesis tool, or write a script or tool to perform the conversion. The next section describes the format of a multicycle path constraint file in detail.

Format and Content of a Multicycle Path Information File

The following listing shows a simple multicycle path information file.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Constraints Report 
%     Module: Sbs
%     Model: mSbs.mdl
%
%     File Name: hdlsrc/Sbs_constraints.txt
%     Created: 2009-04-10 09:50:10
%     Generated by MATLAB 7.9 and HDL Coder 1.6
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%




%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Multicycle Paths
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
FROM : Sbs.boolireg; TO : Sbs.booloreg; PATH_MULT : 2; RELATIVE_CLK : source,
   Sbs.clk;
FROM : Sbs.boolireg_v<0>; TO : Sbs.booloreg_v<0>; PATH_MULT : 2; 
   RELATIVE_CLK : source, Sbs.clk;
FROM : Sbs.doubireg; TO : Sbs.douboreg; PATH_MULT : 2; RELATIVE_CLK : source,
   Sbs.clk;
FROM : Sbs.doubireg_v<0>; TO : Sbs.douboreg_v<0>; PATH_MULT : 2; 
   RELATIVE_CLK : source, Sbs.clk;
FROM : Sbs.intireg(7:0); TO : Sbs.intoreg(7:0); PATH_MULT : 2; 
   RELATIVE_CLK : source, Sbs.clk;
FROM : Sbs.intireg_v<0>(7:0);TO : Sbs.intoreg_v<0>(7:0);PATH_MULT : 2 
   RELATIVE_CLK : source,Sbs.clk;

The first section of the file is a header that identifies the source model and gives other information about how HDL Coder generated the file. this section terminates with the following comment lines:

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Multicycle Paths
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Note

For a single-rate model or a model without multicycle paths, the coder generates only the header section of the file.

The main body of the file follows. This section contains a flat table, each row of which defines a multicycle path constraint.

Each constraint consists of four fields. The format of each field is one of the following:

KEYWORD : field;
KEYWORD : subfield1,... subfield_N;

The keyword identifies the type of information contained in the field. The keyword string in each field terminates with a space followed by a colon.

The delimiter between fields is the semicolon. Within a field, the delimiter between subfields is the comma.

The following table defines the fields of a multicycle path constraint, in left-to-right order.

Keyword : field (or subfields)	Field Description
`FROM : src_reg_path;`	The source (or FROM) register of a multicycle path in the system. The value of `src_reg_path` is the HDL path of the source register's output signal. See also Register Path Syntax for FROM : and TO : Fields .
`TO : dst_reg_path;`	The destination (or TO) register of a multicycle path in the system. The FROM register drives the TO register in the HDL code. The value of `dst_reg_path` is the HDL path of the destination register's output signal. See also Register Path Syntax for FROM : and TO : Fields.
`PATH_MULT : N;`	The path multiplier defines the number of clock cycles that a signal has to propagate from the source to destination register. The `RELATIVE_CLK` field describes the clock associated with the path multiplier (the relative clock for the path). The path multiplier value `N` indicates that the signal has N clock cycles of its relative clock to propagate from source to destination register. The coder does not report register-to-register paths where N = 1, because this is the default path multiplier.
`RELATIVE_CLK : relclock, sysclock;`	The `RELATIVE_CLK` field contains two comma-delimited subfields. Each subfield expresses the location of the relative clock in a different form, for the use of different synthesis tools. The subfields are: `relclock`: Since HDL Coder currently generates only single-clock systems, this subfield takes the value `source`. In a multi-clock system, the relative clock associated with a multicycle path could be either the source or destination register of the path, and this subfield could take on either of the values `source` or `destination`. This usage is reserved for future release of the coder. `sysclock`: This subfield is intended for use with synthesis tools that require the actual propagation time for a multicycle path. `sysclock` provides the path to the system's top-level clock (e.g., `Sbs.clk`) You can use the period of this clock and the path multiplier to calculate the propagation time for a given path.

Register Path Syntax for FROM : and TO : Fields

The FROM : and TO: fields of a multipath constraint provide the path to a source or destination register and information about the signal data type, size, and other characteristics.

Fixed Point Signals. For fixed point signals, the register path has the form

reg_path<ps> (hb:lb)

where:

reg_path is the HDL hierarchical path of the signal. The delimiter between hierarchical levels is the period, for example: Sbs.u_H1.initreg.
<ps>: Part select (zero-origin integer index) for vector signals. Angle brackets <> delimit the part select field
(hb:lb): Bit select field, indicated from high-order bit to low-order bit. The signal width (hb:lb) is the same as the defined width of the signal in the HDL code. This representation does not necessarily imply that the bits of the FROM : register are connected to the corresponding bits of the TO: register. The actual bit-to-bit connections are determined during synthesis.

Boolean and Double Signals. For boolean and double signals, the register path has the form

reg_path<ps>

where:

reg_path is the HDL hierarchical path of the signal. The delimiter between hierarchical levels is the period (.), for example: Sbs.u_H1.initreg.
<ps>: Part select (zero-origin integer index) for vector signals. Angle brackets <> delimit the part select field

For boolean and double signals, no bit select field is present.

Note

The format does not distinguish between boolean and double signals.

Examples. The following table gives several examples of register-to-register paths as represented in a multicycle path information file.

Path	Description
`FROM : Sbs.intireg(7:0); TO : Sbs.intoreg(7:0);`	Both signals are fixed point and eight bits wide.
`FROM : Sbs.intireg; TO : Sbs.intoreg;`	Both signals are either boolean or double.
`FROM : Sbs.intireg<0>(7:0); TO : Sbs.intoreg<1>(7:0);`	The FROM signal is the first element of a vector. The TO signal is the second element of a vector. Both signals are fixed point and eight bits wide.
`FROM : Sbs.u_H1.intireg(7:0); TO : Sbs.intoreg(7:0);`	The signal `intireg` is defined in the module `H1`, and `H1` is inside the module `Sbs`. `u_H1` is the instance name of `H1` in `Sbs`. Both signals are fixed point and eight bits wide.

Ordering of Multicycle Path Constraints

For a given model or subsystem, the ordering of multicycle path constraints within a multicycle path information file may vary depending on whether the target language is VHDL^® or Verilog^®, and on other factors. The ordering of constraints may also change in future versions of the coder. When you design scripts or other tools that process multicycle path information file, do not build in any assumptions about the ordering of multicycle path constraints within a file.

Clock Definitions

When you use multiple clock mode, the multicycle path information file also contains a "Clock Definitions" section, as shown in the following listing. This section is located after the header and before the "Multicycle Paths" section.

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Clock Definitions
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
CLOCK: Sbs.clk PERIOD: 0.05
CLOCK: Sbs.clk_1_2 BASE_CLOCK: Sbs.clk MULTIPLIER: 2 PERIOD: 0.1

The following table defines the fields for the clock definitions.

Keyword : field (or subfields)	Field Description
`CLOCK: clock_name`	Each clock in the design has a CLOCK definition line.
`PERIOD: float_value`	The Simulink^® rate (floating point value) associated with this CLOCK.
`BASE_CLOCK: base_clock_name`	Names the master clock. This field does not appear on the master clock.
`MULTIPLIER: int_value`	Gives the ratio of the period of this clock to the master clock. This field does not appear on the master clock.

File Naming and Location Conventions

The file name for the multicycle path information file derives from the name of the DUT and the postfix string '_constraints', as follows:

DUTname_constraints.txt

For example, if the DUT name is symmetric_fir, the name of the multicycle path information file is symmetric_fir_constraints.txt.

HDL Coder writes the multicycle path information file to the target .

Generating Multicycle Path Information Files Using the GUI

To enable generation of multicycle path information files, select Register-to-register path info in the Multicycle Path Constraints section of the HDL Code Generation > Target and Optimizations pane of the Configuration Parameters dialog box.

When you select this check box and generate code for your model, the code generator creates a multicycle path information file.

Generating Multicycle Path Information Files Using the Command Line

To generate a multicycle path information file from the command line, pass in the property/value pair 'MulticyclePathInfo','on' to makehdl, as in the following example.

>> dut = 'hdlfirtdecim_multicycle/Subsystem';
>> makehdl(dut, 'MulticyclePathInfo','on');
### Generating HDL for 'hdlfirtdecim_multicycle/Subsystem'
### Starting HDL Check.
### HDL Check Complete with 0 errors, 0 warnings and 1 message.

### MESSAGE: For the block 'hdlfirtdecim_multicycle/Subsystem/downsamp0'
   The initial condition may not be used when the sample offset is 0.

### Begin VHDL Code Generation
### Working on Subsystem_tc as hdlsrc\Subsystem_tc.vhd
### Working on hdlfirtdecim_multicycle/Subsystem as hdlsrc\Subsystem.vhd
### Generating package file hdlsrc\Subsystem_pkg.vhd
### Finishing multicycle path connectivity analysis.
### Writing multicycle path information in hdlsrc\Subsystem_constraints.txt
### HDL Code Generation Complete.

Limitations

Unsupported Blocks and Implementations

The following table lists block implementations (and associated Simulink blocks) that will not contribute to multicycle path constraints information.

Implementation	Block(s)
SumCascadeHDLEmission	Add, Subtract, Sum, Sum of Elements
ProductCascadeHDLEmission	Product, Product of Elements
MinMaxCascadeHDLEmission	MinMax, Maximum, Minimum
ModelReferenceHDLInstantiation	Model
SubsystemBlackBoxHDLInstiation	Subsystem
RamBlockDualHDLInstantiation	Dual Port RAM
RamBlockSimpDualHDLInstantiation	Simple Dual Port RAM
RamBlockSingleHDLInstantiation	Single Port RAM

Limitations on MATLAB Function Blocks and Stateflow Charts

Loop-Carried Dependencies. HDL Coder does not generate constraints for MATLAB Function blocks or Stateflow^® charts that contain a for loop with a loop-carried dependency.

Indexing Vector or Matrix Variables. In order to generate constraints for a vector or matrix index expression, the index expression must be one of the following:

A constant
A for loop induction variable

For example, in the following example of code for a MATLAB Function block, the index expression reg(i) does not generate constraints.

function y = fcn(u)
%#codegen 

N=length(u);
persistent reg;
if isempty(reg)
    reg = zeros(1,N);
end

y = reg;

for i = 1:N-1
    reg(i) = u(i) + reg(i+1);
end
reg(N) = u(N);

Documentation