Unit Delay Resettable Synchronous
Delay input signal by one sample period when external Reset signal is false
- Library:
HDL Coder / Discrete
Description
The Unit Delay Resettable Synchronous block delays the input signal u by one sample period when the external Reset signal is false. When the Reset signal is true, the state and output signal take the value of the Initial condition parameter. The Reset signal is true when R is not zero and false when R is zero.
The Unit Delay Resettable Synchronous block implementation consists of
a Synchronous Subsystem that contains a Resettable Delay
block with a Delay length of one and a State Control
block in Synchronous mode. When you use this block in your model and
have HDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware
resources due to the Synchronous behavior of the State
Control block.
Limitations
The block does not support vector inputs on the Reset port.
You cannot use the block inside Enabled Subsystem, Triggered Subsystem, or Resettable Subsystem blocks that use
Classicsemantics. The Subsystem must useSynchronoussemantics.