Unit Delay Enabled Resettable Synchronous
Delay input signal by one sample period when external Enable signal is true and external Reset signal is false
- Library:
HDL Coder / Discrete
Description
The Unit Delay Enabled Resettable Synchronous block combines the functionality of the Unit Delay Enabled Synchronous block and the Unit Delay Resettable Synchronous block.
The Unit Delay Enabled Resettable Synchronous block delays the input signal u by one sample period when the external Enable signal is true and when the external Reset signal is false. When the Enable signal is false, the state and output signal hold the previous value. When the Reset signal is true, the state and output signal take the value of the Initial condition parameter. The Enable and Reset signals are true when E and R are nonzero and false when E and R equal zero.
The Unit Delay Enabled Synchronous block implementation consists of a
Synchronous Subsystem that contains an Enabled Delay
block with a Delay length of one and a State Control
block in Synchronous mode. When you use this block in your model and
have HDL Coder™ installed, your model generates cleaner HDL code and uses fewer hardware
resources due to the Synchronous behavior of the State
Control block.
Limitations
The block does not support vector inputs on the Reset and Enable ports.
You cannot use the block inside Enabled Subsystem, Triggered Subsystem, or Resettable Subsystem blocks that use
Classicsemantics. The Subsystem must useSynchronoussemantics.
Ports
Input
Input
Output
Parameters
Extended Capabilities
See Also
State Control | Unit Delay | Unit Delay Enabled Synchronous | Unit Delay Resettable Synchronous