coder.HdlConfig class

Package: coder

HDL codegen configuration object

Description

A coder.HdlConfig object contains the configuration parameters that the HDL codegen function requires to generate HDL code. Use the -config option to pass this object to the codegen function.

Construction

hdlcfg = coder.config('hdl') creates a coder.HdlConfig object for HDL code generation.

Properties

Basic

AdderSharingMinimumBitwidth

Minimum bit width for shared adders, specified as a positive integer.

If ShareAdders is true and ResourceSharing is greater than 1, share adders only if adder bit width is greater than or equal to AdderSharingMinimumBitwidth.

Values: integer greater than or equal to 2

ClockEdge

Specify active clock edge.

Values: 'Rising' (default) | 'Falling'

DistributedPipeliningPriority

Priority for distributed pipelining algorithm.

DistributedPipeliningPriority Value Description

NumericalIntegrity (default)

Prioritize numerical integrity when distributing pipeline registers.

This option uses a conservative retiming algorithm that does not move registers across a component if the functional equivalence to the original design is unknown.

Performance

Prioritize performance over numerical integrity.

Use this option if your design requires a higher clock frequency and the MATLAB^® behavior does not need to strictly match the generated code behavior.

This option uses a more aggressive retiming algorithm that moves registers across a component even if the modified design’s functional equivalence to the original design is unknown.

Values: 'NumericalIntegrity' (default) | 'Performance'

GenerateHDLTestBench

Generate an HDL test bench, specified as a logical.

Values: false (default) | true

HDLCodingStandard

HDL coding standard to follow and check when generating code. Generates a compliance report showing errors, warnings, and messages.

Values: 'None' (default) | 'Industry'

HDLCodingStandardCustomizations

HDL coding standard rules and report customizations, specified using HDL Coding Standard Customization Properties. If you want to customize the coding standard rules and report, you must set HDLCodingStandard to 'Industry'.

Value: HDL coding standard customization object

HDLLintTool

HDL lint tool script to generate.

Values: 'None' (default) | 'AscentLint' | 'Leda' | 'SpyGlass' |'Custom'

HDLLintInit

HDL lint script initialization name, specified as a character vector.

HDLLintCmd

HDL lint script command.

If you set HDLLintTool to Custom, you must use %s as a placeholder for the HDL file name in the generated Tcl script. Specify HDLLintCmd as a character vector using the following format:

custom_lint_tool_command -option1 -option2 %s

HDLLintTerm

HDL lint script termination name, specified as a character vector.

InitializeBlockRAM

Specify whether to initialize all block RAM to '0' for simulation.

Values: true (default) | false

InlineConfigurations

Specify whether to include inline configurations in generated VHDL code.

When true, include VHDL configurations in files that instantiate a component.

When false, suppress the generation of configurations and require user-supplied external configurations. Set to false if you are creating your own VHDL configuration files.

Values: true (default) | false

LoopOptimization

Loop optimization in generated code. See Optimize MATLAB Loops.

LoopOptimization Value	Description
`LoopNone` (default)	Do not optimize loops in generated code.
`StreamLoops`	Stream loops.
`UnrollLoops`	Unroll Loops.

MinimizeClockEnables

Specify whether to omit generation of clock enable logic.

When true, omit generation of clock enable logic wherever possible.

When false (default), generate clock enable logic.

MultiplierPartitioningThreshold

Specify maximum input bit width for hardware multipliers. If a multiplier input bit width is greater than this threshold, HDL Coder™ splits the multiplier into smaller multipliers.

To improve your hardware mapping results, set this threshold to the input bit width of the DSP or multiplier hardware on your target device.

Values: integer greater than or equal to 2

MultiplierSharingMinimumBitwidth

Minimum bit width for shared multipliers, specified as a positive integer.

If ShareMultipliers is true and ResourceSharing is greater than 1, share multipliers only if multiplier bit width is greater than or equal to MultiplierSharingMinimumBitwidth.

Values: integer greater than or equal to 2

InstantiateFunctions

Generate instantiable HDL code modules from functions.

Values: false (default) | true

PreserveDesignDelays

Prevent distributed pipelining from moving design delays or allow distributed pipelining to move design delays, specified as a logical.

Persistent variables and dsp.Delay System objects are design delays.

Values: false (default) | true

ShareAdders

Share adders, specified as a logical.

If true, share adders when ResourceSharing is greater than 1 and adder bit width is greater than or equal to AdderSharingMinimumBitwidth.

Values: false (default) | true

ShareMultipliers

Share multipliers, specified as a logical.

If true, share multipliers when ResourceSharing is greater than 1, and multiplier bit width is greater than or equal to MultiplierSharingMinimumBitwidth.

Values: true (default) | false

SimulateGeneratedCode

Simulate generated code, specified as a logical.

Values: false (default) | true

SimulationIterationLimit

Maximum number of simulation iterations during test bench generation, specified as an integer. This property affects only test bench generation, not simulation during fixed-point conversion.

Values: unlimited (default) | positive integer

SimulationTool

Simulation tool name.

Values: 'ModelSim' (default) | 'ISIM'

SynthesisTool

Synthesis tool name.

Values: 'Xilinx ISE' (default) | 'Altera Quartus II' | 'Xilinx Vivado'

SynthesisToolChipFamily

Synthesis target chip family name, specified as a character vector.

Values: 'Virtex4' (default) | 'Family name'

SynthesisToolDeviceName

Synthesis target device name, specified as a character vector.

Values: 'xc4vsx35' (default) | 'Device name'

SynthesisToolPackageName

Synthesis target package name, specified as a character vector.

Values: 'ff668' (default) | 'Package name'

SynthesisToolSpeedValue

Synthesis target speed, specified as a character vector.

Values: '-10' (default) | 'Speed value'

SynthesizeGeneratedCode

Synthesize generated code or not, specified as a logical.

Values: false (default) | true

TargetLanguage

Target language of the generated code.

Values: 'VHDL' (default) | 'Verilog'

TestBenchName

Test bench function name, specified as a character vector. You must specify a test bench.

Values: '' (default) | 'Testbench name'

TimingControllerArch

Timing controller architecture.

TimingControllerArch Value	Description
`default` (default)	Do not generate a reset for the timing controller.
`resettable`	Generate a reset for the timing controller.

TimingControllerPostfix

Postfix to append to design name to form name of timing controller, specified as a character vector.

Values: '_tc' (default) | 'Postfix'

UseFileIOInTestBench

Create and use data files for reading and writing test bench input and output data.

Values: 'on' (default) | 'off'

VHDLLibraryName

Target library name for generated VHDL^® code, specified as a character vector.

Values: 'work' (default) | 'Library name'

Cosimulation

`GenerateCosimTestBench`	Generate a cosimulation test bench or not, specified as a `logical`. Values: `false` (default) \| `true`
`SimulateCosimTestBench`	Simulate generated cosimulation test bench, specified as a `logical`. This option is ignored if `GenerateCosimTestBench` is `false`. Values: `false` (default) \| `true`
`CosimClockEnableDelay`	Time (in clock cycles) between deassertion of reset and assertion of clock enable. Values: `0` (default)
`CosimClockHighTime`	The number of nanoseconds the clock is high. Values: `5` (default)
`CosimClockLowTime`	The number of nanoseconds the clock is low. Values: `5` (default)
`CosimHoldTime`	The hold time for input signals and forced reset signals, specified in nanoseconds. Values: `2` (default)
`CosimLogOutputs`	Log and plot outputs of the reference design function and HDL simulator. Values: `false` (default) \| `true`
`CosimResetLength`	Specify time (in clock cycles) between assertion and deassertion of reset. Values: `2` (default)
`CosimRunMode`	HDL simulator run mode during simulation. When in Batch mode, you do not see the HDL simulator GUI, and the HDL simulator automatically shuts down after simulation. Values: `Batch` (default) \| `GUI`
`CosimTool`	HDL simulator for the generated cosim test bench. Values: `ModelSim` (default) \| `Incisive`

FPGA-in-the-loop

`GenerateFILTestBench`	Generate a FIL test bench or not, specified as a `logical`. Values: `false` (default) \| `true`
`SimulateFILTestBench`	Simulate generated cosimulation test bench, specified as a `logical`. This option is ignored if `GenerateCosimTestBench` is `false`. Values: `false` (default) \| `true`
`FILBoardName`	FPGA board name, specified as a character vector. You must override the default value and specify a valid board name. Values: `'Choose a board'` (default) \| `'A board name'`
`FILBoardIPAddress`	IP address of the FPGA board, specified as a character vector. You must enter a valid IP address. Values: `192.168.0.2` (default)
`FILBoardMACAddress`	MAC address of the FPGA board, specified as a character vector. You must enter a valid MAC address. Values: `00-0A-35-02-21-8A` (default)
`FILAdditionalFiles`	List of additional source files to include, specified as a character vector. Separate file names with a semi-colon (";"). Values: `''` (default) \| `'Additional source files'`
`FILLogOutputs`	Log and plot outputs of the reference design function and FPGA. Values: `false` (default) \| `true`

Examples

collapse all

Generate Verilog Code from MATLAB Code

Create a coder.HdlConfig object, hdlcfg.

hdlcfg = coder.config('hdl'); % Create a default 'hdl' config

Set the test bench name. In this example, the test bench function name is mlhdlc_dti_tb.

hdlcfg.TestBenchName = 'mlhdlc_dti_tb';

Set the target language to Verilog^®.

hdlcfg.TargetLanguage = 'Verilog';

Generate HDL code from your MATLAB design. In this example, the MATLAB design function name is mlhdlc_dti.

codegen -config hdlcfg mlhdlc_dti

Generate Cosim and FIL Test Benches

Create a coder.FixptConfig object with default settings and provide test bench name.

fixptcfg = coder.config('fixpt'); 
fixptcfg.TestBenchName = 'mlhdlc_sfir_tb';

Create a coder.HdlConfig object with default settings and set enable rate.

hdlcfg = coder.config('hdl'); % Create a default 'hdl' config
hdlcfg.EnableRate = 'DUTBaseRate';

Instruct MATLAB to generate a cosim test bench and a FIL test bench. Specify FPGA board name.

hdlcfg.GenerateCosimTestBench = true;
hdlcfg.FILBoardName = 'Xilinx Virtex-5 XUPV5-LX110T development board';
hdlcfg.GenerateFILTestBench = true;

Perform code generation, Cosim test bench generation, and FIL test bench generation.

codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_sfir

Alternatives

You can also generate HDL code from MATLAB code using the HDL Workflow Advisor. For more information, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.

Documentation

coder.HdlConfig class

Description

Construction

Properties

Examples

Generate Verilog Code from MATLAB Code

Generate Cosim and FIL Test Benches

Alternatives

See Also

Functions

Classes

Properties

Topics

HDL Coder Documentation

Support