Repeat

Resample input at higher rate by repeating values

Library

Signal Operations

dspsigops

Description

The Repeat block upsamples each channel of the M_i-by-N input to a rate L times higher than the input sample rate. To do so, the block repeats each consecutive input sample L times at the output. You specify the integer L in the Repetition count parameter.

You can use the Repeat block inside of triggered subsystems when you set the Rate options parameter to Enforce single-rate processing.

Frame-Based Processing

When you set the Input processing parameter to Columns as channels (frame based), the block upsamples each column of the input over time. In this mode, the block can perform either single-rate or multirate processing. You can use the Rate options parameter to specify how the block upsamples the input:

When you set the Rate options parameter to Enforce single-rate processing, the input and output of the block have the same sample rate. In this mode, the block outputs a signal with a proportionally larger frame size than the input. The block upsamples each channel independently by repeating each row of the input matrix L times at the output. For upsampling by a factor of L, the output frame size is L times larger than the input frame size (M_o = M_i*L), but the input and output frame rates are equal.
For an example of single-rate upsampling, see the Single-Rate Processing example in Examples.
When you set the Rate options parameter to Allow multirate processing, the block treats an M_i-by-N matrix input as N independent channels. The block generates the output at the faster (upsampled) rate by using a proportionally shorter frame period at the output port than at the input port. For L repetitions of the input, the output frame period is L times shorter than the input frame period (T_fo = T_fi/L). In this mode, the output always has the same frame size as the input.
See Multirate, Frame-Based Processing example in Examples for an example that uses the Repeat block in this mode.

Sample-Based Processing

When you set the Input processing parameter to Elements as channels (sample based), the block treats an M-by-N matrix input as M*N independent channels, and upsamples each channel over time. The block upsamples each channel over time such that the output sample rate is L times higher than the input sample rate (T_so = T_si/L). In this mode, the output is always the same size as the input.

Zero Latency

The Repeat block has zero-tasking latency for all single-rate operations. The block is in a single-rate mode if you set the Repetition count parameter to 1 or if you set the Input processing parameter to Columns as channels (frame based) and the Rate options parameter to Enforce single-rate processing.

The Repeat block also has zero-tasking latency for multirate operations if you run your model in Simulink^® single-tasking mode.

Zero-tasking latency means that the block repeats the first input (received at t=0) for the first L output samples, the second input for the next L output samples, and so on.

Nonzero Latency

The Repeat block has tasking latency for multirate, multitasking operation:

In multirate, sample-based processing mode, the initial condition for each channel is repeated for the first L output samples. The channel's first input appears as output sample L+1. The Initial conditions parameter can be an M_i-by-N matrix containing one value for each channel, or a scalar to be applied to all signal channels.
In multirate, frame-based processing mode, the first row of the initial condition matrix is repeated for the first L output samples, the second row of the initial condition matrix is repeated for the next L output samples, and so on. The first row of the first input matrix appears in the output as sample M_iL+1. The Initial conditions parameter can be an M_i-by-N matrix, or a scalar to be repeated across all elements of the M_i-by-N matrix.

Note

For more information on latency and the Simulink tasking modes, see Excess Algorithmic Delay (Tasking Latency) and Time-Based Scheduling and Code Generation (Simulink Coder).

Examples

Example 1. Example: Single-Rate Processing

In the ex_repeat_ref2 model, the Repeat block resamples a single-channel input with a frame size of 16. The block repeats input values to upsample the input by a factor of 4. Thus, the output of the block has a frame size of 64. The input and output frame rates are identical.

Example 2. Example: Multirate, Frame-Based Processing

In the ex_repeat_ref1 model, the Repeat block resamples a single-channel input with a frame period of 1 second. The block repeats input values to upsample the input by a factor of 4. Thus, the output of the block has a frame period of 0.25 seconds. The input and output frame sizes are identical.

Parameters

Repetition count

The integer number of times, L, that the input value is repeated at the output. This is the factor by which the block increases the output frame size or sample rate.

Input processing

Specify how the block should process the input. You can set this parameter to one of the following options:

Columns as channels (frame based) — When you select this option, the block treats each column of the input as a separate channel. In this mode, the block can perform single-rate or multirate processing.
Elements as channels (sample based) — When you select this option, the block treats each element of the input as a separate channel. In this mode, the block always performs multirate processing.

Rate options

Specify the method by which the block upsamples the input. You can select one of the following options:

Enforce single-rate processing — When you select this option, the block maintains the input sample rate by increasing the output frame size by a factor of L. To select this option, you must set the Input processing parameter to Columns as channels (frame based).
Allow multirate processing — When you select this option, the block resamples the signal such that the output sample rate is L times faster than the input sample rate.

Initial conditions

The value with which the block is initialized for cases of nonzero latency; a scalar or matrix. This parameter appears only when you configure the block to perform multirate processing.

Supported Data Types

Port	Supported Data Types
Input	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers
Output	Double-precision floating point Single-precision floating point Fixed point (signed and unsigned) Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies on memcpy or memset functions (string.h) under certain conditions.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

The Repeat block uses fewer hardware resources than the Upsample block. If your algorithm does not require zero-padding upsampling, use the Repeat block.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Restrictions

Input processing set to Columns as channels (frame based) is not supported.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a

FIR Interpolation	DSP System Toolbox
Upsample	DSP System Toolbox

Documentation

Repeat

Library

Description

Frame-Based Processing

Sample-Based Processing

Zero Latency

Nonzero Latency

Examples

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

Documentation

Repeat

Library

Description

Frame-Based Processing

Sample-Based Processing

Zero Latency

Nonzero Latency

Examples

Parameters

Supported Data Types

See Also

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.