Use trigger signal as clock

This setting is a parameter in the HDL Code Generation > Global Settings > Ports tab of the Configuration Parameters dialog box.

Settings

Default: Off

On

For triggered subsystems, use the trigger input signal as a clock in the generated HDL code. Make sure that the Clock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.

Off

For triggered subsystems, do not use the trigger input signal as a clock in the generated HDL code.

Command-Line Information

Property: TriggerAsClock
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems within the sfir_fixed/symmetric_fir DUT subsystem, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl ('sfir_fixed/symmetric_sfir','TriggerAsClock','on')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','TriggerAsClock','on')
makehdl('sfir_fixed/symmetric_fir')

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