Generate Reset for Timing Controller

You can generate a reset port for the timing controller, which generates the clock, clock enable, and reset signals in a multirate DUT. In the generated code, the reset for the timing controller is a DUT input port.

Requirements for Timing Controller Reset Port Generation

Your design must use single-clock mode. That is, the ClockInputs property value must be 'Single'.

How To Generate Reset for Timing Controller

To generate a reset port for the timing controller, set the TimingControllerArch property to 'resettable' using makehdl or hdlset_param.

To disable reset port generation for the timing controller, set the TimingControllerArch property to 'default'.

For example, for a model, sfir_fixed, specify a reset port for the timing controller by entering:

hdlset_param('sfir_fixed','TimingControllerArch','resettable')

Limitations for Timing Controller Reset Port Generation

The following workflows are not compatible with timing controller reset port generation:

FPGA Turnkey
FPGA-in-the-Loop
Custom IP core generation

Documentation