Enable HDL DUT port generation for test points

Enable this setting to create DUT output ports for the test point signals in the generated HDL code.

Settings

Default: Off

On: When you enable this setting, the code generator creates DUT output ports for the test point signals in the generated HDL code. You can observe the test point signals and debug your design by connecting a Scope block to the output ports corresponding to these signals.
Off: When you disable this setting, the code generator preserves the test point signals and does not create DUT output ports in the generated HDL code.

Note

The code generator ignores this setting when you designate test points for states inside a Stateflow^® Chart.

Command-Line Information

Property: EnableTestpoints

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, after you designate signals as testpoints for the sfir_fixed/symmetric_fir DUT subsystem, to generate DUT output ports in the HDL code, use either of these methods:

Pass the property as an argument to the makehdl function.

makehdl ('sfir_fixed/symmetric_sfir','EnableTestpoints','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','EnableTestpoints','on')
makehdl('sfir_fixed/symmetric_fir')
```

Documentation