HDL Counter

Free-running or count-limited hardware counter

Library

HDL Coder / Sources

Description

The HDL Counter block models a free-running or count-limited hardware counter that supports signed and unsigned integer and fixed-point data types.

The counter emits its value for the current sample time.

This block does not report wrap on overflow warnings during simulation. To report these warnings, see the Simulink.restoreDiagnostic reference page. The block does report errors due to wrap on overflow.

Control Ports

By default, the counter does not have input ports. Optionally, you can add control ports that enable, disable, load, reset or set the direction of the counter.

The table shows the priority of the control signals and how the counter value is updated in relation to the control signals.

Local reset, `rst`	Load trigger, `load`	Count enable, `enb`	Count direction, `dir`	Next Counter Value
1	–	–	–	initial value
0	1	–	–	`load_val` value
0	0	0	–	current value
0	0	1	1	current value + step value
0	0	1	0	current value - step value

Count direction

The Step value parameter and optional count direction port, dir, interact to determine the actual count direction.

`dir` Signal Value	Step Value Sign	Actual Count Direction
1	+ (positive)	Up
1	- (negative)	Down
0	+ (positive)	Down
0	- (negative)	Up

Parameters

Counter type

Counter behavior.

Free running (default): The counter continues to increment or decrement by the Step value until reset.
Count limited: The counter increments or decrements by the Step value until it is exactly equal to the Count to value.

Initial value

Counter value after reset. The default is 0.

Step value

Value added to counter at each sample time. The default is 1.

Count to value

When the count is exactly equal to Count to value, the count restarts at the Initial value. This option is available when Counter type is set to Count limited. The default is 100.

Count from

Specifies the parameter that sets the start value after rollover. When set to Specify, the Count from value parameter is the start value after rollover. The default is Initial value.

Count from value

Counter value after rollover when Count from is set to Specify. The default is 0.

Local reset port

When selected, creates a local reset port, rst.

Load ports

When selected, creates a load data port, load_val, and load trigger port, load.

Count enable port

When selected, creates a count enable port, enb.

Count direction port

When selected, creates a count direction port, dir.

Counter output data is

Output data type signedness. The default is Unsigned.

Word length

Bit width, including sign bit, for an integer counter; word length for a fixed-point data type counter. The minimum value if Output data type is Unsigned is 1, 2 if Signed. The maximum value is 125. The default is 8.

Fraction length

Fixed-point data type fraction length. The default is 0.

Sample time

Sample time. The default is 1.

This parameter is not available, and the block inherits its sample time from the input ports when any of these parameters is selected:

Local reset port
Load ports
Count enable port
Count direction port

Ports

The block has the following ports:

rst

Resets the counter value. Active-high.

This port is available when you select Local reset port.

Data type: Boolean

load

Sets the counter to the load value, load_val. Active-high.

This port is available when you select Load ports.

Data type: Boolean

load_val

Data value to load.

This port is available when you select Load ports.

Data type: Same as count.

enb

Enables counter operation. Active-high.

This port is available when you select Count enable port.

Data type: Boolean

dir

Count direction. This port interacts with Step value to determine count direction.

1: Step value is added to the current counter value to compute the next value.
0: Step value is subtracted from the current counter value to compute the next value.

This port is available when you select Count direction port.

Data type: Boolean

count

Counter value.

Data type: Determined automatically based on Counter output data is, Word length, and Fraction length.

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline.

Restrictions

If the bitwidth of the input signal to a HDL Counter exceeds the data type limit, the generated HDL code can produce incorrect simulation results. To accommodate the larger bit width, use a larger data type.

Documentation

HDL Counter

Library

Description

Control Ports

Count direction

Parameters

Ports

Extended Capabilities

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

Restrictions

Introduced in R2014a

HDL Coder Documentation

Support

Documentation

HDL Counter

Library

Description

Control Ports

Count direction

Parameters

Ports

Extended Capabilities

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

Restrictions

Introduced in R2014a

HDL Coder Documentation

Support

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.