The transfer function of a CIC decimation filter is

where:

The CIC Decimation HDL Optimized block has the CIC filter structure shown in this figure. The structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters [1].

You can locate the unit delay in the integrator part of the CIC Filter in either the feed-forward or feedback path. These two configurations yield an identical filter frequency response. However, the numerical outputs from these two configurations are different due to the latency of the block. Because, the configuration is preferred for HDL implementation, this block puts the unit delay in the feed-forward path of the integrator.

The block downsamples the integrator stage output using R, either the fixed decimation rate provided using the Decimation factor (R) parameter or the variable decimation rate provided using the decimFactor input port. At the downsampler stage, the block uses a counter to count the valid input samples, which depend on the decimation rate. Whenever the decimation rate changes, the block resets and starts a new calculation from the next sample. This mechanism prevents the block from accumulating false values. Then, the block provides the decimated output to the comb part.

The gain of the block is given by $$Gain={(R\text{x}M)}^N$$,

where:

The block implements gain correction in two parts: coarse gain and fine gain. In coarse gain correction, the block calculates the shift value, adds the shift value to the fractional bits to create a numeric type, and performs a bit-shift left and reinterpretcast. In fine gain correction, the block divides the remaining gain with the coarse gain if the gain is not a power of 2. Then, the block multiplies the corrected coarse gain corrected value with the inverse value of the fine gain. Before the block starts processing, all possible shift and fine gain values are precalculated initially and stored in an array.

You can modify this equation as $$Gain=2^{cGain}\text{x}fGain$$. In this equation, cGain is the coarse gain, and fGain is the fine gain. These gains are given by these equations.

To perform gain correction when the Variable decimation parameter is selected, the block sets the output data type configured with the maximum decimation rate and bit-shifts left for all the values under the maximum decimation rate. The bit-shift value is equal to $${\text{Maximum gain - log}}_{\text{2}}\text{(current gain)}$$.

This section explains how the block outputs data based on the output data type selection. Consider a block with R, M, and N values 8, 1, and 3, respectively, and an input width of 16. The output word length is calculated as $$B_{\text{OUT}}=B_{\text{IN}}+[{\log }_2(Gain)]$$,

where:

When you set the Output data type parameter to Full precision, the block outputs data with a word length of 25 by adding nine gain bits to the input word length of 16.

When you set the Output data type parameter to Same word length as input, the block outputs data with a word length of 16, which is the same length as the input word length. The internal integrator and comb stages use the full-precision data type with 25 bits.

When you set the Output data type parameter to Minimum section word lengths and the Output word length parameter to 16, the block outputs data with a word length of 16. In this case, the block changes the bit width at each stage, based on the Pruning algorithm.

If the Output word length parameter value is less than the number of bits required at the block output, the least significant bits (LSBs) at the earlier stages are pruned. The number of LSBs to discard at each stage is provided in the Hogenauer algorithm [1]. This algorithm minimizes the loss of information in the output data.

This section shows the latencies of the block when operated with fixed and variable decimation rates.

This figure shows the output of the block for the default configuration, that is, a fixed decimation rate with R, M, and N values 2, 1, and 2, respectively. The block returns valid output data at every second cycle based on the fixed Decimation factor (R) value of 2. The latency of the block is 5 clock cycles, and is calculated as 3 + N.

This figure shows the output of the block for a fixed decimation with R, M, and N values 8, 1, and 3, respectively, and with the Gain correction parameter selected. The block returns valid output data at every eighth cycle based on the fixed Decimation factor (R) value of 8. The latency of the block is 15 clock cycles, and is calculated as 3 + N + 9.

This figure shows the output of the block for variable decimation (decimFactor) input port values 2, 4, and 8 and M and N values 1 and 3, respectively. In this case, the Gain correction parameter is cleared. The block returns valid output data at second, fourth, and eight cycles corresponding to the decimFactor port values 2, 4, and 8, respectively. The block accepts decimFactor port value changes only when the valid input port is 1.The latency of the block is 7 clock cycles, and is calculated as 4 + N.

The performance of the synthesized HDL code varies with your target and synthesis options. This table shows the resource and performance data synthesis results of the block with fixed and variable decimation rates when R, M, and N values are 2, 1, and 2, respectively. The generated HDL is targeted to a Xilinx^® Zynq^®- 7000 ZC706 evaluation board.

Resources and frequencies vary based on R, M, and N values and other parameter values selected in the block mask.