BPSK Modulator Baseband

Modulate using binary phase shift keying method

Library

PM, in Digital Baseband sublibrary of Modulation

Description

The BPSK Modulator Baseband block modulates using the binary phase shift keying method. The output is a baseband representation of the modulated signal.

This block accepts a column vector input signal. The input must be a discrete-time binary-valued signal. If the input bit is 0 or 1, respectively, then the modulated symbol is exp(jθ) or -exp(jθ), respectively, where θ represents the Phase offset parameter.

For information about the data types each block port supports, see the Supported Data Types table on this page.

Constellation Visualization

The BPSK Modulator Baseband block provides the capability to visualize a signal constellation from the block mask. This Constellation Visualization feature allows you to visualize a signal constellation for specific block parameters. For more information, see the Constellation Visualization section of the Communications Toolbox™ User's Guide.

Dialog Box

Phase offset (rad): The phase of the zeroth point of the signal constellation.

Output data type

The output data type can be set to double, single, Fixed-point, User-defined, or Inherit via back propagation.

Setting this parameter to Fixed-point or User-defined enables fields in which you can further specify details. Setting this parameter to Inherit via back propagation, sets the output data type and scaling to match the following block.

Output word length

Specify the word length, in bits, of the fixed-point output data type. This parameter is only visible when you select Fixed-point for the Output data type parameter.

Set output fraction length to

Specify the scaling of the fixed-point output by either of the following two methods:

Choose Best precision to have the output scaling automatically set such that the output signal has the best possible precision.
Choose User-defined to specify the output scaling in the Output fraction length parameter.

This parameter is only visible when you select Fixed-point for the Output data type parameter or when you select User-defined and the specified output data type is a fixed-point data type.

User-defined data type

Specify any signed built-in or signed fixed-point data type. You can specify fixed-point data types using the sfix, sint, sfrac, and fixdt functions from Fixed-Point Designer™. This parameter is only visible when you select User-defined for the Output data type parameter.

Output fraction length

For fixed-point output data types, specify the number of fractional bits, or bits to the right of the binary point. This parameter is only visible when you select Fixed-point or User-defined for the Output data type parameter and User-defined for the Set output fraction length to parameter.

Supported Data Types

Port	Supported Data Types
Input	Double-precision floating point Single-precision floating point Boolean 8-, 16-, and 32-bit signed integers 8-, 16-, and 32-bit unsigned integers ufix(1)
Output	Double-precision floating point Single-precision floating point Fixed point (signed only)

Pair Block

BPSK Demodulator Baseband

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Documentation

BPSK Modulator Baseband

Library

Description

Constellation Visualization

Dialog Box

Supported Data Types

Pair Block

See Also

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

Introduced before R2006a

Communications Toolbox Documentation

Support

Documentation

BPSK Modulator Baseband

Library

Description

Constellation Visualization

Dialog Box

Supported Data Types

Pair Block

See Also

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

HDL Block Properties

Introduced before R2006a

Communications Toolbox Documentation

Support

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.