%% Getting Started with RAM and ROM in Simulink(R)
% This example shows how to utilize RAM resources in your FPGA
% design using HDL Coder(TM).

% Copyright 2008-2019 The MathWorks, Inc.

%% Introduction
% Dedicated RAM blocks in FPGA are valuable resources for digital designs.
% It is easy to design with RAM and ROM in Simulink(R), and utilize the
% dedicated RAM blocks available in your FPGA using HDL Coder. 
%

%% RAM Blocks in the HDL Example Library
% HDL Coder provides following types of RAM blocks in the HDL RAMs block
% library. Use |hdllib| to display blocks that are compatible with HDL Coder(TM),
% and then select the |HDL RAMs| library under |HDL Coder|: 
% 
% * Single Port RAM 
% * Single Port RAM System
% * Simple Dual Port RAM 
% * Simple Dual Port RAM System
% * Dual Port RAM
% * Dual Port RAM System
% * Dual Rate Dual Port RAM

% Run this command navigate to RAM blocks in HDL library
% hdllib

%%
% The RAM blocks are masked subsystems built using Simulink blocks for
% behavioral simulation. For code generation, HDL Coder generates
% predefined templates that describe RAM structures in HDL. Most synthesis
% tools recognize the RAM structures in the templates, and map them to RAM
% resources on the FPGA. For more information, see  
% <matlab:helpview(fullfile(docroot,'hdlcoder/modeling-ram-and-rom-blocks.html'))
% HDL Coder Block Library - RAM Blocks> in the documentation.

%% Using Generic RAM Coding Style for RAM Blocks
% By default, HDL Coder provides RAM template that uses clock enable for
% the RAM structures. As an alternative, HDL Coder also provides a style of
% generic template that does not use clock enable. The generic RAM style
% template implements clock enable with logic in a wrapper around the RAM.
% You can control this using 'RAM Architecture' option in the HDL Coder
% global settings panel.
%
% You may want to use the generic RAM style if your synthesis tool does not
% support RAM structures with a clock enable, and cannot map the HDL to
% FPGA RAM resources as a result.
% 
% The example |hdlcoderfirram| is an example of how to use the generic RAM
% style for your design.

open_system('hdlcoderfirram');
open_system('hdlcoderfirram/FIR_RAM');

%% Selecting RAM Coding Style
% The RAM Coding Style is selected by choosing the desired RAM
% Architecture on the "Coding Style" tab of the HDL Code Generation Global
% Settings configuration page.

%% Building a ROM Using Simulink Blocks
% HDL Coder does not provide a ROM block, but you can easily build
% one using a Lookup Table block and a Unit Delay block from Simulink, as
% shown in the following example.

open_system('hdlcoderrom');
open_system('hdlcoderrom/ROM');

%%
% Follow these modeling guidelines when building a ROM from Simulink:
%
% * For an n-bit address, specify all $2^n$ entries of the Lookup Table
% data. Otherwise, your synthesis tool may not map the generated code to
% RAM, and the code may not match your Simulink model.
% * Place the Lookup Table and Unit Delay blocks in the same model
% hierarchy.
% * Support of RAM reset logic varies among FPGA devices and synthesis
% tools. For best synthesis result, suppress the generation of reset logic
% for the Unit Delay block by setting its 'ResetType' property to 'none', in the HDL Block Properties dialog box.
% Also set the 'IgnoreDataChecking' property to 1 in the HDL Test Bench
% configuration parameters to ignore the initial simulation mismatch caused
% by suppressing the reset logic. 
%%
% If you follow the preceding guidelines, most synthesis tools will 
% implement the ROM using dedicated RAM blocks in an FPGA.

%% Minimum RAM Size Requirement
% If the size of the RAM or ROM in your design is small, your synthesis
% tools may map the generated code to registers instead of dedicated RAM
% blocks for better speed performance. Check your synthesis tool for any
% minimum RAM size requirement, and if desired, how you may override that
% requirement.

displayEndOfDemoMessage(mfilename)
