%% Save Target Hardware Settings in Model
% This example shows how to save your target hardware settings in a 
% Simulink(R) model. 

% Copyright 2012-2020 The MathWorks, Inc.

%%
%
% This example also shows different ways that you can export, modify, and import target
% hardware settings. This example uses the Xilinx Zynq platform, 
% but in the same way, you can save target hardware settings in models 
% that target the Intel SoC devices, FPGA Turnkey, and Simulink Real-Time FPGA I/O boards.
%
%% Open the Model
%
open_system('hdlcoder_led_blinking');

%% Configure the Target Hardware Settings
% 
% When you configure the target hardware settings, you
% modify the model. If you save the model, the target hardware settings are
% saved as part of the model.
%
% You can configure the target hardware settings in three ways:
%
% 
% * HDL Workflow Advisor
% * HDL Block Properties dialog box for Inport or Outport
% * |hdlset_param|
%
% Since the HDL Workflow Advisor provides a dropdown menu for each
% target hardware option, it is best to use the HDL Workflow
% Advisor when you configure the target hardware settings for the first
% time. After you save the model with a valid configuration, you can view,
% modify, and apply settings from the command line.
%
% _*Use HDL Workflow Advisor to configure model or port hardware settings*_
%
% Open the HDL Workflow Advisor from the subsystem
% |hdlcoder_led_blinking/led_counter| and specify your target hardware
% settings in tasks 1.1 and 1.2. 
%
% In the *Set Target* > *Set Target Device and Synthesis Tool* task:
% 
% * For *Target workflow*, select |IP Core Generation|.
% * For *Target platform*, select |Xilinx Zynq ZC702 evaluation kit|.
% 
% In the *Set Target* > *Set Target Interface* task, map the
% ports to interfaces as follows:
%
% * For *Blink_frequency* and *Blink_direction* input ports, select the AXI4-Lite interface. 
% * For the *LED* output port, select |External Port|.
% * For the *Read_back* output port, select the AXI4-Lite interface.
%
% <<hdlcoder_interfaceSaving_interface1.png>>
%
% Specify HDL IP core name and version in task 3.2 *Generate RTL Code and IP Core*. 
% 
% <<hdlcoder_interfaceSaving_ipsettings.png>>
%
% For details, see <docid:hdlcoder_ug#example-hdlcoder_ip_core_tutorial_zynq>.
%
% _*Use HDL Block Properties dialog box to map DUT ports to target interface*_
%
% You can specify target interface settings for the DUT interface by using the HDL Block
% Properties dialog box for any Inport or Outport. You can also specify the HDL IP core 
% settings by using the HDL Block Properties dialog box for the DUT
% subsystem. However, you can use the HDL
% Block Properties dialog box to configure only the DUT target interface and HDL IP core settings.
% Set other target hardware settings from the HDL Workflow Advisor, or by using |hdlset_param| at the
% command line.  
%
% For example, you can change the bit range of the *Blink_frequency* Inport to x"120" 
% and remap the *LED* Outport to LEDs General Purpose [0:7]:
%
% # From the subsystem |hdlcoder_led_blinking/led_counter|, right-click the *Blink_frequency* Inport, 
% and select *HDL Code* > *HDL Block Properties*. Click the *Target Specification* Tab. 
% For *IOInterfaceMapping*, enter |x"120"|. 
% # Similarly, for the *LED* Outport, for *IOInterface*, enter |LEDs General Purpose [0:7]|.
%
% <<hdlcoder_interfaceSaving_interface3.png>>
%
% Right-click the subsystem |hdlcoder_led_blinking/led_counter|, and select 
% *HDL Code* > *HDL Block Properties*. Note you can change *IPCoreName* and
% *IPCoreVersion* under *Target Specification* Tab. 
% 
% <<hdlcoder_interfaceSaving_ipsettings2.png>>
%
% The target interface and HDL IP core settings you
% specify using the HDL Block Properties dialog box are validated when you
% open the HDL Workflow Advisor.
%
% _*Use hdlset_param to configure model or DUT port hardware settings*_
%
% To configure target hardware settings for your model or DUT ports, you can 
% use |hdlset_param|. 
%
% For example, to change the *TargetPlatform* to Xilinx Zynq ZC706
% evaluation kit, enter:
%
%   hdlset_param('hdlcoder_led_blinking', 'TargetPlatform', 'Xilinx Zynq ZC706 evaluation kit');
%
% To set the Bit Range of *Blink_frequency* Inport to |x"120"|; 
% and set the *LED* Outport to |LEDs General Purpose [0:7]|, enter:
%
%   hdlset_param('hdlcoder_led_blinking/led_counter/Blink_frequency', 'IOInterfaceMapping', 'x"120"');
%   hdlset_param('hdlcoder_led_blinking/led_counter/LED', 'IOInterface', 'LEDs General Purpose [0:7]');
%
% To set the IP core name and version, enter:
%
%   hdlset_param('hdlcoder_led_blinking/led_counter', 'IPCoreName', 'my_ipcore');
%   hdlset_param('hdlcoder_led_blinking/led_counter', 'IPCoreVersion', '2.0');
%
%% Export and Import Target Hardware Settings
% To export all non-default HDL code generation options in your model,
% including the target hardware settings, you can use *hdlsaveparams* and
% *hdlrestoreparams*. You can modify the model settings in the saved
% MATLAB file, and apply the settings to the same model or to a different
% model.
%
% For example, to export the settings from the hdlcoder_led_blinking model to a MATLAB file, |targetSetting.m|,
% enter:
%
%   hdlsaveparams('hdlcoder_led_blinking/led_counter','targetSetting.m')
%
% You can modify the settings in |targetSetting.m| as desired, then enter
% the following command to apply the settings to the model:
%
%   hdlrestoreparams('hdlcoder_led_blinking/led_counter','targetSetting.m')
% 
%% Save and Reopen the Model
% # Save the model |hdlcoder_led_blinking| as |hdlcoder_led_blinking_saved|.
% # Open the saved model, |hdlcoder_led_blinking_saved|.
% # Open the HDL Workflow Advisor from the subsystem
% |hdlcoder_led_blinking_saved/led_counter|.
%
% Notice that the modified settings are automatically loaded to tasks 1.1 and 1.2 in
% the HDL Workflow Advisor.
%
% <<hdlcoder_interfaceSaving_interface4.png>>

displayEndOfDemoMessage(mfilename)
