%% Generate Simulink(R) Model From CORDIC Atan2 Verilog(R) Code
% This example shows how you can import a file containing Verilog code and
% generate the corresponding Simulink model by using the |importhdl|
% function. |importhdl| imports and parses the specified Verilog files to
% generate the corresponding Simulink model. The Verilog code in this example
% contains a CORDIC atan2 algorithm.

% Copyright 2019 The MathWorks, Inc.

%% CORDIC 2-Argument Arctangent (atan2) Verilog Design
% This Verilog input file implements a CORDIC atan2 algorithm.
cordic_atan2_verilog_file = fullfile(matlabroot, 'toolbox', 'hdlcoder', 'hdlcoderdemos', 'cordic_atan2.v');
type(cordic_atan2_verilog_file);
%%
% This Verilog design contains various commonly used Verilog constructs
% such as:
%
% * Continuous assignments
% * Always blocks
% * Conditional Statements
% * Module instantiation
% * Generate Constructs
% * For Loop

%% Import HDL File Containing CORDIC atan2 Algorithm
% To import the Verilog file, specify the file name as an argument to the
% |importhdl| function.
importhdl(cordic_atan2_verilog_file);
%%
% |importhdl| parses the input file and displays messages of the import process
% in the MATLAB(TM) Command Window. The import provides a link to the generated
% Simulink model |cordic_atan2.slx|. The generated model uses the same
% name as the top module in the input Verilog file.
%% Examine Generated Simulink Model
% To open the generated Simulink model, click the link in the Command Window.
% The model is saved in the |hdlimport/cordic_atan2| path relative to the current folder.
% You can simulate the model and observe the simulation results.
open_system('hdlimport/cordic_atan2/cordic_atan2')
Simulink.BlockDiagram.arrangeSystem('cordic_atan2')
set_param('cordic_atan2', 'UnconnectedOutputMsg', 'None');
sim('hdlimport/cordic_atan2/cordic_atan2.slx');

%% Generated Module instances
% The Verilog code instantiates |15| kernel modules by using the generate
% construct. In the generated Simulink model, |15| kernel modules are seen.
%%
%
% generate
% for (i = 0; i<15; i =i+1)
% begin
% Kernel cordic_iterator (.clk(clk),
% .reset(reset),
% .enable(enable),
% .itr_num(i),
% .x_in(x_k[i]),
% .y_in(y_k[i]),
% .z_in(z_k[i]),
% .lut_constant(LUT[i]),
% .x_out(x_k[i+1]),
% .y_out(y_k[i+1]),
% .z_out(z_k[i+1]));
% end
% endgenerate
%
%
%
%%
% <<importhdlGenerateConstruct.png>>

%% Simulink model for the Kernel Module
%
%
% module Kernel(
% input clk,
% input reset,
% input enable,
% input signed [17:0]x_in,
% input signed [17:0]y_in,
% input signed [17:0]z_in,
% input [4:0]itr_num,
% input signed [15:0]lut_constant,
% output reg signed [17:0]x_out,
% output reg signed [17:0]y_out,
% output reg signed [17:0]z_out);
%
% wire signed [17:0] lut_constant_signExtension = {{2{lut_constant[15]}},lut_constant};
%
% always @(posedge clk)begin
% if(reset)begin
% x_out <={18{1'b0}};
% y_out <={18{1'b0}};
% z_out <= {18{1'b0}};
% end
% else if(enable)begin
% if(y_in[17])begin
% x_out <= x_in -(y_in>>>itr_num);
% y_out <= y_in + (x_in>>>itr_num);
% z_out <= z_in - lut_constant_signExtension;
% end
% else begin
% x_out <= x_in +(y_in>>>itr_num);
% y_out <= y_in - (x_in>>>itr_num);
% z_out <= z_in + lut_constant_signExtension;
% end
% end
% end
%
% endmodule
%%
% <<importhdlKernelModule.png>>

%% References
%
% * <docid:hdlcoder_ref#mw_c87ae455-535c-4a9a-aadc-e1ac45322bcc>
% * <docid:hdlcoder_ug#mw_99fcb397-3e6e-4028-8e10-d2db06374a2a>