%% Distributed Pipelining: Speed Optimization
% This example shows how to use distributed pipelining to optimize a design
% for speed in HDL Coder.
 
%% Introduction
% Distributed pipelining is a subsystem-wide optimization supported by HDL 
% Coder for achieving high clock speed hardware. By turning on 'Distributed 
% Pipelining', the coder redistributes the input pipeline registers, output
% pipeline register of the subsystem and the registers in the subsystem to
% appropriate positions to minimize the combinatorial logic between registers 
% and maximize the clock speed of the chip synthesized from the generated 
% HDL code.
%
% Consider the following example model of a symmetric FIR filter. The 
% combinatorial logic from an input or a register to an output or another register
% contains a product block and an adder tree. Distributed pipelining will move 
% the output registers set at the subsystem level to reduce the levels of the 
% combinatorial logic.
 
%   Copyright 2010-2012 The MathWorks, Inc.
 
bdclose all;
load_system('sfir_fixed');
open_system('sfir_fixed/symmetric_fir');
 
%% Setting Output Pipeline Stage
% To increase the clock speed, the user can set a number of pipeline stages 
% for any subsystem. Without turning on distributed pipelining, the 
% specified number of registers will be added to each of the output ports 
% of the subsystem. Some synthesis tools support features like retiming
% that optimize the position of the registers during synthesis.  
%
% In this example, the subsystem output pipeline register is set to 5.
%
% The code-generation model explicitly reflects the inserted register at 
% output ports of the subsystem(highlighted in orange). 
 
hdlset_param('sfir_fixed/symmetric_fir', 'OutputPipeline', 5);
makehdl('sfir_fixed/symmetric_fir');
open_system('gm_sfir_fixed/symmetric_fir');
set_param('gm_sfir_fixed', 'SimulationCommand', 'update');
 
%% Setting Distributed Pipelining
% Distributed pipelining is one of the subsystem block options. Once turned
% on, the registers in the subsystem, including output pipeline registers 
% and input pipeline registers, will be repositioned to achieve best clock 
% speed. It is equivalent to retiming at subsystem level. 
%
% The code-generation model explicitly reflects the distributed registers 
% in the subsystem (highlighted in orange). 
 
hdlset_param('sfir_fixed/symmetric_fir', 'DistributedPipelining', 'on');
makehdl('sfir_fixed/symmetric_fir');
open_system('gm_sfir_fixed/symmetric_fir');
set_param('gm_sfir_fixed', 'SimulationCommand', 'update');
 
%% Opportunities for Distributed Pipelining Across Subsystem Hierarchies
% Since 'Distributed Pipelining' is a subsystem-level parameter, different
% subsystems at different levels of the hierarchy can specify different
% pipeline stage values and different 'Distributed Pipelining' settings. 
% By default, the coder distributes only registers of the specified 
% subsystem in this subsystem, not through the lower level subsystems. If 
% cross hierarchy distribution is desired, users can set the 'Distributed 
% Pipelining' for lower subsystems to 'On', then turn on the global option 
% 'Hierarchical Distributed Pipelining'. When the local and global options 
% are on, the entire subsystem, including the lower level subsystems, will 
% be considered as a single subsystem when registers are distributed.  

bdclose all;
displayEndOfDemoMessage(mfilename)


