
\msection{Introduction to gem5}{Brad Beckmann}

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\frametitle{Introduction to gem5}

\bi 
\item What is gem5?
\bi
\item The \emph{best} parts of M5
\item The \emph{best} parts of GEMS
\ei
\vskip30pt
\item Overall goals, design principles, and capabilities
\ei
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\frametitle{What is gem5?}

\bi 
\item The combination of M5 and GEMS into a new simulator
  \bi
  \vskip15pt
  \item Google scholar statistics
    \bi 
    \item M5 (IEEE Micro): \textbf{304} citations
    \item GEMS (CAN): \textbf{588} citations
    \ei
  \vskip15pt
  \item Best aspects of both glued together
    \bi 
    \item M5: CPU models, ISAs, I/O devices, infrastructure
    \item GEMS (essentially Ruby): cache coherence protocols, interconnect models
    \ei
  \ei
\ei
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\begin{frame}
\frametitle{What else is new?}
\bi
\item Many other things have changed since previous tutorials beyond GEMS+M5
\vskip15pt
\item Some of the highlights:
    \bi
    \item The world's most popular ISAs: ARM and x86
    \item The In-order CPU model
    \item New documentation
    \ei
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\item Overall gem5 has a high degree of capabilities
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\frametitle{Android on ARM FS}
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\frametitle{What gem5 is  \emph{Not}}

   \bi 
   \item A hardware design language
      \bi 
      \item Higher level for design space exploration, simulation speed
      \ei
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   \item A restrictive environment
      \bi 
      \item Just \CC\ and Python with an event queue and a bunch of APIs you can choose to ignore
      \ei
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   \item Finished!
      \bi 
      \item Always room for improvement \ldots
      \ei
   \ei
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\frametitle{What We Would Like gem5 to Be}

   \bi 
   \item Something that spares you the pain we've been through
   \item A community resource
      \bi 
      \item Modular enough to localize changes
      \item Contribute back, and spare others some pain
      \ei
   \item A path to reproducible/comparable results
      \bi 
      \item A common platform for evaluating ideas
      \ei
   \item Let us know how we can help you contribute
      \bi 
      \item Public wiki is up at http://www.gem5.org
%      \item Public repository access now available
      \item \emph{Please} submit patches and additional features 
      \item Ability to add modules with \texttt{EXTRAS=}
      \item The more active the community is, the more successful gem5 will be!
      \ei
   \ei
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\begin{frame}
\frametitle{Will gem5 do what I want?}
\bi
\item Maybe!
\vskip15pt
\item The gem5 simulator already does many generally useful things.
\vskip15pt
\item It has code for things other people have needed before.
\vskip15pt
\item Almost all users are also developers.  
\vskip15pt
\item You'll likely need to do some development to customize/extend gem5 for your project.
\ei
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\begin{frame}
\frametitle{Two Views of gem5}
\begin{block}{View \#1}
\bi 
\item A framework for event-driven simulation
\bi
\item Events, objects, statistics, configuration
\ei
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\begin{block}{View \#2}
\bi
\item A collection of predefined object models
\bi
\item CPUs, caches, busses, devices, etc.
\ei
\ei
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\bi 
\item This tutorial focuses on \#2
\item You may find \#1 useful even if \#2 is not
    \bi
    \item At least three other ``simulators'' have been created using \#1
    \ei
\ei
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\begin{frame}
\frametitle{Main Goals}
\color{red} Overall Goal: \emph{Open source community tool focused on architectural modeling}
   \vskip2pt
   \bi 
   \item Flexibility
      \bi 
      \item Multiple CPU models across the speed vs. accuracy spectrum
      \item Two execution modes: System-call Emulation \& Full-system
      \item Two memory system models: Classic \& Ruby
      \item Once you learn it, you can apply to a wide-range of investigations
      \ei
   \item Availability
      \bi 
      \item For both academic and corporate researchers
      \item No dependence on proprietary code
      \item BSD license
      \ei
   \item Collaboration
      \bi 
      \item Combined effort of many with different specialties
      \item Active community leveraging collaborative technologies
      \ei
   \ei
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\frametitle{Key Features}
   \bi 
   \item Pervasive object-oriented design
      \bi 
      \item Provides modularity, flexibility
      \item Significantly leverages inheritance  \emph{e.g. SimObject}
      \ei
   \vskip2pt
   \item Python integration
      \bi 
      \item Powerful front-end interface
      \item Provides initialization, configuration, \& simulation control 
      \ei
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   \item Domain-Specific Languages
      \bi 
      \item ISA DSL: defines ISA semantics
      \item Cache Coherence DSL (a.k.a.\textbf{SLICC}): defines coherence logic
      \ei
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   \item Standard interfaces: \texttt{Ports} and \texttt{MessageBuffers}
   \ei
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\frametitle{Capabilities}
   \bi 
   \item \textbf{Execution modes}: System-call Emulation (SE) \& Full-System (FS)
   \item \textbf{ISAs}: Alpha, ARM, MIPS, Power, SPARC, x86
   \item \textbf{CPU models}: AtomicSimple, TimingSimple, InOrder, and O3
   \item \textbf{Cache coherence protocols}: broadcast-based, directories, etc.
   \item \textbf{Interconnection networks}: Simple \& Garnet (Princeton, MIT)
   \item \textbf{Devices}: NICs, IDE controller, etc.
   \item \textbf{Multiple systems}: communicate over TCP/IP
   \ei
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\frametitle{Cross-Product Matrix}
\begin{tabular}{|c|c||c|c|c|}
\hline
\multicolumn{2}{|c||}{\textbf{Processor}} & \multicolumn{3}{|c|}{\textbf{Memory System}} \\
\hline
\multirow{2}{*}{CPU Model} & \multirow{2}{*}{System Mode} & \multirow{2}{*}{Classic} & \multicolumn{2}{|c|}{Ruby} \\
& & & Simple & Garnet \\
\hline
\hline
\multirow{2}{*}{Atomic Simple} & SE & & & \\
& FS & & & \\
\hline
\multirow{2}{*}{Timing Simple} & SE & & & \\
& FS & & & \\
\hline
\multirow{2}{*}{InOrder} & SE & & & \\
& FS & & & \\
\hline
\multirow{2}{*}{O3} & SE & & & \\
& FS & & & \\
\hline
\end{tabular}
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