# MODELS

MODELNAME: soc_OFDM_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_OFDM_top.slx
BLOCKTYPE_FREQUENCY: 1;1;2;2;17;2;14;1;1;1;2;2
CHECKSUM: D1C5F4A6EB97393DA0CAE4635CF1D86F
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_OFDM_fpga.slx___Model_Block___soc_OFDM_proc.slx___Model_Block___
ANNOTATION:
<!DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.0//EN http://www.w3.org/TR/REC-html40/strict.dtd> <html><head><meta name=qrichtext content=1 /><style type=text/css> p, li { white-space: pre-wrap; } </style></head><body align=left style= font-family:Arial; font-size:12px; font-weight:400; font-style:normal;>   OFDM Transmit and Receive Using Xilinx RFSoC Device FPGA Memory Processor <!DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.0//EN http://www.w3.org/TR/REC-html40/strict.dtd> <html><head><meta name=qrichtext content=1 /><style type=text/css> p, li { white-space: pre-wrap; } </style></head><body align=left style= font-family:Arial; font-size:12px; font-weight:400; font-style:normal;> Copyright 2020-2023 The MathWorks, Inc. External I/O External I/O

BLOCK:
AXI4-Stream to Software;Data;Delay;Enable;EstimatedCFO;FPGA Algorithm;IO Data Sink;Processor;Processor-Frame based processing;RF Data Converter;RF Loopback;Reference;Register Write;Rx UDP Write;RxData;Status UDP Write;SubSystem;Task Manager;Terminator;UDP Write;UDP Write ;adc;codeRate;dac;data;dataReadTaskEvent;decodedCodeRate;decodedModType;displayReset;done;enableCPECCorrec;enableChanEqui;enableInternalLoopback;headerView;insertCFO;modType;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived;packetValid;snrdB;statusUDPReport

BLOCKTYPE:
AXI4-Stream to Software;Delay;EnablePort;IO Data Sink;Inport;ModelReference;Outport;RF Data Converter;Register Channel;Task Manager;Terminator;UDP Write

PRODUCT:
DSP System Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_WLAN_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_WLAN_fpga.slx
CHECKSUM: 58DF30E7A8480121A6A2B45C55A4E08B
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
NO HDL Block NO HDL Block  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. 1/(numSCs*modOrder*codeRate) numSCs*modOrder*codeRate numSCs*modOrder Calculating PSDU len for VHT frame using initial 25bits of VHT SigB Dectecting CRC on first 19 bits Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Accumulated delay for reset to match both Deinterleaver outputs choose output based on block size Deinterleaver for Non-HT frame with block size 48  Deinterleaver for HT/VHT frame with block size 52  poly: 1 0 0 1 0 0 0 Selecting BPSK and 1/2 rate coding for VHT Signal B field  decoderInpLen = ceil((psduLen+22)/(numSCs*modOrder*codeRate))*(numSCs*modOrder) codeRate modSel numSCs*modOrder 1/(numSCs*modOrder*codeRate) Appriopriate delays to match detected frame format arrival Choose L-Data from symbol 6  Calculate the Rx time from L-sig bits for VHT frame format Compute the number of OFDM data symbols for VHT frame format Choose bits from 25 to end for VHT Sig parameters Choose bits from 25 to 65 for CRC detection Threshold chose as half of used subcarriers in signal fields Delays to match arrival of MCS Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW  Choose L-SIG, HT-SIG and VHT-SIG based on format detected Choose BPSK   choose L Sig For QBPSK Choose QBPSK  Storing OFDM symbol 6 and 7 until frame format detection is completed  Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) reference pilots are stored in LUT for 4 symbols pilots for 4 symbols are stored to avoid modulo operation  Counter for pilot Subcarriers for 4 Symbols  delay the adder output till the end of Symbol delay value = Maximum Used subcarrier- Last pilot Subcarrier position  add the pilots; reset the pilots for every Symbol Multiply the Equalizer Output with reference pilots  Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output  Choose polarity 1 for VHT Sig B Choose ZStart based on Format detected selecting Data field for equalization Delay by 1 OFDM Symbol time Selecting 9th symbol i.e., HT/VHT LTF after OFDM demod  Sending chan est as 1 when valid is low to channel equalizer Select VHTSigB symbol for frame format 2 Selecting only VHT data for frame format 2 Delay by 1.4 times OFDM symbol length to match frame format detected HT/VHT scaling factor  Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) reference pilots are stored in LUT for 4 symbols pilots for 4 symbols are stored to avoid modulo operation  Counter for pilot Subcarriers for 4 Symbols  delay the adder output till the end of Symbol delay value = Maximum Used subcarrier- Last pilot Subcarrier position  add the pilots; reset the pilots for every Symbol Multiply the Equalizer Output with reference pilots  Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers (65 for 20Mhz)   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output   Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output  Choose polarity 1 for L-SIG selecting from L-SIG field to L-Data for equalization Delay by 1 OFDM Symbol time Sending chan est as 1 when valid is low to channel equalizer Selecting LLTF 1 and 2 for channel estimation  Non-HT scaling factor Select Non-HT frame format used subcarriers Searching peak in LSTF region Upsample by 8 for 20MHz and 4 for 40MHz is used for Resource Sharing in the Discrete FIR filter  delayLen=filterUpsampleFactor-1  Latency = (coeffLen/filterUpsampleFactor)+filterUpsampleFactor+9 Inputs are sampled only when counter reach zero  LUT Index is selected based on Frame Format and MCS  Inputs are sampled only when counter reach zero  LUT Index is selected based on Frame Format and MCS   1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  Generate Status Signals to monitor Outside FPGA WLAN Transmit and Receive Status Signal Generator  Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;2-D Lookup Table;<valid>;AND;Abs;Add;Add Constant;Bit Clear;Bit Concat;Bit Set;Bit Shift;Bus Creator;Bus Selector;C;CPECorrector;CPEEstimator;CRCCheck;CRCCheckAndBitInterpretation;ChannelEqualizer;ChannelEstimator;Coarse CFO Correction;Coarse CFO Estimation;Coarse CFO Estimation and Correction;Coarse Time Sync;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Concatention;Conjugate;Constant;Constellation Formation;Conversion;DTConverter;DTadjust;Data Constellation Diagram;Data Symbols;Data Type Conversion;DataRecovery;DataSubCarrierSelector;DataValid;DeInterleaver_HT;DeInterleaver_NonHT;Decimate_20MHz;Decimate_40MHz;Decimator;Decoder;Deinterleaver;Deinterleaver Block;Delay;Depuncturer;DepuncturerCtrlGen;Descrambler;Diagnostic Decoder;Direct Lookup Table (n-D);Discrete FIR Filter HDL Optimized;Divide;Downsample;Enable;Enabled Delay;EqValidIn;Extract Bits;FIR Decimation HDL Optimized;FIR Decimator;FIR Interpolator;Fine CFO Correction;Fine CFO Estimation;Fine CFO Estimation and Correction;Fine Time Sync;FormatIdentification;Frame Format ;FrameFormatController;FrameFormatDetectionAndSignalRecovery;Freq;From;Function Impl;Gain;General CRC Generator HDL Optimized;General CRC Syndrome Detector HDL Optimized;Generate Base Read Address;Generate Current Frame Status;Generate Forced End;Generate Output Control Signals;Generate Read Address;Generate Ready;Generate Write Address;Goto;HDL Counter;HTCRCStatus;HTDataIn;HTRst;HTScSelector;HTSigBitRecover;HTSigCRCCheck;HTValid;HT_VHTCPEEstAndCorrection;HT_VHTChannelEstAndEqualize;HT_VHTchanEst;HT_VHTchanEstValid;Handle Input Control Signals;Header Constellation Diagram;In;Initial Seed;LSTF_start;LSigBitRecover;LUT;LUTAddr;LUTSelect;Logical Operator;MATLAB Function;MCS;MagnitudeSquared;Math Function;MovingSum;Multiport Switch;NCO HDL Optimized;NOT;NonHTCPEEstAndCorrection;NonHTChannelEstAndEqualize;NonHTDataIn;NonHTDataSelector;NonHTRst;NonHTScSelector;NonHTValid;OFDM Channel Estimator;OFDM Demodulator;OFDM Equalizer;OFDMDemodParamsCalculator;OFDMDemodulation;OR;Out;Outport;PSDULen;PSDULenNonHT;PSDULength;PilotSubCarrierSelector;PolarityGenerator;Prepare Inputs;Prepare Outputs;Product;RAM;Read Address of Deinterleaver;Read Address of Interleaver;Read Logic;Real-Imag to Complex;Reciprocal;RefPilotsOut;Reference;RefrenceSignalGen;Relational Operator;Repeat;Rx Filter;RxDataI_In;RxDataQ_In;RxData_Out;RxValidOut;RxValid_In;RxValid_Out;Sample Control Bus Creator;Sample Control Bus Selector;Shift Arithmetic;SignalBitRecovery;SignalFieldController;Simple Dual Port RAM;Stage;Stage 2 16QAM ;Stage 2 64QAM;Stage 2 BPSK;Stage 2 QPSK;State Control;Store Block Lengths;SubSystem;Subtract;Sum;Switch;SymbEndInd;SymbStart;Symbol Counter;Symbol Demodulator;SymbolEndInd;Synchronous Enabled 16 Sample Delay ;Synchronous Enabled Unit Delay;Terminator;To Workspace;TxDataI_Out;TxDataQ_Out;TxValid_Out;Tx_LUT_Selection;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;VHT SignalB CRC Check;VHTSigB;VHTSigBCRCStatus;VHTSigBMCS;VHTSigBitRecover;VHTSigCRCCheck ;VHTSigCRCStatus;ValidController;Vector Decimation;Vector Decimator;Vector Interpolation;Visualize Data Constellation;Visualize Header Constellation;Viterbi Decoder;ViterbiDecoder;WLAN;WLAN HDL;WLANHDLReceiver;WLANTimeAndFrequencySynchronization;WLAN_Rx;WLAN_Tx;WLAN_Tx_20MHz;WLAN_Tx_40MHz;WLAN_Tx_Rx;Write Logic;advPop;averageSigFieldsFor40MHz;averageVhtSigBbits;averager;averaging unit;avgCorr;baseAddr;bit;blockCount;blockDataCount;blockLen;blockValid;bps;chCtrlIn;chCtrlOut;chanEst;chanEstLen;chanEstVal;chanEstValid;codeRate;codeRateIn;codeRateOut;colCounter;complexConj;complexConjugate;considerFirstPeak;corrFilter;corrIn;corrOut;corrValid;corrValidIn;correlator;count;countEnb;countRst;countVal;countValue;counterRst;cpLen;ctrl;ctrlGen;ctrlIn;ctrlOut;currentAddr;dPoints;dValid;data constellation points;dataBits;dataConst;dataConstValid;dataConstellation;dataConstellationValid;dataIOut;dataI_in;dataIn;dataOut;dataQOut;dataQ_in;dataSCValid;dataScValidOut;dataSelector ;dataValid;decodedMCS;decoderInpLen;delayedCorrelation;diagBus;diagBusControl;din_img;din_real;dout;en;enable;enb;end;endIn;endOut;endReady;energy;energyCalculator;energyIn;energyOut;estimate;extractLTFs;failCheck;fftLen;fifoCount;fifoData;forcedEnd;format;formatDetected;formatIn;formatOut;frameFormat;frameFormatIn;frameFormatMapping;frameFormatOut;frameOn;freq;freqIn;freqOff;freqOffset;freqOut;freqValidIn;freqValidOut;functionValues;hPoints;hValid;hView;header constellation points;headerConst;headerConstellation;headerConstellationValid;headerView;in;interpretVHTSigB;isQBPSK;lgSc;llr;load;loadH;loadIn;lstfStart;lstfStartIn;lstfStartOut;lstf_start;magnitudeSquared;mapmodSelTobps;maxPeak;maxPeakSearcher;maxPeakVal;maxPeakValue;modSel;modSelIn;modSelOut;numOFDMSymbVHT;numOFDMSymbolCalVHT;numSCS;numSCSFlag;numSCSOut;numSCs;numSCsConverter;numSCsIn;numSCsOut;numSTS;numSymb;out;packetDetected;packetOut;peakDetection;peakDetector;peakIn;peakOut;peakSearcher;pilotScValid;pilotScValidOut;polarity;pop;psduLen;psduLenOut;psduLength;puncVec;puncVecSelector;push;rateMapping;rdAddr;rd_dout;readStart;ready;readyCounter;reset;resetOut;rgSc;rowCounter;rst;rstIn;rstOut;rxBits;rxData;rxDataIn;rxDataOut;rxTimeVHT;rxValid;rxValidIn;rxValidOut;sample counter;sampleAndHold;sampleIn;sampleParallel;searchStartOfFrame;signBit;signalCRCStatus;signalParity;signalParityStatus;start;startIn;startOut;storingSignalFields;streamSynchrnizer;switch;symbCount;symbNum;symbNum ;symbNumOut;symbRst;symbol counter;symbolDemodulator;symbolRst;syncEn;syncOut;syncStart;thresholdValid;trigger;txData;txDataOut;txIData;txQData;txValid;txValidOut;txvalid;u;updatedPsduLen;valid;validData;validForEqualization;validIn;validOut;vhtCRCRefBit;vhtCRCRefBitValid;vhtCRCRefBitVld;vhtCRCRefBits;vhtCRCRefBitsVld;vhtCRCVld;vhtRotation;vhtSigB;vhtSigBBitVld;vhtSigBDecoding;vhtSigBVld;vhtSigCRCBit;vhtSigCRCVld;vitInputLen;vitInputLenCalc;vitOut;vout;wrAddr;wrValid;wr_din;x;y

BLOCKTYPE:
Abs;ArithShift;Bias;Bit Clear;Bit Concat;Bit Set;Bit Shift;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Depuncturer;Discrete FIR Filter;DownSample;EnablePort;Extract Bits;FIR Decimator;FIR Interpolator;From;Gain;General CRC Generator HDL Optimized;General CRC Syndrome Detector HDL Optimized;Goto;HDL Counter;HDL_FIFO;Inport;Logic;LookupNDDirect;Lookup_n-D;Math;MultiPortSwitch;NCO;OFDM Channel Estimator;OFDM Demodulator;OFDM Equalizer;Outport;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;Sample Control Bus Creator;Simple Dual-port RAM;StateControl;Sum;Switch;Symbol Demodulator;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;Viterbi Decoder

BLOCKTYPE_FREQUENCY:
2;22;2;1;1;1;2;1;1;3;3;188;13;4;9;275;2;48;1283;39;1;2;15;2;7;2;1;39;11;1;1;39;170;9;958;420;44;22;7;24;2;2;1;2;855;70;5;102;16;39;6;16;2;114;109;4;70;4;2;59;6;2

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Wireless HDL Toolbox


MODELNAME: soc_WLAN_hostUDPReceive
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_WLAN_hostUDPReceive.slx
ANNOTATION: WLAN Receiver Host UDP Receive Model Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;1;10;7;2;3;14;1;7;2
CHECKSUM: 52BB6929902D54E4C6627DC85924188B
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Bit Slice;Constellation Diagram;Control Scope;Data Type Conversion;Display;Enable;In;Real-Imag to Complex;Reference;Selector;Status Signals;SubSystem;UDP Receive Constellation;UDP Receive Status;Visualize Constellation;decodedMCS;frameFormat;freqOffset;packetDetected;psduLen;signalCRCStatus;signalParityStatus;statusSignals

BLOCKTYPE:
Bit Slice;ConstellationDiagram;DataTypeConversion;Display;EnablePort;Inport;Outport;RealImagToComplex;Selector;UDP Receive


MODELNAME: soc_WLAN_hwtop
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_WLAN_hwtop.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc. External I/O WLAN Receive Hardware with RFSoC FPGA
BLOCKTYPE_FREQUENCY: 2;1;1;5;1;3;1;7;1;2;1;1;1;1;1;1
CHECKSUM: BAC980260AC65E62439C2269E95B7706
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_WLAN_fpga.slx___Model_Block___
BLOCK:
Bit Slice;Constant;Constellation Diagram;Data Type Conversion;Delay;Display;Enable;FPGA Algorithm;MCS;Manual Switch;RF Data Converter;RF Loopback;Real-Imag to Complex;Reference;SoC Bus Creator;SoC Bus Selector;SubSystem;Terminator;Visualize Constellation;adc;dac;frameFormat;input

BLOCKTYPE:
Bit Slice;Bus Creator;Bus Selector;Constant;ConstellationDiagram;DataTypeConversion;Delay;Display;EnablePort;Inport;ManualSwitch;ModelReference;Outport;RF Data Converter;RealImagToComplex;Terminator

PRODUCT:
Communications Toolbox;DSP System Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_WLAN_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_WLAN_proc.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;4;7;1;2;41;1;27;2;7;3;1;1;1;2
CHECKSUM: 233130FC0A0BF3270BFD330FC25A47B0
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Asynchronous Task Specification;Constant;Data;Data Type Conversion;Decode Status Signals;Digital Clock;Enable;Event driven;MCS;MCS_Out;Manual Switch;Processor Algorithm Periodic;Rate Transition;Read Event;ReadRegisters;Reference;Register Read;Register Write;RxData;RxUDPData;StatusReport;Stream Read;SubSystem;Subsystem;System Outputs;UDP Write;Vector Concatenate;WriteRegisters;data;dataTask;decodedMCS;decoded_MCS;done;frameFormat;frameFormatOut;frameFormat_Out;frame_Format;freqOffset;freq_Offset;headerView;header_View;msg;packetDetected;packet_Detected;psduLen;psdu_Len;signalCRCStatus;signalCRC_Status;signalParityStatus;signalParity_Status;statusUDPReport;valid

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;DigitalClock;EnablePort;Inport;ManualSwitch;Outport;RateTransition;Register Read;Register Write;Stream Read;System Outputs;TriggerPort;UDP Write


MODELNAME: soc_WLAN_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_WLAN_top.slx
BLOCKTYPE_FREQUENCY: 1;1;2;2;14;2;7;1;1;1;2;2
CHECKSUM: 52941FF42F6FC328F35900A1EAED0175
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_WLAN_fpga.slx___Model_Block___soc_WLAN_proc.slx___Model_Block___
ANNOTATION:
 Copyright 2020 The MathWorks, Inc.  WLAN Receiver Using Xilinx RFSoC Device FPGA Memory Processor  Copyright 2023 The MathWorks, Inc. External I/O External I/O

BLOCK:
AXI4-Stream to Software;Data;Delay;Enable;FPGA Algorithm;IO Data Sink;MCS;Processor;Processor-Frame based processing;RF Data Converter;RF Loopback;Reference;Register Write;Rx UDP Write;RxData;Status UDP Write;SubSystem;Task Manager;Terminator;UDP Write;UDP Write ;adc;dac;data;dataReadTaskEvent;decodedMCS;done;frameFormat;frameFormatOut;freqOffset;headerView;packetDetected;pasduLen;signalCRCStatus;signalParityStatus;statusUDPReport

BLOCKTYPE:
AXI4-Stream to Software;Delay;EnablePort;IO Data Sink;Inport;ModelReference;Outport;RF Data Converter;Register Channel;Task Manager;Terminator;UDP Write

PRODUCT:
DSP System Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_dvbs2_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_dvbs2_fpga.slx
CHECKSUM: 7477F695E2A95AF6FC9BCCA3DAAA22FA
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2)  Add Block is used to obtain integer index to Lookup Table  Set this value to zero to disable correction  Let Z be the complex phase estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z))  Wrap on overflow with data type signed and 1 intergral bit will wrap the output to lie in between -1 to 1 Differential Detection Compute Energy peak picker Pilot always true, without pilots not supported Compute Energy Compute Energy  The initial output of these outports are set to 0 as this is an enabled subsystem Hold pilotEnable signal Hold pilotsEnable signal after endOfPLSC Proportional-Plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence Use this port to enable the CCFO for higer carrier offsets  Fixed point precision loss warnings are supressed in Mask Init Callback Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AWGN Generator;Active;Add;AddADn;AddAUp;AddBCtr;AddBDn;AddBUp;Assertion;Bias;Bit Concat;Bit Flipping and Averaging;Bit Shift;Bitwise Operator;Buffer FIFO;Bus Creator;Bus Selector;CFO;CPO;CWswitch;Channel;Coarse Frequency Estimator;Coarse Phase Corrector;Coarse Phase Estimator;Coarse Phase Synchronizer;Code Word LUT 1 to ;Code Word LUT 33 to ;Compare To Constant;Complex Multiplier;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Compute Euclidean Distance;Compute R(m) for 1 to ;Compute R(m) for 13 to ;Compute R(m) for 7 to ;Compute R(m)_;ConcatandExtract;Concatention;Conj;Constant;ConstlOut;Corr Add;Corr Subtract;Correlator;CwEdMetric;DVB-S2 HDL Receiver;DVBS;DVBS2 TxRx;Data Type Conversion;Data Type Duplicate;Data Type Propagation;Delay;Delta;Demux;Digital Automatic Gain Control;Direct Digital Synthesis;Discrete FIR Filter HDL Optimized;Display;Divide by ;Downsample;E;Ed;En;Enable;Error Detector;Euclidean Distance Sum Up;Extract Bits;FEC;FECFrame;FIFO;FIR Decimation HDL Optimized;FIR Interpolator;Fine Frequency Synchronizer;Fine Gain Control;Fine Phase Synchronizer;For Each;For Each Subsystem;Frame Synchronizer;FreqEst;Frequency Error Detector;From;Function Impl;FunctionEvaluation;GTED;Gain;Gardner TED;Gaussian Noise With Given Variance;Get Min Index;Goto;HDL Counter;In;Input Sample Counter;Integer Delay;Integer to Bit Convertor;Integrator Gain;Interpolation Control;Interpolation Filter;K;L and R Algorithm 18 point;LS;LUT;LUT Based Tx;LUTAddr;Logical Operator;Loop Filter;MATLAB Function;ML Decoder;MODCOD;MS;Math Function;Max Peak Searcher;Modified L and R Algorithm;Moving Average;Moving Average ;Moving Sum;Multiport Switch;Mux;NCO;NCO HDL Optimized;No HDL;Out;PL Data Descrambler;PL Data Descrambler and Pilot Valid Indicator;PL Frame Demultiplexer;PL Header Decoder;PL Header Recovery;PL Scramble Sequence Mapper LUT;PL Scrambler Gold Sequence Generator;PLSC Correlator;PLSC Descrambler;PLSC Valid Counter;PLSCCorr;PLSCCorrOut;PLSCDiag;PLSCValid;Peak Search for Fixed Modulation;Phase Error Detector;Pilot Blks Counter;Pilot Valid Indicator;Pilot and Sync Pulse Indicator;PilotIdx Counter;Power Q and Beta Offset Rotation;Prepare Inputs;Prepare Outputs;PrevEst;Product;ProductCtr;ProductDn;ProductUp;RRC Receive Matched Filter;RangeReconstruction;RangeReduction;Rate Handle;Real-Imag to Complex;Reciprocal;Reference;Relational Operator;Repeat;RxDataI_Out;RxData_Out;RxValid_Out;SOF Correlator;SOFCorrDelayed;SOFCorrOut;Shift Arithmetic;Simple Dual Port RAM;SinCos;Sine HDL Optimized;Source Encoding;SqrtEval;SqrtImplementation;State Register;SubSystem;Subsystem;Subtract;Sum;Switch;Symbol Synchronizer;SyncPulse;Synchronizer and PL Header Decoder;TausURNG;TausUniformRandGen;Terminator;Threshold Scaling;ThresholdLimiter;Time Frequency and Coarse Phase Synchronizer;Time and Coarse Frequency Synchronizer;Timing Adjust;To Workspace;Underflow;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Unit Variance Gaussian Noise;Unwrapping algorithm;Upsample;ValueOut;Variance Estimator;Vector Decimation;Vector Interpolation;VisualizeCorrelationSignals;X PN Generator M_n;X PN Generator M_nplus;Y PN Generator M_;a;adc_dac_loopback;avgOut;awgn;b;bits6Out;chCtrlIn;chCtrlOut;complexEst;complexEstimate;constlOut;constl_valid;constlvalid;corr;corrValue;correlationIn;currentEst;dB to Linear Scale Converter;dValid;data;dataIOut;dataI_in;dataIn;dataOut;dataQOut;dataQ_in;decodedFecFrame;decodedModcod;diagBus;din_img;din_real;done;dout;e;empty;enNoise;enable;enb;enbNoise;endOfLUT;endOfPLSC;endOfPLSCIn;endOfPLSc;endOfSOF;endOfSOFIn;err;estOut;estValid;estimate;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;extRst;f;fecFrame;fecframe;finePhaseEn;finefreqEst;forBit;freqEst;full;functionValues;g;g1(16,15);gain;hValid;has Pilots;hasPilots;headerInfo;idxIn;idxOut;indexIndicater;indexIndicator;indexIndicatorIn;indexIndicatorOut;indices;inputCount;interpolant;isdummy;leadingZeroDetector;log;logImplementation;mod;modcod;modcodIdx;modcodidx;modocd;monostable;mu;nFreqEst;ncount;nframesSynced;noiseVar;normCoaFreqEst;normFineFreqEst;normFreqEst;normalizedEst;numSynced;out;outValid;pass;passIn;passOut;peakSearch;pi/2 BPSK Soft Bit Generator;pilotBlkCount;pilotConstel;pilotEnable;pilotIdx;pilotIdxOut;pilotValid;pilotValidIn;pilotValidOut;pilotidx;pop;push;rd;reset;resetFCPO;resetIn;resetOut;rst;rstCCFO;rstFCPO;rstOut;rxData;rxDataOut;rxExtValid_In;rxExtdataI_In;rxExtdataQ_In;rxValid;rxValidOut;rxdataInI;rxdataInQ;rxvalidIn;scaled;searchHold;snrdB;softBit;sqrt(noisePow/2);strobe;success;sum;switch;symbSyncDataOut;symbSyncValidOut;synbSyncDiag;synchronizedData;synchronizedPulse;synchronizedValid;threshold;thresholdExceeded;timing Reference;timing Reference Long;timingOffset;timingOffsetLong;timingOffsetValid;trigger;txData;txDataI_Out;txDataOut;txDataQ_Out;txIData;txLUT;txQData;txValid;txValidOut;txValid_Out;txdataIOut;txdataQOut;txvalid;txvalidOut;u;u0(16,16);u0(48,48);u1(16,16);v;valid;validIn;validOut;valueIn;varOut;vin;vout;wr;x;xMn;xMnp;x_e;x_f;xph;y;yM;y_e;y_f;z;zvalid

BLOCKTYPE:
ArithShift;Assertion;Bias;Bit Concat;Bit Shift;Bitwise Operator;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Complex to Magnitude-Angle;ComplexToRealImag;Constant;Data Type Propagation;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;DownSample;EnablePort;Extract Bits;FIR Decimator;FIR Interpolator;ForEach;From;Gain;Goto;HDL Counter;Inport;Logic;LookupNDDirect;Lookup_n-D;Math;MultiPortSwitch;Mux;NCO;Outport;PN Sequence Generator;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;Simple Dual-port RAM;Sine and Cosine HDL optimized block;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample

BLOCKTYPE_FREQUENCY:
14;4;1;3;22;21;1;1;7;2;109;3;63;41;1;84;30;2232;21;4;2;4;3;27;1;1;14;128;47;55;61;457;111;6;34;31;8;11;5;412;4;102;28;10;8;9;2;2;194;34;29;2;36;32;3

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_dvbs2_hostUDPReceive
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_dvbs2_hostUDPReceive.slx
ANNOTATION: DVB-S2 Receiver Host UDP Receive Model Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;1;9;5;2;1;3;10;1;5;2
CHECKSUM: 239ED4023876471AE2E867DB39DBC0FE
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Bit Slice;Constellation Diagram;Control Scope;DVBS2 Status Report;Data Type Conversion;Display;Enable;Est Frequency Offset;FreqEst;Gain;In;Real-Imag to Complex;Reference;Selector;Status Signals;StatusSignals;SubSystem;UDP Receive Constellation;UDP Receive Status;Visualize Constellation;decodedFECFrame;decodedMODCOD;nframesSynced;statusSignals;varOut

BLOCKTYPE:
Bit Slice;ConstellationDiagram;DataTypeConversion;Display;EnablePort;Gain;Inport;Outport;RealImagToComplex;Selector;UDP Receive


MODELNAME: soc_dvbs2_hwtop
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_dvbs2_hwtop.slx
BLOCKTYPE_FREQUENCY: 2;1;1;9;1;4;1;5;1;2;3;3;1;2;1;1;1
CHECKSUM: 7E85FA4B40FD961E25DB1C6DF05FE381
PRODUCT: Communications Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_dvbs2_fpga.slx___Model_Block___
ANNOTATION:
adc_dac_loopback = 1 RFDC loopback = 0 Internal loopback   DVB-S2 Receiver Hardware Model with RFSoC External I/O FPGA  Copyright 2023 The MathWorks, Inc.

BLOCK:
Bit Slice;CFO;CPO;Constant;Constellation Diagram;Data Type Conversion;Delay;Enable;EsNodB;Estimated Frequency offset;FPGA_Algorithm;False;Gain;Manual Switch;Out;RF Data Converter;RF Loopback;Real-Imag to Complex;Reference;SoC Bus Creator;SoC Bus Selector;SubSystem;Subsystem;Terminator;True;Visualize Constellation;adc;dac;decoded FECFRAME;decoded MODCOD;estVar;fine;input;modcodIdx;number of frames synchronized

BLOCKTYPE:
Bit Slice;Bus Creator;Bus Selector;Constant;ConstellationDiagram;DataTypeConversion;Delay;Display;EnablePort;Gain;Inport;ManualSwitch;ModelReference;Outport;RF Data Converter;RealImagToComplex;Terminator


MODELNAME: soc_dvbs2_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_dvbs2_proc.slx
ANNOTATION: adc_dac_lp = 1 RFDC in loopback =0 TxRx loopback Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;10;5;1;2;1;41;3;37;2;5;7;1;1;1;2
CHECKSUM: 764FD24139C2C044D071BD0753CB5B40
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Asynchronous Task Specification;CFO;CPO;Constant;Data;Data Type Conversion;Decode Status Signals;Digital Clock;Enable;Event driven;FreqEst;Freq_Est;Gain;Manual Switch;Processor Algorithm Periodic;Rate Transition;Read Event;ReadRegisters;Reference;Register Read;Register Write;RxData;RxUDPData;StatusReport;Stream Read;SubSystem;Subsystem;System Outputs;UDP Write;Vector Concatenate;WriteRegisters;adc_dac_lb;adc_dac_loopback;data;dataTask;decodedFecFrame;decodedModcod;decoded_FecFrame;decoded_Modcod;decoded_varOut;done;enbNoise;enb_Noise;endNoise;fineFreqEst;insertCFO;insertCPO;insert_CFO;insert_CPO;modcodIdx;modcod_Idx;modcodidx;msg;nFramesSynced;nFrames_Synced;resetFCPO;reset_FCPO;snr_dB;snrdB;statusUDPReport;valid;varOut;var_Out

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;DigitalClock;EnablePort;Gain;Inport;ManualSwitch;Outport;RateTransition;Register Read;Register Write;Stream Read;System Outputs;TriggerPort;UDP Write


MODELNAME: soc_dvbs2_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_dvbs2_top.slx
BLOCKTYPE_FREQUENCY: 1;1;2;2;12;2;11;1;1;1;2;2
CHECKSUM: 4DAB61476CA8938C56F3B11D99479320
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_dvbs2_fpga.slx___Model_Block___soc_dvbs2_proc.slx___Model_Block___
ANNOTATION:
 Copyright 2023 The MathWorks, Inc. FPGA External I/O  DVB-S2 Receive Using Xilinx RFSoC Device Device  Copyright 2022 The MathWorks, Inc. Memory Processor External I/O Copyright 2022 The MathWorks, Inc.

BLOCK:
AXI4-Stream to Software;Delay;Enable;FPGA_Algorithm;FreqEst;IO Data Sink;Processor;Processor - Frame based processing;RF Data Converter;RF Loopback;Reference;Register Channel;Rx UDP Write;RxData;Status UDP Write;SubSystem;Task Manager;Terminator;UDP Write;UDP Write ;adc;adc_dac_loopback;dac;data;dataReadTaskEvent;decodedFecFrame;decodedModcod;done;enbNoise;insertCFO;insertCPO;modcodIdx;nFramesSynced;resetFCPO;snrdB;statusUDPReport;varOut

BLOCKTYPE:
AXI4-Stream to Software;Delay;EnablePort;IO Data Sink;Inport;ModelReference;Outport;RF Data Converter;Register Channel;Task Manager;Terminator;UDP Write


MODELNAME: visionzynq_target_capture
BLOCKTYPE_FREQUENCY: 1;2;2;2;2;2;2;2;2;1;1
CHECKSUM: D9BA3652B25C99CF25A2A3CCCE07AC48
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/target/esw/src/visionzynq-target-capture/mdl/visionzynq_target_capture.slx

BLOCK:
AXI4-Interface Read;Data Type Conversion;Enable;For Iterator;For Iterator Subsystem;Gain;In;Logical Operator;Out;Recv Enable cmd;Reference;Selector;Send Frame;SubSystem;UDP Receive;UDP Send;Vision Zynq Target Capture Server

BLOCKTYPE:
AXI4-Interface Read;DataTypeConversion;EnablePort;ForIterator;Gain;Inport;Logic;Outport;Selector;UDP Receive;UDP Send


MODELNAME: dummy_master
PATH: toolbox/soc/supportpackages/zynq_vision/target/hw/src/dummy_master/dummy_master.slx
BLOCKTYPE: BusCreator;BusSelector;Constant;DataTypeConversion;Inport;Outport;Terminator
BLOCKTYPE_FREQUENCY: 5;3;14;5;7;7;9
CHECKSUM: F75DDC9CC920AE3B15195ACA03B76022
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices
BLOCK:
AXIReadCtrlIn;AXIReadCtrlOut;AXIReadData;AXIWriteCtrlIn;AXIWriteCtrlOut;AXIWriteData;AXIWritedata;Bus Creator;Bus Selector;BusCreator;Constant;Data Type Conversion;FromMemory;SubSystem;Terminator;ToMemory;dummyMaster


MODELNAME: dut_bypass
PATH: toolbox/soc/supportpackages/zynq_vision/target/hw/src/dut_bypass/dut_bypass.slx
BLOCKTYPE: BusSelector;Constant;Frame To Pixels;Terminator
BLOCKTYPE_FREQUENCY: 2;3;1;10
CHECKSUM: 1511EEDE7B710ACF5A07F41DF82A7163
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox
BLOCK:
Bus Selector;Constant;Frame To Pixels;Reference;SubSystem;bypassOut;dutBypass;hEndOut;hStartOut;pixelOut;vEndOut;vStartOut;validOut


MODELNAME: frame_capture
PATH: toolbox/soc/supportpackages/zynq_vision/target/hw/src/frame_capture/frame_capture.slx
BLOCKTYPE_FREQUENCY: 8;4;4;4;2;2;7;15;1;2;54;4;29;3;14;1
CHECKSUM: FAD7E15309B1F9F008D4138913624E42
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox
BLOCK:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;Channel ;Compare To Constant;Constant;DUTIn;DUTIn_ctrl;DUTIn_hEnd;DUTIn_hStart;DUTIn_vEnd;DUTIn_vStart;DUTIn_valid;DUTOut;DUTOut_ctrl;DUTOut_hEnd;DUTOut_hStart;DUTOut_vEnd;DUTOut_vStart;DUTOut_valid;DataIn;Delay;Frame To Pixels;Multiport Switch;Packer16to;Packer8to;PackerPass;Pixel Control Bus Creator;Pixel Control Bus Selector;ROI Selector;Reference;SubSystem;TPG;TPG_ctrl;TPG_hEnd;TPG_hStart;TPG_vEnd;TPG_vStart;TPG_valid;Terminator;Vector Concatenate;ctrlIn;ctrlOut;dataPacker;frameCaptureBlock;hSize;hSizeOut;out Counter;packingMode;packingModeOut;pixelIn;pixelOut;sourceSelect;srcSel;srcSelOut;vEnd;vEndIn;vEndOut;vSize;vSizeOut;vStart;vStartIn;vStartOut;valid;validIn;validOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Delay;Frame To Pixels;HDL Counter;Inport;MultiPortSwitch;Outport;Pixel Control Bus Creator;Terminator;visionhdl.ROISelector


MODELNAME: hdmi_passthrough24bit
BLOCKTYPE: Constant;Delay;Inport;Outport;Pixel Control Bus Creator;Terminator
BLOCKTYPE_FREQUENCY: 6;2;2;2;1;2
CHECKSUM: B5AF1ABC32AB510D223B4A6E62366D7B
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox
PATH:
toolbox/soc/supportpackages/zynq_vision/target/hw/src/hdmi_passthrough24bit/hdmi_passthrough24bit.slx

BLOCK:
Constant;Delay;Pixel Control Bus Creator;Reference;SubSystem;Terminator;passthrough24bit;pixelControlBusIn;pixelControlBusOut;pixelIn;pixelOut


MODELNAME: tpg
PATH: toolbox/soc/supportpackages/zynq_vision/target/hw/src/tpg/tpg.slx
BLOCKTYPE: BusSelector;Constant;Frame To Pixels;Terminator
BLOCKTYPE_FREQUENCY: 2;5;1;13
CHECKSUM: 0B03C0440E671838BDB8B3012DFB9A7E
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox
BLOCK:
Frame To Pixels;Pixel Control Bus Selector;Reference;SubSystem;Terminator;To Increment;To Level;To Mode;testPatternGeneration


MODELNAME: vht2axivs
PATH: toolbox/soc/supportpackages/zynq_vision/target/hw/src/vht2axivs/vht2axivs.slx
BLOCKTYPE_FREQUENCY: 1;2;4;3;2;1;10;2;4;1;2;4
CHECKSUM: 12713CE135FD5E20D415ED3DC98FA7B0
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox
BLOCK:
 Demux ; SFunction ; Terminator ;Bit Concat;Bus Selector;Constant;Delay;Frame To Pixels;Logical Operator;MATLAB Function;Pixel Control Bus Creator;Reference;SubSystem;Terminator;TriggerStart;ctrlOut;hEndIn;hStartIn;pixelIn;pixelOut;start;vEndIn;vStart;vStartIn;validIn;vht2axivs;writeTrigger

BLOCKTYPE:
Bit Concat;BusSelector;Constant;Delay;Demux;Frame To Pixels;Inport;Logic;Outport;Pixel Control Bus Creator;S-Function;Terminator


MODELNAME: visionzynqHWSWTemplate
PATH: toolbox/soc/supportpackages/zynq_vision/visionzynq/visionzynqHWSWTemplate.slx
BLOCK: Capture Block;Ground;HW User Logic Interface Block;Image;SubSystem;ULInterfaceIn;ULInterfaceOut
BLOCKTYPE: Ground;Inport;Outport
BLOCKTYPE_FREQUENCY: 1;1;2
CHECKSUM: EA4CC0713F90EEDB17946D76D0AC6FB3
PRODUCT: Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
ARM Interface to Vision Zynq Device ARM Interface to HW User Logic  Write to HW user logic here  Read from HW user logic here  Add video processing algorithm here


MODELNAME: visionzynqTgtHWTemplate
PATH: toolbox/soc/supportpackages/zynq_vision/visionzynq/visionzynqTgtHWTemplate.slx
BLOCK: Capture Block;Ground;HW User Logic Interface Block;Image;SubSystem;ULInterfaceIn;ULInterfaceOut
BLOCKTYPE: Ground;Inport;Outport
BLOCKTYPE_FREQUENCY: 1;1;2
CHECKSUM: 2B7FEE8D96D728390D6BDF1D4B3C54A0
PRODUCT: Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Simulink Interface to HW User Logic  Write to HW user logic here Vision Zynq Device to Simulink Algorithm  Add video processing algorithm here  Read from HW user logic here


MODELNAME: vzBilateral_PixelStream
BLOCKTYPE_FREQUENCY: 1;2;2;3;6;1;14;1;1;1;2;1;1;1;1;26;1;20;3;6;3;1;1;1;1;1;1
CHECKSUM: D751FA30B88865859A132737AB6A2971
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzBilateral_PixelStream.slx

ANNOTATION:
Conversion Copyright 2017-2023 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Bilateral Filter Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
?;Align;B;BIn;BOut;Bilateral Filter;Bilateral Filter Algorithm;BinaryIn;BinaryOut;BinaryToRGB;Bit Slice;Color Space Converter;Constant;CtrlIn;CtrlOut;Delay;Display;Edge Detector;Edges;FrameBoundary;From Multimedia File;G;GIn;GOut;Gain;HDL Counter;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;LED;Logical Operator;Matrix Concatenate;Overlay;OverlayColor;PB0 Show Edge Only;Pixel Control Bus Selector;Pixel-Stream Output;PushButton;Quantize;R;RGB Concatenate;RGB Select;RGBIn;RGBOut;RIn;ROut;Rate Transition;Reference;SW Cfg Gradient Threshold;SW Cfg Overlay Color ;Select B;Select G;Select R;Selection Subsystem;Selector;SubSystem;Switch;Terminator;ThreshIn;ThreshOut;Vector Concatenate;Video Capture HDMI;cGradientThresh;cOverlayColor;ctrl;ctrlIn;ctrlOut;pbEdgeOnly;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Slice;BusSelector;Color Space Converter;Concatenate;Constant;CustomCallbackButton;Delay;Display;Edge Detector;From Multimedia File;Gain;HDL Counter;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Logic;Outport;RateTransition;Selector;Switch;Terminator;To Video Display;VariantSource;visionhdl.BilateralFilter;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzCarCounting
BLOCK: ?;SubSystem;Subsystem
BLOCKTYPE: CustomCallbackButton
BLOCKTYPE_FREQUENCY: 1
CHECKSUM: FD3AA2BE758E38AC7B234BE0A189DB3D
PRODUCT: Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzCarCounting.slx

ANNOTATION:
 This example shows how to use the Xilinx Zynq-Based Vision Support Package with Simulink to target a Car Tracking algorithm to the ARM on the Zynq(R) hardware. It uses two models: one for simulation with the attached hardware and one for targeting the ARM on the Zynq Open the full write-up by double clicking the Info block. Open individual models by clicking the appropriate blocks below.  Tracking Cars Using Foreground Detection Algorithm with Zynq-Based Hardware Copyright 2017 The MathWorks, Inc.


MODELNAME: vzCarCounting_01_FrameBased
BLOCKTYPE_FREQUENCY: 1;3;1;2;1;4;1;1;1;2;1;1;1;1
CHECKSUM: CBB882FA32D86E2F6549F352E28518A5
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzCarCounting_01_FrameBased.slx

ANNOTATION:
Copyright 2017 -2023 The MathWorks Inc. Algorithm Display  Tracking Cars Using Foreground Detection Algorithm with Zynq-Based Hardware Source

BLOCK:
?;BBox;Blob Analysis;Car Tracking Algorithm;Constant;Count;Draw Shapes;From Multimedia File;Image Source;In;Insert Text;Median Filter;Out;Overlay Results;ROI;Reference;Results;SubSystem;Text Background;Video Capture HDMI;Video In;Video Out;vision.ForegroundDetector;x position;y position

BLOCKTYPE:
Blob Analysis;Constant;CustomCallbackButton;Draw Shapes;From Multimedia File;Inport;Insert Text;MATLABSystem;Median Filter;Outport;Selector;VariantSource;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzCarCounting_02_SwTargeting
BLOCKTYPE_FREQUENCY: 1;3;1;2;4;1;1;1;2;1;1;1
CHECKSUM: 724A8825B764B51748FEC1E9B0AFFC19
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzCarCounting_02_SwTargeting.slx

ANNOTATION:
Copyright 2017-2023 The MathWorks Inc.  Tracking Cars Using Foreground Detection Algorithm with Zynq-Based Hardware (Software Targeting Model) Algorithm Display Source

BLOCK:
?;BBox;Blob Analysis;Car Tracking Algorithm;Constant;Count;Draw Shapes;In;Insert Text;Median Filter;Out;Overlay Results;ROI;Reference;Results;SubSystem;Text Background;Video Capture HDMI;Video In;Video Out;vision.ForegroundDetector;x position;y position

BLOCKTYPE:
Blob Analysis;Constant;CustomCallbackButton;Draw Shapes;Inport;Insert Text;MATLABSystem;Median Filter;Outport;Selector;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzCorner_PixelStream
BLOCKTYPE_FREQUENCY: 1;1;2;1;3;9;1;5;106;1;1;2;1;5;1;1;1;37;29;8;4;1;6;5;3;4;1;1;1;1
CHECKSUM: 245C88B444381D7F4053390B5EB468EA
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzCorner_PixelStream.slx

ANNOTATION:
Conversion Copyright 2016 -2023 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Corner Detection and Image Overlay Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
?;Add;B;BIn;BOut;BinaryIn;BinaryOut;BinaryToRGB;Bit Slice;Color Space Converter;Compare To Constant;Constant;Convert Levels;Corner Overlay Algorithm;CtrlIn;CtrlOut;CtrlOut ;Data Type Conversion;Delay;Display;Edges;From Multimedia File;G;GIn;GOut;Gain;GaussianGx;GaussianGy;GaussianGyGx;GradX;GradY;Gradients;Gradx;Grady;Gx;GxSquared;Gy;GyGx;GySquared;HDL Counter;HarrisIn;HarrisOut;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;LED;Matrix Concatenate;Overlay;OverlayColor;OverlayTransp;PB0 Show Corner Only;Pixel Control Bus Selector;Pixel Stream Aligner;Pixel-Stream Output;PixelOut;Product;PushButton;R;RGB Concatenate;RGB Select;RGB2Bin;RGBIn;RGBOut;RGBout;RIn;ROut;Rate Transition;Reference;Relational Operator;SW Cfg Overlay Color ;SW Cfg Overlay Transparency;SW Cfg Slice Level;Select B;Select G;Select R;Selection Subsystem;Selector;SliceLevel;SquareComp;SubSystem;Sum;Switch;Terminator;Vector Concatenate;Video Capture HDMI;cOverlayColor;cOverlayTransp;cSliceLevel;ctrl;ctrlIn;ctrlOut;det_trace;pbCornerOnly;pixel;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Slice;BusSelector;Color Space Converter;Compare To Constant;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;Display;From Multimedia File;Gain;HDL Counter;Image Filter;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Outport;Product;RateTransition;RelationalOperator;Selector;Sum;Switch;Terminator;To Video Display;VariantSource;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzEdge_01_FrameBased
BLOCKTYPE_FREQUENCY: 2;1;6;1;1;1;1;1;13;6;2;4;2;5;3;1;1;1
CHECKSUM: 0496F901774A7B1D95CC32B6C2CFDC8F
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzEdge_01_FrameBased.slx

ANNOTATION:
Display Algorithm Source  Edge Detection and Image Overlay Frame-Based Algorithm with Zynq-Based Hardware  Copyright 2016-2023 The MathWorks, Inc.

BLOCK:
?;Add;Bus Creator;Bus Selector;CbIn;CbOut;Constant;CrIn;CrOut;DIPSwitch;DS0 Grayscale;Edge Detection;Edges;Frame Rate;Frame-Based Edge Overlay Algorithm;From Multimedia File;Gain;Image Source ;Original Image;Output Image;Overlay;PB0 Show Edge Only;Product;PushButton;Rate Transition;Reference;SW Cfg Alpha;SW Cfg Threshold;Selection Subsystem;SubSystem;Switch;Video Capture HDMI;YIn;YOut;cAlpha;cThreshold;dsGrayscale;pbEdgeOnly

BLOCKTYPE:
BusCreator;BusSelector;Constant;CustomCallbackButton;Edge Detection;Frame Rate Display;From Multimedia File;Gain;Inport;Outport;Product;RateTransition;Sum;Switch;To Video Display;VariantSource;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzEdge_02_PixelStream
BLOCKTYPE_FREQUENCY: 1;3;2;2;1;10;1;24;4;1;1;1;1;1;44;26;3;4;8;2;4;9;1;2;1;1;1;1;1;1
CHECKSUM: CEEF022826C43FCB4C843988CAD20DA4
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzEdge_02_PixelStream.slx

ANNOTATION:
1 Conversion Copyright 2016 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Edge Detection and Image Overlay HDL Pixel-Streaming Algorithm with Zynq-Based Hardware  Frame-Based Algorithm

BLOCK:
 ;?;Add;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CbCr;CbCrIn;CbCrOut;CbIn;CbOut;Compare HDL User Logic with Behavioral;Constant;CrIn;CrOut;CtrlIn;CtrlOut;DIPSwitch;DS0 Grayscale;Delay;Display;Edge Detection;Edge Detector;Edge Overlay Algorithm;EdgeIn;EdgeOut;Edges;Frame-Based Output;From Multimedia File;Full-Frame Behavioral Algorithm;Gain;HDL Counter;Image Overlay;Image Source;LED;Overlay;OverlayOut;PB0 Show Edge Only;PSNR;PSNR for Cb;PSNR for Cr;PSNR for Y;Pixel Control Bus Selector;Pixel Stream Aligner;Pixel-Stream Output;Product;PushButton;Rate Transition;Reference;SW Cfg Alpha;SW Cfg Threshold;Select Interleaved CbCr;Select Y;Selection Subsystem;SubSystem;Switch;Terminator;Threshold;Vector Concatenate;Video Capture HDMI;Y;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr 4:2:2 Resize;YCbCr From Scalar;YCbCr To Scalar;YIn;YOut;alpha;behCb;behCr;behY;cAlpha;cThreshold;ctrlIn;ctrlOut;dsGrayscale;hdlCb;hdlCr;hdlY;pbEdgeOnly;pixelCtrl;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Concatenate;Constant;CustomCallbackButton;Delay;Display;Edge Detection;Edge Detector;From Multimedia File;Gain;HDL Counter;Inport;Outport;PSNR;Product;RateTransition;Selector;Sum;Switch;Terminator;To Video Display;VariantSource;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr Resize;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzEdge_03_TargetSource
BLOCKTYPE_FREQUENCY: 1;3;2;2;1;8;1;21;1;1;1;1;1;25;17;2;4;2;2;4;1;1;1;1;1;1;1;1
CHECKSUM: 3E12698469BEDF4FAEFA19BF40541456
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzEdge_03_TargetSource.slx

ANNOTATION:
1 Copyright 2016-2023 The MathWorks, Inc. Source Display  Edge Detection and Image Overlay Pixel-Stream Algorithm with Zynq-Based Hardware (Hardware Targeting Model) Conversion Pixel-Stream Algorithm Conversion

BLOCK:
?;Add;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CbCr;CbCrIn;CbCrOut;Constant;CtrlIn;CtrlOut;DIPSwitch;DS0 Grayscale;Delay;Display;Edge Detection;Edge Detector;Edge Overlay Algorithm;EdgeIn;EdgeOut;Edges;Frame Rate;From Multimedia File;HDL Counter;Image Overlay;Image Source;LED;Output Image;Overlay;OverlayOut;PB0 Show Edge Only;Pixel Control Bus Selector;Pixel Stream Aligner;Product;PushButton;Rate Transition;Reference;SW Cfg Alpha;SW Cfg Threshold;Select Interleaved CbCr;Select Y;Selection Subsystem;SubSystem;Switch;Terminator;Threshold;Vector Concatenate;Video Capture HDMI;Y;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr 4:2:2 Resize;YCbCr From Scalar;YCbCr To Scalar;YIn;YOut;alpha;cAlpha;cThreshold;ctrlIn;ctrlOut;dsGrayscale;pbEdgeOnly;pixelCtrl;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Concatenate;Constant;CustomCallbackButton;Delay;Display;Edge Detector;Frame Rate Display;From Multimedia File;HDL Counter;Inport;Outport;Product;RateTransition;Selector;Sum;Switch;Terminator;To Video Display;VariantSource;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr Resize;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzEdge_03_TargetSource_interface_saved
BLOCKTYPE_FREQUENCY: 1;2;1;1;2;1;1
CHECKSUM: 644BEDB436A3A8A6150CEFB022DC8240
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzEdge_03_TargetSource_interface_saved.slx

ANNOTATION:
Vision Zynq Software Interface Model: vzEdge_03_TargetSource This model contains blocks that can be used for software generation. Generated by HDL Workflow Advisor on 20-Jan-2017 12:32:04 ARM Interface to Vision Zynq Device ARM Interface to HW User Logic

BLOCK:
?;Edge Overlay Algorithm;Frame Rate Display;Reference;SW Cfg Alpha;SW Cfg Threshold;Terminator;Video Capture HDMI;Video Viewer

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;Constant;CustomCallbackButton;Frame Rate Display;Terminator;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzEdge_03_TargetSource_tgthw_interface_saved
BLOCKTYPE_FREQUENCY: 2;1;1;1;1;1
CHECKSUM: E8328958F7D0E4E8169C60648DCB71B6
PRODUCT: Computer Vision Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzEdge_03_TargetSource_tgthw_interface_saved.slx

ANNOTATION:
Vision Zynq Targeted Hardware Interface Model: vzEdge_03_TargetSource This model contains blocks that can be used for simulation with targeted hw user logic. Generated by HDL Workflow Advisor on 20-Jan-2017 12:31:50 Simulink Interface to HW User Logic Vision Zynq Device to Simulink Algorithm

BLOCK:
?;Behavioral Algorithm Output Display;Edge Overlay Algorithm;Frame Rate Display;Reference;SW Cfg Alpha;SW Cfg Threshold;Video Capture HDMI

BLOCKTYPE:
Constant;CustomCallbackButton;EdgeOverl_ip VisionZynq Target Cosimulation;Frame Rate Display;To Video Display;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzFogRectification_PixelStream
BLOCKTYPE_FREQUENCY: 2;1;36;4;33;1;8;148;1;1;12;1;2;12;21;1;1;1;1;1;61;22;4;54;15;6;9;2;14;18;2;2;1;3;1;1;1
CHECKSUM: E3CC13EDE9E8BBA8229DE5EBD7DFD82A
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzFogRectification_PixelStream.slx

ANNOTATION:
logic to find porch+number of columns (o1/i1)*(0:I1) CALCULATION o1/i1 CALCULATION CONVERSION TO UPCOUNTER (0 TO i1) DESIGN OF DOWNCOUNTER FROM i1 TO 0 CIRCUIT FOR POPPING t1 WHEN i2 CALCULATION IS DONE ((o2-o1) / (i2 - i1)) * i1 UPCOUNTER FROM i1+1 TO i2 DOWN COUNTER FROM i2 TO 0 ((o2-o1 / (i2 - i1)) * (i1+1:i2) t2 = ( (((o2-o1) / (i2 - i1)) * (i1+1:i2)) - (((o2-o1) / (i2 - i1)) * i1) ) + o1 COUNTER DESIGN FROM i2 to 255 (255-o2) / (255 - i2) * i2 ( ((255-o2) / (255 - i2) * (i2+1 :255)) - ((255 -o2) / (255 - i2))*i2 ) t3 = ( ((255-o2) / (255 - i2) * (i2+1 :255)) - ((255 - o2) / (255 - i2))*i2 ) + o2 Histogram Calculation and Normalization Contrast Stretching - LUT Contrast Stretching - T calculation Source Conversion Pixel-Stream Algorithm Conversion Compare and Display Frame Buffer Model  Fog Rectification Pixel-Stream Algorithm with Zynq-Based Hardware Copyright 2020-2021 The MathWorks, Inc.

BLOCK:
 Delay;?;AND;Add;B;BIn;BOut;Bilateral Filter;BtoFramebuffer;Compare To Constant;Constant;ContrastEnhancement;CounterForWriteAddress;CtrlIn;CtrlOut;DarkChannel;Data Type Conversion;Delay;DiffOfInputAndDiffim;Enable;Enabled Subsystem;FactorCalculation;Fog Rectification Algorithm;FogOutputView;FogRemoval;From;From Multimedia File;G;GIn;GOut;Gain;GeneratePopForImageBuffer;Goto;GtoFramebuffer;HDL Counter;HDL FIFO;HistNormAndCDFCalculation;Histogram;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;In;InputBuffer;LUT;Matrix Concatenate;Max;NOT;OR;Out;Pixel Control Bus Selector;Pixel Stream Aligner;Pixel-Stream Output;Pixel-Stream input;Product;R;RGB Concatenate;RGB Select;RGBtoGray;RIn;ROut;Reciprocal;Reference;Relational Operator;Restoration;RtoFramebuffer;ScaledInput;Select B;Select G;Select R;Selector;Simple Dual Port RAM;SubSystem;Subtract;Switch;T;TCalculation;Terminator;TgenEnb;Vector Concatenate;Video Capture HDMI;Video Frame Buffer;bufferB;bufferG;bufferR;busOutAfterConv;cdf;ctrlBus;ctrlBusIn;ctrlBusOut;ctrlIn;ctrlOut;darkCh;dataIn;defogCtrlOut;defogPixOut;diffOfIpAnddiffim;diffimAfterConv;diffimAfterReduction;diffimForRestoration;diffimForRst;enablei;factor;hdlOutput;histVal;i;i1Andi2Calculation;i1Calculation ;i1Val;i2Calculation;i2HighEnable;i2Val;min;outB;outG;outR;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut;pop;popVB;rdValid;scaledPixelIn;t;t1Calculation;t1Enable;t2Calculation;t2Enable;t2Rst;t3Calculation;t3Enable;validFromHist;validHist;writeAddress;writeEnable

BLOCKTYPE:
BusSelector;Color Space Converter;Compare To Constant;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;EnablePort;Frame Buffer Simulation;From;From Multimedia File;Gain;Goto;HDL Counter;HDL_FIFO;Histogram;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Logic;MinMax;Outport;Product;RelationalOperator;Selector;Simple Dual-port RAM;Sum;Switch;Terminator;To Video Display;VariantSource;hdl.RAM;visionhdl.BilateralFilter;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzGamma_PixelStream
BLOCKTYPE_FREQUENCY: 2;4;1;1;1;1;2;1;1;6;1;1;1;1;17;16;1;3;2;3;1;1;1
CHECKSUM: 5BCC2736BB8B18C994F8EB496A9B27ED
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzGamma_PixelStream.slx

ANNOTATION:
Conversion Copyright 2016 -2023 The MathWorks Inc. Pixel-Stream Algorithm Compare and Display Conversion  Gamma Correction Pixel-Streaming Algorithmwith Zynq-Based Hardware Source

BLOCK:
?;B;BIn;BOut;Bit Concat;Bit Slice;CtrlIn;CtrlOut;DIPSwitch;DS0 Correct;Delay;Display;From Multimedia File;G;GIn;GOut;Gamma Correction Algorithm;Gamma Corrector;Gamma Corrupt;HDL Counter;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;LED;Pixel Control Bus Selector;Pixel-Stream Output;R;RGB Concatenate;RGB Pixel Splice;RGB Select;RGBIn;RIn;ROut;Rate Transition;Reference;Select B;Select G;Select R;SubSystem;Switch;Terminator;Vector Concatenate;Video Capture HDMI;correctedCtrl;correctedPixel;corruptCtrl;corruptPixel;ctrl;dsCorrect;pixel;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;switch

BLOCKTYPE:
Bit Concat;Bit Slice;BusSelector;Concatenate;Constant;CustomCallbackButton;Delay;Display;From Multimedia File;Gamma Corrector;HDL Counter;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Outport;RateTransition;Selector;Switch;Terminator;To Video Display;VariantSource;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzGettingStarted
ANNOTATION: Getting Started with Vision Zynq Hardware Copyright 2016-2023 The MathWorks, Inc.
BLOCK: ?;Frame Rate Display;Reference;To Video Display;Video Capture HDMI
BLOCKTYPE: CustomCallbackButton;Frame Rate Display;To Video Display;visionzynq.internal.VideoCaptureHDMI
BLOCKTYPE_FREQUENCY: 1;1;1;1
CHECKSUM: B74E1FEDC1BC485C16C224C2B62D0020
PRODUCT: Computer Vision Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzGettingStarted.slx


MODELNAME: vzGettingStartedMIPI
ANNOTATION: Getting Started with MIPI Sensor Copyright 2022 The MathWorks, Inc.
BLOCK: ?;Reference;To Video Display;Video Capture MIPI
BLOCKTYPE: CustomCallbackButton;To Video Display;visionzynq.internal.VideoCaptureMIPI
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: F531975B0710D9B71DECB3E25C663E36
PRODUCT: Computer Vision Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzGettingStartedMIPI.slx


MODELNAME: vzHistogramEqualization_PixelStream
BLOCKTYPE_FREQUENCY: 3;8;2;3;1;2;2;1;1;43;2;2;1;1;4;1;39;1;35;1;1;2;4;1;1;1;3;3;1;1;1;1;1;1
CHECKSUM: F7B5490A98932C04C048FF23B1A83A9B
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzHistogramEqualization_PixelStream.slx

ANNOTATION:
internally pipelined with 1 register before multiplier and 1 register after multiplier. ~ Delay = 2  Frame Buffer Model Conversion Display Conversion Source  Histogram Equalization Algorithm with Zynq-Based Hardware and External Memory Frame Buffer Pixel-Stream Algorithm Copyright 2018 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;?;Apply Equalization;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CDFOut;CbCr;CbCrFromFrameBuf;CbCrIn;CbCrOut;CbCrToFrameBuf;Compare To Constant;Constant;Contrast Adjustment;CtrlIn;CtrlOut;Delay;Display;FrameSize;From Multimedia File;HDL Counter;HGComputationRdy;HGEqualization;HSize;Histogram;Histogram Computation;Histogram Equalization Algorithm;HistogramDone;Image Source;Index Vector;LED;Matrix Concatenate;PB0 Bypass Algorithm;Pixel Control Bus Selector;Pixel-Stream Output;PixelIn;Product;Rate Transition;Reference;Select Interleaved CbCr;Select Y;Selector;Signal Specification;State Control;SubSystem;Sum;Switch;Terminator;VSize;Vector Concatenate;Video Capture;Video Frame Buffer;Y;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr 4:2:2 Resize;YCbCr From Scalar;YCbCr To Scalar;YFromFrameBuf;YIn;YOut;YToFrameBuf;accmHist;accm_hist;applyEq;binReset;bypass;cdf;cdfVectorGen;cdf_vector;ctrl;ctrlBusIn;ctrlFromFrameBuf;ctrlIn;ctrlOut;ctrlToFrameBuf;detectFrameSize;done;err;errorLED;f;frameSize;histComp;histEqData;hist_accum;hist_data;im;pbBypass;pctrlOut;pdataOut;pfifoCtrlIn;pfifoDataIn;pixel;pixelCtrl;pixelData;pixelFromFrameBuf;pixelIn;pixelOut;popFrame;readDone;valid;validOut;y;ycdf

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Contrast Adjustment;CustomCallbackButton;Delay;Demux;Display;Frame Buffer Simulation;From Multimedia File;HDL Counter;Histogram;Inport;MultiPortSwitch;Outport;Product;RateTransition;S-Function;Selector;SignalSpecification;StateControl;Sum;Switch;Terminator;To Video Display;VariantSource;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr Resize;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzImageRotation_PixelStream
BLOCKTYPE_FREQUENCY: 1;1;6;4;8;6;3;18;2;1;4;9;3;1;14;1;4;6;2;1;1;1;83;73;1;68;2;1;3;3;9;3;4;7;11;1;4;12;1;3;1
CHECKSUM: 1EE2E891C670B0FBC0F6F6642C1A16BA
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzImageRotation_PixelStream.slx

ANNOTATION:
Conversion Copyright 2018 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Image Rotation Algorithm with Zynq-Based Hardware and AXI Master External Memory Access External Memory with AXI Interface

BLOCK:
 Demux ; SFunction ; Terminator ; ackIn==;?;AXIReadCtrlIn;AXIReadCtrlOut;AXIReadData;AXIWriteCtrlIn;AXIWriteCtrlOut;AXIWriteData;AXIWritedata;AckGen;Add;B;BIn;BOut;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;BusCreator;Column_Counter;Compare To Constant;Constant;CtrlIn;CtrlOut;Data Type Conversion;Delay;Display;External Memory;From;From Multimedia File;FromMemory;G;GIn;GOut;Goto;HDL Counter;HDL FIFO;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Rotation Algorithm;Image Source;In;LED;Line_Counter;Logical Operator;MATLAB Function;MATLAB System;Out;PB0 Show ROI Only;Pixel Control Bus Selector;Pixel-Stream Output;Product;PushButton;Q;R;RGB Concatenate;RGB Select;RGBOut;RIn;ROI;ROI Selector;ROut;Rate Transition;ReadCtrl;ReadTrigger;ReadTriggered;Reference;Relational Operator;Rotated;S;Select B;Select G;Select R;Selector;Signal Specification;Start;SubSystem;Switch;Terminator;ToMemory;Unit Delay;ValAddEnb;ValwrLenCnt;Vector Concatenate;Video Capture HDMI;Wr_control;WriteCtrl;ack;ackIn;ackIn Posedge Detect;ackIn_d;ackIn_d1==;ackOut;afull;axiWrLen;axiWrLen!=;axiWrLen-1==cnt & axiWrLen!=0 ;axiWrLen==cnt+;axi_rd_add;axi_rd_len;axi_rd_ready;axi_rd_val;axi_wr_en;axi_wr_length;axim_ack;axim_rd_addr;axim_rd_aready;axim_rd_avalid;axim_rd_dready;axim_rd_dvalid;axim_rd_len;axim_wr_ack;axim_wr_addr;axim_wr_enb;axim_wr_len;axim_wr_ready;cache_reg;ctrl;data_fwft_fifo;data_in;data_out;ddr_ack_d;dtci;edgeDet;empty_i;empty_o;full;fwft_logic;if cnt < axiWrLen;out_reg;pbROIOnly;ping_pong;pixel;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pop_o;push;ram_addr;ram_rd_addr;ram_rd_val;ram_wr_addr;ram_wr_enb;ram_wr_enb cond;rd_ack;rd_control;readTrigger;sr_latch;start;triggerMemory;vEnd;vStart;valAddEnb;valid;wrEnb;wr_ack;wr_addr-;wr_enb;wr_len;wr_leng;writeTrigger

BLOCKTYPE:
Bit Concat;Bit Shift;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Conversion Inherited;CustomCallbackButton;DataTypeConversion;Delay;Demux;Display;From;From Multimedia File;Goto;HDL Counter;HDL_FIFO;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Logic;MATLABSystem;Outport;Product;RateTransition;RelationalOperator;S-Function;Selector;SignalSpecification;Sum;Switch;Terminator;To Video Display;Unit Delay Enabled;UnitDelay;VariantSource;visionhdl.ROISelector;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzLaneDetection
BLOCK: ?;SubSystem;Subsystem
BLOCKTYPE: CustomCallbackButton
BLOCKTYPE_FREQUENCY: 1
CHECKSUM: 9B07450848B43D5880F7D6CE7FC5A560
PRODUCT: Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzLaneDetection.slx

ANNOTATION:
 This example shows how to use the Xilinx Zynq-Based Vision Support Package with Simulink to target a Lane Detection algorithm to the ARM on the Zynq(R) hardware. It uses three models: one for targeting the FPGA on the Zynq, one for simulation with the attached hardware after targeting the FPGA and one for targeting the ARM on the Zynq. Open the full write-up by double clicking the Info block. Open individual models by clicking the appropriate blocks below.  Lane Detection Algorithm with Zynq-Based Hardware Copyright 2017 The MathWorks, Inc.


MODELNAME: vzLaneDetection_01_PixelStream
CHECKSUM: A948CF6EE2C614477F984ACD7E093AA5
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzLaneDetection_01_PixelStream.slx

ANNOTATION:
offset columns pipelining wait 3 full frames before triggering output at input frame rate Frame Buffer Model Conversion Compare and Display Algorithm Copyright 2017-2018 The MathWorks, Inc. Pixel-Stream Algorithm  Lane Detection Pixel-Stream Algorithm with Zynq-Based Hardware Source Conversion

BLOCK:
 Demux ; SFunction ; Terminator ;?;Abs;Add;AverageLeftWidth;AverageRightWidth;B;BFromFrameBuf;BIn;BOut;BToFrameBuf;Birds-Eye View;BirdsEyeInput;BirdsEyeLaneOverlay;BirdsEyeView;CameraView;CaptureLane;Color Space Converter;ColumnCountNeg;ColumnCountPos;Compare To Constant;Compare To Zero;ComputeEgoLanes;Constant;CtrlIn;CtrlInterface;CtrlOut;Data Type Conversion;Delay;DelayBalance;Discrete FIR Filter;Driver;Enable;FirstPassEgoLane;FitPolyLeftLane;FitPolyRightLane;From;From Multimedia File;G;GFromFrameBuf;GIn;GOut;GToFrameBuf;Gain;Goto;HDL Counter;Histogram;HistogramAddress;HistogramColumnCount;HistogramReadOut;HistogramValid;Im;Im ;ImOut;Image Frame To Pixels ;Image Pixels To Frame;Image Source;In;Index;Inlier;Lane Detection Algorithm;Lane Fit And Overlay Algorithm;LaneCandidateGeneration;LaneCapture;LaneDetection;LaneFit;LaneLeft;LaneLeftin;LaneLeftout;LaneREG1En;LaneREG2En;LaneREG3En;LaneREG4En;LaneREG5En;LaneREG6En;LaneREG7En;LaneREGData;LaneRight;LaneRightin;LaneRightout;LaneWidth;LeftLane;LeftLaneLoc ;LeftLaneOffset;LeftLaneVal;LeftOffset;Logical Operator;Matrix Concatenate;Multiport Switch;NegativeHistogramCount;Out;OverlapandMultiply;OverlayLaneMarkings;OverlayOutput;OverlayPolyLeftLane;OverlayPolyRightLane;P;PeakFIlterAddress;PeakFIlterData;PeakVal;Pixel Control Bus Creator;Pixel Control Bus Selector;Pixel Stream FIFO;Pixel Switch;Poly;PolyLeftLane;PolyRightLane;PositiveHistogramCount;Product;R;RFromFrameBuf;RGB Concatenate;RGB Select;RIn;ROI Selector;ROut;RToFrameBuf;Rate Transition;Reference;RegionCount;RegisterWriteGen;Relational Operator;RemoveOutlier;RightLane;RightLaneLoc;RightLaneOffset;RightLaneVal;RightOffset;Select B;Select G;Select R;Selector;Signal Specification;State Control;StoreDominantLanes;StoreLaneMem;SubSystem;Subsystem;Terminator;TiledROIExractor;UpdateLaneWidth;Valid Switch;Vector Concatenate;VerticallyOrientatedFilter;Video Capture HDMI;Video Frame Buffer;ZeroCrossingDetection;ZeroCrossingFilter;average;controlIn;controlOut;crtlIn;ctrlFromFrameBuf;ctrlIn;ctrlToFrameBuf;data;dataReady;done;enable;enableREG;enable_out;findMin;framePop;frameStart;genTrigger;hwDone;hwStart;ind;indmin;lane;lane1En;lane1In;lane2En;lane2In;lane3En;lane3In;lane4En;lane4In;lane5En;lane5In;lane6En;lane6In;lane7En;lane7In;laneAddress;laneCIn;laneCapture;laneIn;laneREGRST;laneRST;laneVal;leftwidth;matchedHist;minInd;minVal;negHistCount;offsetVal;peakIndex;peakREG;peakVal;peakValueMemory;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut;posHistCount;process;regEnable;regionStart;rightminop;rightwidth;start;swDone;swStart;triggerOut;val;valGreater;valmin;width;zeroCrossingTrue

BLOCKTYPE:
Abs;BusSelector;Color Space Converter;Compare To Constant;Compare To Zero;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;Demux;DiscreteFir;EnablePort;Frame Buffer Simulation;From;From Multimedia File;Gain;Goto;HDL Counter;Histogram;Image Filter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;Logic;MultiPortSwitch;Outport;Pixel Control Bus Creator;Pixel Stream FIFO;Product;RateTransition;RelationalOperator;S-Function;Selector;SignalSpecification;StateControl;Sum;Terminator;To Video Display;VariantSource;visionhdl.BirdsEyeView;visionhdl.ROISelector;visionzynq.internal.VideoCaptureHDMI

BLOCKTYPE_FREQUENCY:
10;4;1;22;9;5;46;1;3;267;6;1;2;1;17;1;4;9;9;4;1;1;1;178;35;62;154;6;1;1;8;21;6;6;21;4;40;16;3;1;3;3;1

PRODUCT:
Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzLaneDetection_02_HardwareInterface
DESCRIPTION: Lane Detection Detect lanes from streaming video.
BLOCKTYPE_FREQUENCY: 2;1;1;1;5;1;17;1;11;4;5;5;5;1;1
CHECKSUM: 4F7EBF3AD72534EBEAB6B77DE685660C
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzLaneDetection_02_HardwareInterface.slx

ANNOTATION:
Vision Zynq Targeted Hardware Interface Model: vzLaneDetection_01_PixelStream Simulink Interface to HW User Logic Vision Zynq Device to Simulink Algorithm This model contains blocks that can be used for simulation with targeted hw user logic. Generated by HDL Workflow Advisor on 28-Jul-2020 19:48:28

BLOCK:
 Demux ; SFunction ; Terminator ;?;BirdsEyeInput;BirdsEyeLaneOV;Delay;Driver;Enable;FitPolyLeftLane;FitPolyRightLane;Im;Im ;ImOut;Index;Lane Detection Algorithm;Lane Fit And Overlay Algorithm;LaneFit;LeftLane;OverlayLaneMarkings;OverlayOutput;OverlayPolyLeftLane;OverlayPolyRightLane;P;Poly;PolyLeftLane;PolyRightLane;Rate Transition;Reference;RightLane;Signal Specification;SubSystem;Vector Concatenate;Video Capture HDMI;dataReady;laneCIn;process;swDone;swStart

BLOCKTYPE:
Concatenate;Constant;CustomCallbackButton;Delay;Demux;EnablePort;Inport;LaneDetec_ip VisionZynq Target Cosimulation;Outport;RateTransition;S-Function;SignalSpecification;Terminator;To Video Display;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzLaneDetection_03_SoftwareInterface
DESCRIPTION: Lane Detection Detect lanes from streaming video.
BLOCKTYPE_FREQUENCY: 1;2;1;1;1;5;1;17;11;4;5;5;5;1;1
CHECKSUM: 786322761D6BFA85BEE48A1518CC10AD
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzLaneDetection_03_SoftwareInterface.slx

ANNOTATION:
Vision Zynq Software Interface Model: vzLaneDetection_01_PixelStream ARM Interface to Vision Zynq Device ARM Interface to HW User Logic This model contains blocks that can be used for software generation. Generated by HDL Workflow Advisor on 28-Jul-2020 19:48:50

BLOCK:
 Demux ; SFunction ; Terminator ;?;BirdsEyeInput;BirdsEyeLaneOV;Delay;Driver;Enable;FitPolyLeftLane;FitPolyRightLane;Im;Im ;ImOut;Index;Lane Detection Algorithm;Lane Fit And Overlay Algorithm;LaneFit;LeftLane;OverlayLaneMarkings;OverlayOutput;OverlayPolyLeftLane;OverlayPolyRightLane;P;Poly;PolyLeftLane;PolyRightLane;Rate Transition;Reference;RightLane;Signal Specification;SubSystem;Vector Concatenate;Video Capture HDMI;dataReady;laneCIn;process;swDone;swStart

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;Concatenate;Constant;CustomCallbackButton;Delay;Demux;EnablePort;Inport;Outport;RateTransition;S-Function;SignalSpecification;Terminator;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Embedded Coder;Embedded Coder Support Package for ARM Cortex-A Processors;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzLowLightEnhancement_PixelStream
BLOCKTYPE_FREQUENCY: 3;4;1;1;52;1;5;1;1;14;1;13;6;1;6;2;1;1;1;1;1
CHECKSUM: 211C54B402E75EBFFA16D32625324903
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzLowLightEnhancement_PixelStream.slx

ANNOTATION:
EnhancementFactor Conversion Copyright 2019-2023 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Low Light Enhancement Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
?;Add;B;BIn;BOut;Constant;CtrlIn;CtrlOut;DarkChannel;Data Type Conversion;Delay;Enhance- ment;From Multimedia File;G;GIn;GOut;HazeFactor;Image Filter;Image Frame To Pixels ;Image Pixels To Frame;Image Source;InvOut;Inversion;IterativeFilter;LowLight Enhancement Algorithm;Matrix Concatenate;PixIn;Pixel Stream Aligner;Pixel-Stream Output;Product;R;RGB Concatenate;RGB Select;RIn;ROut;Rate Transition;Reciprocal;Reference;Select B;Select G;Select R;Selector;SubSystem;Subtract;Terminator;Vector Concatenate;Video Capture HDMI;ctrlIn;ctrlOut;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;From Multimedia File;Image Filter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;MinMax;Outport;Product;RateTransition;Selector;Sum;Terminator;To Video Display;VariantSource;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzMultiPixMultiComp_PixelStream
BLOCKTYPE_FREQUENCY: 1;1;7;1;1;1;5;1;1;1;1;22;1;18;6;20;1;1;1;1;1;1
CHECKSUM: A790FB522A22EA3C5CB159151C9C28AF
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzMultiPixMultiComp_PixelStream.slx

ANNOTATION:
Conversion Source Algorithm Display Conversion Copyright 2021 -2023 The MathWorks, Inc.  MultiPixel-MultiComponent Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
15x15 Blur;?;Add;B;BIn;BOut;BlendBloom;Bloom;BrightSpotFilter;Color Space Converter;Compare To Constant;Constant;CtrlIn;CtrlOut;Delay;For Each;From Multimedia File;G;GIn;GOut;Image Filter;Image Frame To Pixels ;Image Pixels To Frame;Image Source;Matrix Concatenate;MultiPixelColorSpaceConverter;MultiPixelToRGBVec;Multiport Switch;Pixel Stream Aligner;Pixel-Stream Output;R;RGB;RGB Concatenate;RGB Select;RGBVecToMultiPixel;RIn;ROut;Reference;Reshape;Selector;SubSystem;Terminator;Vector Concatenate;Video Capture HDMI;ctrlIn;ctrlOut;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut;refpixelIn

BLOCKTYPE:
Color Space Converter;Compare To Constant;Concatenate;Constant;CustomCallbackButton;Delay;ForEach;From Multimedia File;Image Filter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;MultiPortSwitch;Outport;Reshape;Selector;Sum;Terminator;To Video Display;VariantSource;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzPotholeDetection_PixelStream
BLOCKTYPE_FREQUENCY: 4;57;9;1;1;9;6;3;31;1;17;82;1;1;1;3;1;1;1;4;10;1;1;93;27;5;2;4;3;79;1;6;9;9;8;20;20;4;6;1;1;1;1;1;1
CHECKSUM: F4620A9DF91E04AF5E262EAD34CA8D6A
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzPotholeDetection_PixelStream.slx

ANNOTATION:
Check for updated string wait one frame, then trigger at the start of all other frames Processor Algorithm Conversion Copyright 2017 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Pothole Detection and Text Overlay Pixel-Stream Algorithm with Zynq-Based Hardware Frame Buffer Model

BLOCK:
1-D Lookup Table;?;Add;Align;Area Threshold;AreaThresh;AreaThreshOut;B;BFromFrameBuf;BIn;BOut;BToFrameBuf;BWCtrlIn;BWIn;Bilateral Filter;Bit Concat;Bit Slice;Cartoon RGB;Centroid;CentroidKernel;Closing;Color Space Converter;Compare To Constant;Compare To Zero;Constant;CtrlIn;CtrlOut;CtrlOut ;Data Type Conversion;Delay;DetectAndHold;DetectOut;Display;Dual Port RAM;Edge Detector;EnTapDelay;Enable;ExpandData;Fiducial31x;For Each;For Each Subsystem;FrameBoundary;From Multimedia File;G;GFromFrameBuf;GIn;GOut;GToFrameBuf;Gain;GradThresh;Gradient Threshold;HDL Counter;HVCounters;Image Frame To Pixels ;Image Pixels To Frame;Image Source;In;Index Vector;KeyIn;LED;Line Buffer;LineCount;LineRGB;Logical Operator;Matrix Concatenate;MinMax;Mux;OR;Out;Overlay;Overlay32x;OverlayRGB;OverlayTransp;Pixel Control Bus Creator;Pixel Control Bus Selector;Pixel-Stream Output;PixelCount;PixelOut;Pothole Detection Algorithm;Product;R;RFromFrameBuf;RGB Concatenate;RGB Select;RGBCtrlIn;RGBIn;RGBOut;RGBin;RGBout;RIn;ROut;RToFrameBuf;Reference;Relational Operator;Select B;Select G;Select R;Selector;Show Raw;ShowRaw;ShowRawIn;State Control;StringIn;SubSystem;Subsystem;Subtract;Sum;Switch;SwitchStream;Tapped Delay;Terminator;Text String;TextString;ThreshIn;ThreshOut;ToBits;TrapezoidalMask;UpdateText;Vector Concatenate;Video Capture HDMI;Video Frame Buffer;area;areaIn;areaThresh;bottomEdge;char ROM;ctrl;ctrlFromFrameBuf;ctrlIn;ctrlOut;ctrlToFrameBuf;curLine;dataIn;dataOut;detectIn;detectOut;en;enable;enableLD;fiducial ROM;genTrigger;hCount;in;isValidIdx;leftEdge;leftIdxValid;maxReg;notvEnd;overlayAlpha;overlayRGB;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelVectIn;popFrame;posOnly;posOut;rgbIn;rgbOut;rightEdge;rightIdxValid;shiftIn;showRaw;sum;sumOut;textString;topEdge;triggerOut;vCount;wrAddr;wrData;wrEn;xCenter;xLoc;xLocIn;xLocOut;yCenter;yLoc;yLocIn;yLocOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusSelector;Closing;Color Space Converter;Compare To Constant;Compare To Zero;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;Display;Dual-port RAM;Edge Detector;EnablePort;ForEach;Frame Buffer Simulation;From Multimedia File;Gain;HDL Counter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;Logic;Lookup_n-D;MinMax;MultiPortSwitch;Mux;Outport;Pixel Control Bus Creator;Product;RelationalOperator;Selector;StateControl;Sum;Switch;Tapped Delay Line;Terminator;To Video Display;VariantSource;visionhdl.BilateralFilter;visionhdl.LineBuffer;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzSharpen_PixelStream
BLOCKTYPE_FREQUENCY: 1;3;3;1;1;15;1;1;1;1;1;3;1;16;6;10;1;1;1;1;1;2;2;1;2;1;1;1;1
CHECKSUM: 5028CF93B76F8CC062B5CAD7C854330E
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzSharpen_PixelStream.slx

ANNOTATION:
Conversion Copyright 2016-2023 The MathWorks, Inc. Pixel-Stream Algorithm Compare and Display Conversion  Image Sharpening Pixel-Streaming Algorithmwith Zynq-Based Hardware Source

BLOCK:
 Demux ; SFunction ; Terminator ;?;Align Video;Bit Slice;Blur Image;Constant;CtrlIn;CtrlOut;DIPSwitch;DS0 Sharpen;Data Type Conversion Inherited;Delay;Display;FIFO;From;From Multimedia File;Goto;HDL Counter;Image Filter;Image Sharpening Algorithm;Image Source;ImageIn;ImageOut;In;LED;Logical Operator;Out;Pixel Control Bus Selector;Pixel-Stream Output;Pop;Push;Rate Transition;Reference;Signal Specification;Simple Dual Port RAM;Source Output;SubSystem;Switch;Terminator;Unit Delay Enabled Resettable;Video Capture HDMI;Y Frame To Pixels;Y Pixels To Frame;Y Resize;YIn;YOut;YOutOrig;YOutSharp;ctrlIn;ctrlInDelayed;ctrlOut;dsSharpen;original;pixel;pixelInDelayed;rst_FIFO;sharpened;switch

BLOCKTYPE:
Bit Slice;BusSelector;Constant;Conversion Inherited;CustomCallbackButton;Delay;Demux;Display;From;From Multimedia File;Goto;HDL Counter;Image Filter;Inport;Logic;Outport;RateTransition;S-Function;SignalSpecification;Simple Dual-port RAM;Switch;Terminator;Unit Delay Enabled Resettable;VariantSource;VideoViewer;Y Frame To Pixels;Y Pixels To Frame;Y Resize;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Image Processing Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzVisionAlgorithmWorkflow
BLOCK: ?;SubSystem;Subsystem
BLOCKTYPE: CustomCallbackButton
BLOCKTYPE_FREQUENCY: 1
CHECKSUM: 969709FA80A6586AC57BB6EEEC2E7B99
PRODUCT: Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/examples_resources/models/vzVisionAlgorithmWorkflow.slx

ANNOTATION:
 This example shows how to use the Xilinx Zynq-Based Vision Support Package with Simulink for developing vision algorithms. It uses several models to show the gradual progression from a behavioral algorithm to a fully deployed target system running that algorithm. Open the full write-up by double clicking the Info block. Open individual models in the workflow by clicking the appropriate blocks below. Developing Vision Algorithms for Zynq-Based Hardware Copyright 2016 The MathWorks, Inc.


MODELNAME: vzBilateral_PixelStream
BLOCKTYPE_FREQUENCY: 1;2;2;3;6;1;14;1;1;1;2;1;1;1;1;26;1;20;3;6;3;1;1;1;1;1;1
CHECKSUM: 3C4FD4F234EA40F1634F5B2C99F01A3C
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzBilateral_PixelStream.slx

ANNOTATION:
Conversion Copyright 2017-2023 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Bilateral Filter Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
?;Align;B;BIn;BOut;Bilateral Filter;Bilateral Filter Algorithm;BinaryIn;BinaryOut;BinaryToRGB;Bit Slice;Color Space Converter;Constant;CtrlIn;CtrlOut;Delay;Display;Edge Detector;Edges;FrameBoundary;From Multimedia File;G;GIn;GOut;Gain;HDL Counter;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;LED;Logical Operator;Matrix Concatenate;Overlay;OverlayColor;PB0 Show Edge Only;Pixel Control Bus Selector;Pixel-Stream Output;PushButton;Quantize;R;RGB Concatenate;RGB Select;RGBIn;RGBOut;RIn;ROut;Rate Transition;Reference;SW Cfg Gradient Threshold;SW Cfg Overlay Color ;Select B;Select G;Select R;Selection Subsystem;Selector;SubSystem;Switch;Terminator;ThreshIn;ThreshOut;Vector Concatenate;Video Capture HDMI;cGradientThresh;cOverlayColor;ctrl;ctrlIn;ctrlOut;pbEdgeOnly;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Slice;BusSelector;Color Space Converter;Concatenate;Constant;CustomCallbackButton;Delay;Display;Edge Detector;From Multimedia File;Gain;HDL Counter;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Logic;Outport;RateTransition;Selector;Switch;Terminator;To Video Display;VariantSource;visionhdl.BilateralFilter;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzCarCounting_01_FrameBased
BLOCKTYPE_FREQUENCY: 1;3;1;2;1;4;1;1;1;2;1;1;1;1
CHECKSUM: 8B9F2A5B33BC4C7870D5B4F77DC4C40A
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzCarCounting_01_FrameBased.slx

ANNOTATION:
Copyright 2017 -2023 The MathWorks Inc. Algorithm Display  Tracking Cars Using Foreground Detection Algorithm with Zynq-Based Hardware Source

BLOCK:
?;BBox;Blob Analysis;Car Tracking Algorithm;Constant;Count;Draw Shapes;From Multimedia File;Image Source;In;Insert Text;Median Filter;Out;Overlay Results;ROI;Reference;Results;SubSystem;Text Background;Video Capture HDMI;Video In;Video Out;vision.ForegroundDetector;x position;y position

BLOCKTYPE:
Blob Analysis;Constant;CustomCallbackButton;Draw Shapes;From Multimedia File;Inport;Insert Text;MATLABSystem;Median Filter;Outport;Selector;VariantSource;VideoViewer;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzCarCounting_02_SwTargeting
BLOCKTYPE_FREQUENCY: 1;3;1;2;4;1;1;1;2;1;1;1
CHECKSUM: DE44CDEAEC1B905DADDB5AE20EC6B683
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzCarCounting_02_SwTargeting.slx

ANNOTATION:
Copyright 2017-2023 The MathWorks Inc.  Tracking Cars Using Foreground Detection Algorithm with Zynq-Based Hardware (Software Targeting Model) Algorithm Display Source

BLOCK:
?;BBox;Blob Analysis;Car Tracking Algorithm;Constant;Count;Draw Shapes;In;Insert Text;Median Filter;Out;Overlay Results;ROI;Reference;Results;SubSystem;Text Background;Video Capture HDMI;Video In;Video Out;vision.ForegroundDetector;x position;y position

BLOCKTYPE:
Blob Analysis;Constant;CustomCallbackButton;Draw Shapes;Inport;Insert Text;MATLABSystem;Median Filter;Outport;Selector;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzCorner_PixelStream
BLOCKTYPE_FREQUENCY: 1;1;2;1;3;9;1;5;106;1;1;2;1;5;1;1;1;37;29;8;4;1;6;5;3;4;1;1;1;1
CHECKSUM: 9AB62BE7BDD959B514B02354231D9977
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzCorner_PixelStream.slx

ANNOTATION:
Conversion Copyright 2016 -2023 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Corner Detection and Image Overlay Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
?;Add;B;BIn;BOut;BinaryIn;BinaryOut;BinaryToRGB;Bit Slice;Color Space Converter;Compare To Constant;Constant;Convert Levels;Corner Overlay Algorithm;CtrlIn;CtrlOut;CtrlOut ;Data Type Conversion;Delay;Display;Edges;From Multimedia File;G;GIn;GOut;Gain;GaussianGx;GaussianGy;GaussianGyGx;GradX;GradY;Gradients;Gradx;Grady;Gx;GxSquared;Gy;GyGx;GySquared;HDL Counter;HarrisIn;HarrisOut;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;LED;Matrix Concatenate;Overlay;OverlayColor;OverlayTransp;PB0 Show Corner Only;Pixel Control Bus Selector;Pixel Stream Aligner;Pixel-Stream Output;PixelOut;Product;PushButton;R;RGB Concatenate;RGB Select;RGB2Bin;RGBIn;RGBOut;RGBout;RIn;ROut;Rate Transition;Reference;Relational Operator;SW Cfg Overlay Color ;SW Cfg Overlay Transparency;SW Cfg Slice Level;Select B;Select G;Select R;Selection Subsystem;Selector;SliceLevel;SquareComp;SubSystem;Sum;Switch;Terminator;Vector Concatenate;Video Capture HDMI;cOverlayColor;cOverlayTransp;cSliceLevel;ctrl;ctrlIn;ctrlOut;det_trace;pbCornerOnly;pixel;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Slice;BusSelector;Color Space Converter;Compare To Constant;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;Display;From Multimedia File;Gain;HDL Counter;Image Filter;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Outport;Product;RateTransition;RelationalOperator;Selector;Sum;Switch;Terminator;To Video Display;VariantSource;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzEdge_01_FrameBased
BLOCKTYPE_FREQUENCY: 2;1;6;1;1;1;1;1;13;6;2;4;2;5;3;1;1;1
CHECKSUM: C88D81AA82714E632A7B1BB8D58EEBF6
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzEdge_01_FrameBased.slx

ANNOTATION:
Display Algorithm Source  Edge Detection and Image Overlay Frame-Based Algorithm with Zynq-Based Hardware  Copyright 2016-2023 The MathWorks, Inc.

BLOCK:
?;Add;Bus Creator;Bus Selector;CbIn;CbOut;Constant;CrIn;CrOut;DIPSwitch;DS0 Grayscale;Edge Detection;Edges;Frame Rate;Frame-Based Edge Overlay Algorithm;From Multimedia File;Gain;Image Source ;Original Image;Output Image;Overlay;PB0 Show Edge Only;Product;PushButton;Rate Transition;Reference;SW Cfg Alpha;SW Cfg Threshold;Selection Subsystem;SubSystem;Switch;Video Capture HDMI;YIn;YOut;cAlpha;cThreshold;dsGrayscale;pbEdgeOnly

BLOCKTYPE:
BusCreator;BusSelector;Constant;CustomCallbackButton;Edge Detection;Frame Rate Display;From Multimedia File;Gain;Inport;Outport;Product;RateTransition;Sum;Switch;To Video Display;VariantSource;VideoViewer;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzEdge_02_PixelStream
BLOCKTYPE_FREQUENCY: 1;3;2;2;1;10;1;24;4;1;1;1;1;1;44;26;3;4;8;2;4;9;1;2;1;1;1;1;1;1
CHECKSUM: B1ED4BE946FA819D300CFA604ECB969C
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzEdge_02_PixelStream.slx

ANNOTATION:
1 Conversion Copyright 2016 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Edge Detection and Image Overlay HDL Pixel-Streaming Algorithm with Zynq-Based Hardware  Frame-Based Algorithm

BLOCK:
 ;?;Add;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CbCr;CbCrIn;CbCrOut;CbIn;CbOut;Compare HDL User Logic with Behavioral;Constant;CrIn;CrOut;CtrlIn;CtrlOut;DIPSwitch;DS0 Grayscale;Delay;Display;Edge Detection;Edge Detector;Edge Overlay Algorithm;EdgeIn;EdgeOut;Edges;Frame-Based Output;From Multimedia File;Full-Frame Behavioral Algorithm;Gain;HDL Counter;Image Overlay;Image Source;LED;Overlay;OverlayOut;PB0 Show Edge Only;PSNR;PSNR for Cb;PSNR for Cr;PSNR for Y;Pixel Control Bus Selector;Pixel Stream Aligner;Pixel-Stream Output;Product;PushButton;Rate Transition;Reference;SW Cfg Alpha;SW Cfg Threshold;Select Interleaved CbCr;Select Y;Selection Subsystem;SubSystem;Switch;Terminator;Threshold;Vector Concatenate;Video Capture HDMI;Y;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr 4:2:2 Resize;YCbCr From Scalar;YCbCr To Scalar;YIn;YOut;alpha;behCb;behCr;behY;cAlpha;cThreshold;ctrlIn;ctrlOut;dsGrayscale;hdlCb;hdlCr;hdlY;pbEdgeOnly;pixelCtrl;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Concatenate;Constant;CustomCallbackButton;Delay;Display;Edge Detection;Edge Detector;From Multimedia File;Gain;HDL Counter;Inport;Outport;PSNR;Product;RateTransition;Selector;Sum;Switch;Terminator;To Video Display;VariantSource;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr Resize;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzEdge_03_TargetSource
BLOCKTYPE_FREQUENCY: 1;3;2;2;1;8;1;21;1;1;1;1;1;25;17;2;4;2;2;4;1;1;1;1;1;1;1;1
CHECKSUM: 7296220E0E49A598CC3F31AB7EAF9F4C
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzEdge_03_TargetSource.slx

ANNOTATION:
1 Copyright 2016-2023 The MathWorks, Inc. Source Display  Edge Detection and Image Overlay Pixel-Stream Algorithm with Zynq-Based Hardware (Hardware Targeting Model) Conversion Pixel-Stream Algorithm Conversion

BLOCK:
?;Add;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CbCr;CbCrIn;CbCrOut;Constant;CtrlIn;CtrlOut;DIPSwitch;DS0 Grayscale;Delay;Display;Edge Detection;Edge Detector;Edge Overlay Algorithm;EdgeIn;EdgeOut;Edges;Frame Rate;From Multimedia File;HDL Counter;Image Overlay;Image Source;LED;Output Image;Overlay;OverlayOut;PB0 Show Edge Only;Pixel Control Bus Selector;Pixel Stream Aligner;Product;PushButton;Rate Transition;Reference;SW Cfg Alpha;SW Cfg Threshold;Select Interleaved CbCr;Select Y;Selection Subsystem;SubSystem;Switch;Terminator;Threshold;Vector Concatenate;Video Capture HDMI;Y;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr 4:2:2 Resize;YCbCr From Scalar;YCbCr To Scalar;YIn;YOut;alpha;cAlpha;cThreshold;ctrlIn;ctrlOut;dsGrayscale;pbEdgeOnly;pixelCtrl;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Concatenate;Constant;CustomCallbackButton;Delay;Display;Edge Detector;Frame Rate Display;From Multimedia File;HDL Counter;Inport;Outport;Product;RateTransition;Selector;Sum;Switch;Terminator;To Video Display;VariantSource;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr Resize;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzEdge_03_TargetSource_interface_saved
BLOCKTYPE_FREQUENCY: 1;2;1;1;2;1;1
CHECKSUM: 2E855E9D0DE897C81DD8791B5187DEA4
PRODUCT: Computer Vision Toolbox;Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzEdge_03_TargetSource_interface_saved.slx

ANNOTATION:
Vision Zynq Software Interface Model: vzEdge_03_TargetSource This model contains blocks that can be used for software generation. Generated by HDL Workflow Advisor on 20-Jan-2017 12:32:04 ARM Interface to Vision Zynq Device ARM Interface to HW User Logic

BLOCK:
?;Edge Overlay Algorithm;Frame Rate Display;Reference;SW Cfg Alpha;SW Cfg Threshold;Terminator;Video Capture HDMI;Video Viewer

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;Constant;CustomCallbackButton;Frame Rate Display;Terminator;VideoViewer;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzEdge_03_TargetSource_tgthw_interface_saved
BLOCKTYPE_FREQUENCY: 2;1;1;1;1;1
CHECKSUM: 6EAABE89EEA5AE766454E9A5B9F1AAA7
PRODUCT: Computer Vision Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzEdge_03_TargetSource_tgthw_interface_saved.slx

ANNOTATION:
Vision Zynq Targeted Hardware Interface Model: vzEdge_03_TargetSource This model contains blocks that can be used for simulation with targeted hw user logic. Generated by HDL Workflow Advisor on 20-Jan-2017 12:31:50 Simulink Interface to HW User Logic Vision Zynq Device to Simulink Algorithm

BLOCK:
?;Behavioral Algorithm Output Display;Edge Overlay Algorithm;Frame Rate Display;Reference;SW Cfg Alpha;SW Cfg Threshold;Video Capture HDMI

BLOCKTYPE:
Constant;CustomCallbackButton;EdgeOverl_ip VisionZynq Target Cosimulation;Frame Rate Display;To Video Display;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzFogRectification_PixelStream
BLOCKTYPE_FREQUENCY: 2;1;36;4;33;1;8;148;1;1;12;1;2;12;21;1;1;1;1;1;61;22;4;54;15;6;9;2;14;18;2;2;1;3;1;1;1
CHECKSUM: F9564997FD952F476D50BD1BCC9D71EF
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzFogRectification_PixelStream.slx

ANNOTATION:
logic to find porch+number of columns (o1/i1)*(0:I1) CALCULATION o1/i1 CALCULATION CONVERSION TO UPCOUNTER (0 TO i1) DESIGN OF DOWNCOUNTER FROM i1 TO 0 CIRCUIT FOR POPPING t1 WHEN i2 CALCULATION IS DONE ((o2-o1) / (i2 - i1)) * i1 UPCOUNTER FROM i1+1 TO i2 DOWN COUNTER FROM i2 TO 0 ((o2-o1 / (i2 - i1)) * (i1+1:i2) t2 = ( (((o2-o1) / (i2 - i1)) * (i1+1:i2)) - (((o2-o1) / (i2 - i1)) * i1) ) + o1 COUNTER DESIGN FROM i2 to 255 (255-o2) / (255 - i2) * i2 ( ((255-o2) / (255 - i2) * (i2+1 :255)) - ((255 -o2) / (255 - i2))*i2 ) t3 = ( ((255-o2) / (255 - i2) * (i2+1 :255)) - ((255 - o2) / (255 - i2))*i2 ) + o2 Histogram Calculation and Normalization Contrast Stretching - LUT Contrast Stretching - T calculation Source Conversion Pixel-Stream Algorithm Conversion Compare and Display Frame Buffer Model  Fog Rectification Pixel-Stream Algorithm with Zynq-Based Hardware Copyright 2020-2021 The MathWorks, Inc.

BLOCK:
 Delay;?;AND;Add;B;BIn;BOut;Bilateral Filter;BtoFramebuffer;Compare To Constant;Constant;ContrastEnhancement;CounterForWriteAddress;CtrlIn;CtrlOut;DarkChannel;Data Type Conversion;Delay;DiffOfInputAndDiffim;Enable;Enabled Subsystem;FactorCalculation;Fog Rectification Algorithm;FogOutputView;FogRemoval;From;From Multimedia File;G;GIn;GOut;Gain;GeneratePopForImageBuffer;Goto;GtoFramebuffer;HDL Counter;HDL FIFO;HistNormAndCDFCalculation;Histogram;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;In;InputBuffer;LUT;Matrix Concatenate;Max;NOT;OR;Out;Pixel Control Bus Selector;Pixel Stream Aligner;Pixel-Stream Output;Pixel-Stream input;Product;R;RGB Concatenate;RGB Select;RGBtoGray;RIn;ROut;Reciprocal;Reference;Relational Operator;Restoration;RtoFramebuffer;ScaledInput;Select B;Select G;Select R;Selector;Simple Dual Port RAM;SubSystem;Subtract;Switch;T;TCalculation;Terminator;TgenEnb;Vector Concatenate;Video Capture HDMI;Video Frame Buffer;bufferB;bufferG;bufferR;busOutAfterConv;cdf;ctrlBus;ctrlBusIn;ctrlBusOut;ctrlIn;ctrlOut;darkCh;dataIn;defogCtrlOut;defogPixOut;diffOfIpAnddiffim;diffimAfterConv;diffimAfterReduction;diffimForRestoration;diffimForRst;enablei;factor;hdlOutput;histVal;i;i1Andi2Calculation;i1Calculation ;i1Val;i2Calculation;i2HighEnable;i2Val;min;outB;outG;outR;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut;pop;popVB;rdValid;scaledPixelIn;t;t1Calculation;t1Enable;t2Calculation;t2Enable;t2Rst;t3Calculation;t3Enable;validFromHist;validHist;writeAddress;writeEnable

BLOCKTYPE:
BusSelector;Color Space Converter;Compare To Constant;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;EnablePort;Frame Buffer Simulation;From;From Multimedia File;Gain;Goto;HDL Counter;HDL_FIFO;Histogram;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Logic;MinMax;Outport;Product;RelationalOperator;Selector;Simple Dual-port RAM;Sum;Switch;Terminator;To Video Display;VariantSource;hdl.RAM;visionhdl.BilateralFilter;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzGamma_PixelStream
BLOCKTYPE_FREQUENCY: 2;4;1;1;1;1;2;1;1;6;1;1;1;1;17;16;1;3;2;3;1;1;1
CHECKSUM: E0D5FEF9B8B1B5B9B09AAABEC928A07F
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzGamma_PixelStream.slx

ANNOTATION:
Conversion Copyright 2016 -2023 The MathWorks Inc. Pixel-Stream Algorithm Compare and Display Conversion  Gamma Correction Pixel-Streaming Algorithmwith Zynq-Based Hardware Source

BLOCK:
?;B;BIn;BOut;Bit Concat;Bit Slice;CtrlIn;CtrlOut;DIPSwitch;DS0 Correct;Delay;Display;From Multimedia File;G;GIn;GOut;Gamma Correction Algorithm;Gamma Corrector;Gamma Corrupt;HDL Counter;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Source;LED;Pixel Control Bus Selector;Pixel-Stream Output;R;RGB Concatenate;RGB Pixel Splice;RGB Select;RGBIn;RIn;ROut;Rate Transition;Reference;Select B;Select G;Select R;SubSystem;Switch;Terminator;Vector Concatenate;Video Capture HDMI;correctedCtrl;correctedPixel;corruptCtrl;corruptPixel;ctrl;dsCorrect;pixel;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;switch

BLOCKTYPE:
Bit Concat;Bit Slice;BusSelector;Concatenate;Constant;CustomCallbackButton;Delay;Display;From Multimedia File;Gamma Corrector;HDL Counter;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Outport;RateTransition;Selector;Switch;Terminator;To Video Display;VariantSource;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzGettingStartedMIPI
ANNOTATION: Getting Started with MIPI Sensor Copyright 2022 The MathWorks, Inc.
BLOCK: ?;Reference;To Video Display;Video Capture MIPI
BLOCKTYPE: CustomCallbackButton;To Video Display;visionzynq.internal.VideoCaptureMIPI
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: DEE225C11EC8544A22FF34B6C9E0D835
PRODUCT: Computer Vision Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzGettingStartedMIPI.slx


MODELNAME: vzHistogramEqualization_PixelStream
BLOCKTYPE_FREQUENCY: 3;8;2;3;1;2;2;1;1;43;2;2;1;1;4;1;39;1;35;1;1;2;4;1;1;1;3;3;1;1;1;1;1;1
CHECKSUM: B9F8258898F38DD8771BE6A6C549C9BA
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzHistogramEqualization_PixelStream.slx

ANNOTATION:
internally pipelined with 1 register before multiplier and 1 register after multiplier. ~ Delay = 2  Frame Buffer Model Conversion Display Conversion Source  Histogram Equalization Algorithm with Zynq-Based Hardware and External Memory Frame Buffer Pixel-Stream Algorithm Copyright 2018 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;?;Apply Equalization;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CDFOut;CbCr;CbCrFromFrameBuf;CbCrIn;CbCrOut;CbCrToFrameBuf;Compare To Constant;Constant;Contrast Adjustment;CtrlIn;CtrlOut;Delay;Display;FrameSize;From Multimedia File;HDL Counter;HGComputationRdy;HGEqualization;HSize;Histogram;Histogram Computation;Histogram Equalization Algorithm;HistogramDone;Image Source;Index Vector;LED;Matrix Concatenate;PB0 Bypass Algorithm;Pixel Control Bus Selector;Pixel-Stream Output;PixelIn;Product;Rate Transition;Reference;Select Interleaved CbCr;Select Y;Selector;Signal Specification;State Control;SubSystem;Sum;Switch;Terminator;VSize;Vector Concatenate;Video Capture;Video Frame Buffer;Y;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr 4:2:2 Resize;YCbCr From Scalar;YCbCr To Scalar;YFromFrameBuf;YIn;YOut;YToFrameBuf;accmHist;accm_hist;applyEq;binReset;bypass;cdf;cdfVectorGen;cdf_vector;ctrl;ctrlBusIn;ctrlFromFrameBuf;ctrlIn;ctrlOut;ctrlToFrameBuf;detectFrameSize;done;err;errorLED;f;frameSize;histComp;histEqData;hist_accum;hist_data;im;pbBypass;pctrlOut;pdataOut;pfifoCtrlIn;pfifoDataIn;pixel;pixelCtrl;pixelData;pixelFromFrameBuf;pixelIn;pixelOut;popFrame;readDone;valid;validOut;y;ycdf

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Contrast Adjustment;CustomCallbackButton;Delay;Demux;Display;Frame Buffer Simulation;From Multimedia File;HDL Counter;Histogram;Inport;MultiPortSwitch;Outport;Product;RateTransition;S-Function;Selector;SignalSpecification;StateControl;Sum;Switch;Terminator;To Video Display;VariantSource;YCbCr 4:2:2 Frame To Pixels;YCbCr 4:2:2 Pixels To Frame;YCbCr Resize;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzImageRotation_PixelStream
BLOCKTYPE_FREQUENCY: 1;1;6;4;8;6;3;18;2;1;4;9;3;1;14;1;4;6;2;1;1;1;83;73;1;68;2;1;3;3;9;3;4;7;11;1;4;12;1;3;1
CHECKSUM: 3B2ADEFC7724351ACFFFDF0AB2F63B70
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzImageRotation_PixelStream.slx

ANNOTATION:
Conversion Copyright 2018 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Image Rotation Algorithm with Zynq-Based Hardware and AXI Master External Memory Access External Memory with AXI Interface

BLOCK:
 Demux ; SFunction ; Terminator ; ackIn==;?;AXIReadCtrlIn;AXIReadCtrlOut;AXIReadData;AXIWriteCtrlIn;AXIWriteCtrlOut;AXIWriteData;AXIWritedata;AckGen;Add;B;BIn;BOut;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;BusCreator;Column_Counter;Compare To Constant;Constant;CtrlIn;CtrlOut;Data Type Conversion;Delay;Display;External Memory;From;From Multimedia File;FromMemory;G;GIn;GOut;Goto;HDL Counter;HDL FIFO;Image Frame To Pixels ;Image Pixels To Frame;Image Resize;Image Rotation Algorithm;Image Source;In;LED;Line_Counter;Logical Operator;MATLAB Function;MATLAB System;Out;PB0 Show ROI Only;Pixel Control Bus Selector;Pixel-Stream Output;Product;PushButton;Q;R;RGB Concatenate;RGB Select;RGBOut;RIn;ROI;ROI Selector;ROut;Rate Transition;ReadCtrl;ReadTrigger;ReadTriggered;Reference;Relational Operator;Rotated;S;Select B;Select G;Select R;Selector;Signal Specification;Start;SubSystem;Switch;Terminator;ToMemory;Unit Delay;ValAddEnb;ValwrLenCnt;Vector Concatenate;Video Capture HDMI;Wr_control;WriteCtrl;ack;ackIn;ackIn Posedge Detect;ackIn_d;ackIn_d1==;ackOut;afull;axiWrLen;axiWrLen!=;axiWrLen-1==cnt & axiWrLen!=0 ;axiWrLen==cnt+;axi_rd_add;axi_rd_len;axi_rd_ready;axi_rd_val;axi_wr_en;axi_wr_length;axim_ack;axim_rd_addr;axim_rd_aready;axim_rd_avalid;axim_rd_dready;axim_rd_dvalid;axim_rd_len;axim_wr_ack;axim_wr_addr;axim_wr_enb;axim_wr_len;axim_wr_ready;cache_reg;ctrl;data_fwft_fifo;data_in;data_out;ddr_ack_d;dtci;edgeDet;empty_i;empty_o;full;fwft_logic;if cnt < axiWrLen;out_reg;pbROIOnly;ping_pong;pixel;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pop_o;push;ram_addr;ram_rd_addr;ram_rd_val;ram_wr_addr;ram_wr_enb;ram_wr_enb cond;rd_ack;rd_control;readTrigger;sr_latch;start;triggerMemory;vEnd;vStart;valAddEnb;valid;wrEnb;wr_ack;wr_addr-;wr_enb;wr_len;wr_leng;writeTrigger

BLOCKTYPE:
Bit Concat;Bit Shift;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Conversion Inherited;CustomCallbackButton;DataTypeConversion;Delay;Demux;Display;From;From Multimedia File;Goto;HDL Counter;HDL_FIFO;Image Pixels To Frame;Image Resize;Image Y Frame To Pixels;Inport;Logic;MATLABSystem;Outport;Product;RateTransition;RelationalOperator;S-Function;Selector;SignalSpecification;Sum;Switch;Terminator;To Video Display;Unit Delay Enabled;UnitDelay;VariantSource;visionhdl.ROISelector;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzLaneDetection_01_PixelStream
CHECKSUM: E23FD02741899481D85AE44D3BA77951
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzLaneDetection_01_PixelStream.slx

ANNOTATION:
offset columns pipelining wait 3 full frames before triggering output at input frame rate Frame Buffer Model Conversion Compare and Display Algorithm Copyright 2017-2018 The MathWorks, Inc. Pixel-Stream Algorithm  Lane Detection Pixel-Stream Algorithm with Zynq-Based Hardware Source Conversion

BLOCK:
 Demux ; SFunction ; Terminator ;?;Abs;Add;AverageLeftWidth;AverageRightWidth;B;BFromFrameBuf;BIn;BOut;BToFrameBuf;Birds-Eye View;BirdsEyeInput;BirdsEyeLaneOverlay;BirdsEyeView;CameraView;CaptureLane;Color Space Converter;ColumnCountNeg;ColumnCountPos;Compare To Constant;Compare To Zero;ComputeEgoLanes;Constant;CtrlIn;CtrlInterface;CtrlOut;Data Type Conversion;Delay;DelayBalance;Discrete FIR Filter;Driver;Enable;FirstPassEgoLane;FitPolyLeftLane;FitPolyRightLane;From;From Multimedia File;G;GFromFrameBuf;GIn;GOut;GToFrameBuf;Gain;Goto;HDL Counter;Histogram;HistogramAddress;HistogramColumnCount;HistogramReadOut;HistogramValid;Im;Im ;ImOut;Image Frame To Pixels ;Image Pixels To Frame;Image Source;In;Index;Inlier;Lane Detection Algorithm;Lane Fit And Overlay Algorithm;LaneCandidateGeneration;LaneCapture;LaneDetection;LaneFit;LaneLeft;LaneLeftin;LaneLeftout;LaneREG1En;LaneREG2En;LaneREG3En;LaneREG4En;LaneREG5En;LaneREG6En;LaneREG7En;LaneREGData;LaneRight;LaneRightin;LaneRightout;LaneWidth;LeftLane;LeftLaneLoc ;LeftLaneOffset;LeftLaneVal;LeftOffset;Logical Operator;Matrix Concatenate;Multiport Switch;NegativeHistogramCount;Out;OverlapandMultiply;OverlayLaneMarkings;OverlayOutput;OverlayPolyLeftLane;OverlayPolyRightLane;P;PeakFIlterAddress;PeakFIlterData;PeakVal;Pixel Control Bus Creator;Pixel Control Bus Selector;Pixel Stream FIFO;Pixel Switch;Poly;PolyLeftLane;PolyRightLane;PositiveHistogramCount;Product;R;RFromFrameBuf;RGB Concatenate;RGB Select;RIn;ROI Selector;ROut;RToFrameBuf;Rate Transition;Reference;RegionCount;RegisterWriteGen;Relational Operator;RemoveOutlier;RightLane;RightLaneLoc;RightLaneOffset;RightLaneVal;RightOffset;Select B;Select G;Select R;Selector;Signal Specification;State Control;StoreDominantLanes;StoreLaneMem;SubSystem;Subsystem;Terminator;TiledROIExractor;UpdateLaneWidth;Valid Switch;Vector Concatenate;VerticallyOrientatedFilter;Video Capture HDMI;Video Frame Buffer;ZeroCrossingDetection;ZeroCrossingFilter;average;controlIn;controlOut;crtlIn;ctrlFromFrameBuf;ctrlIn;ctrlToFrameBuf;data;dataReady;done;enable;enableREG;enable_out;findMin;framePop;frameStart;genTrigger;hwDone;hwStart;ind;indmin;lane;lane1En;lane1In;lane2En;lane2In;lane3En;lane3In;lane4En;lane4In;lane5En;lane5In;lane6En;lane6In;lane7En;lane7In;laneAddress;laneCIn;laneCapture;laneIn;laneREGRST;laneRST;laneVal;leftwidth;matchedHist;minInd;minVal;negHistCount;offsetVal;peakIndex;peakREG;peakVal;peakValueMemory;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut;posHistCount;process;regEnable;regionStart;rightminop;rightwidth;start;swDone;swStart;triggerOut;val;valGreater;valmin;width;zeroCrossingTrue

BLOCKTYPE:
Abs;BusSelector;Color Space Converter;Compare To Constant;Compare To Zero;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;Demux;DiscreteFir;EnablePort;Frame Buffer Simulation;From;From Multimedia File;Gain;Goto;HDL Counter;Histogram;Image Filter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;Logic;MultiPortSwitch;Outport;Pixel Control Bus Creator;Pixel Stream FIFO;Product;RateTransition;RelationalOperator;S-Function;Selector;SignalSpecification;StateControl;Sum;Terminator;To Video Display;VariantSource;visionhdl.BirdsEyeView;visionhdl.ROISelector;visionzynq.internal.VideoCaptureHDMI

BLOCKTYPE_FREQUENCY:
10;4;1;22;9;5;46;1;3;267;6;1;2;1;17;1;4;9;9;4;1;1;1;178;35;62;154;6;1;1;8;21;6;6;21;4;40;16;3;1;3;3;1


MODELNAME: vzLaneDetection_02_HardwareInterface
DESCRIPTION: Lane Detection Detect lanes from streaming video.
BLOCKTYPE_FREQUENCY: 2;1;1;1;5;1;17;1;11;4;5;5;5;1;1
CHECKSUM: 28C505885A39BF4161CE4BF262751565
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzLaneDetection_02_HardwareInterface.slx

ANNOTATION:
Vision Zynq Targeted Hardware Interface Model: vzLaneDetection_01_PixelStream Simulink Interface to HW User Logic Vision Zynq Device to Simulink Algorithm This model contains blocks that can be used for simulation with targeted hw user logic. Generated by HDL Workflow Advisor on 28-Jul-2020 19:48:28

BLOCK:
 Demux ; SFunction ; Terminator ;?;BirdsEyeInput;BirdsEyeLaneOV;Delay;Driver;Enable;FitPolyLeftLane;FitPolyRightLane;Im;Im ;ImOut;Index;Lane Detection Algorithm;Lane Fit And Overlay Algorithm;LaneFit;LeftLane;OverlayLaneMarkings;OverlayOutput;OverlayPolyLeftLane;OverlayPolyRightLane;P;Poly;PolyLeftLane;PolyRightLane;Rate Transition;Reference;RightLane;Signal Specification;SubSystem;Vector Concatenate;Video Capture HDMI;dataReady;laneCIn;process;swDone;swStart

BLOCKTYPE:
Concatenate;Constant;CustomCallbackButton;Delay;Demux;EnablePort;Inport;LaneDetec_ip VisionZynq Target Cosimulation;Outport;RateTransition;S-Function;SignalSpecification;Terminator;To Video Display;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzLaneDetection_03_SoftwareInterface
DESCRIPTION: Lane Detection Detect lanes from streaming video.
BLOCKTYPE_FREQUENCY: 1;2;1;1;1;5;1;17;11;4;5;5;5;1;1
CHECKSUM: A8030B26C491E84A5695A15DFB2D12D9
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzLaneDetection_03_SoftwareInterface.slx

ANNOTATION:
Vision Zynq Software Interface Model: vzLaneDetection_01_PixelStream ARM Interface to Vision Zynq Device ARM Interface to HW User Logic This model contains blocks that can be used for software generation. Generated by HDL Workflow Advisor on 28-Jul-2020 19:48:50

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;Concatenate;Constant;CustomCallbackButton;Delay;Demux;EnablePort;Inport;Outport;RateTransition;S-Function;SignalSpecification;Terminator;VideoViewer;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Embedded Coder;Embedded Coder Support Package for ARM Cortex-A Processors;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: vzLowLightEnhancement_PixelStream
BLOCKTYPE_FREQUENCY: 3;4;1;1;52;1;5;1;1;14;1;13;6;1;6;2;1;1;1;1;1
CHECKSUM: B5F513F7D33A5C636E43D37BF35CC969
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzLowLightEnhancement_PixelStream.slx

ANNOTATION:
EnhancementFactor Conversion Copyright 2019-2023 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Low Light Enhancement Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
?;Add;B;BIn;BOut;Constant;CtrlIn;CtrlOut;DarkChannel;Data Type Conversion;Delay;Enhance- ment;From Multimedia File;G;GIn;GOut;HazeFactor;Image Filter;Image Frame To Pixels ;Image Pixels To Frame;Image Source;InvOut;Inversion;IterativeFilter;LowLight Enhancement Algorithm;Matrix Concatenate;PixIn;Pixel Stream Aligner;Pixel-Stream Output;Product;R;RGB Concatenate;RGB Select;RIn;ROut;Rate Transition;Reciprocal;Reference;Select B;Select G;Select R;Selector;SubSystem;Subtract;Terminator;Vector Concatenate;Video Capture HDMI;ctrlIn;ctrlOut;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut

BLOCKTYPE:
Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;From Multimedia File;Image Filter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;MinMax;Outport;Product;RateTransition;Selector;Sum;Terminator;To Video Display;VariantSource;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzMultiPixMultiComp_PixelStream
BLOCKTYPE_FREQUENCY: 1;1;7;1;1;1;5;1;1;1;1;22;1;18;6;20;1;1;1;1;1;1
CHECKSUM: 1410FA98CFEAAB216B20CD642354ABBA
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzMultiPixMultiComp_PixelStream.slx

ANNOTATION:
Conversion Source Algorithm Display Conversion Copyright 2021 -2023 The MathWorks, Inc.  MultiPixel-MultiComponent Pixel-Stream Algorithm with Zynq-Based Hardware

BLOCK:
15x15 Blur;?;Add;B;BIn;BOut;BlendBloom;Bloom;BrightSpotFilter;Color Space Converter;Compare To Constant;Constant;CtrlIn;CtrlOut;Delay;For Each;From Multimedia File;G;GIn;GOut;Image Filter;Image Frame To Pixels ;Image Pixels To Frame;Image Source;Matrix Concatenate;MultiPixelColorSpaceConverter;MultiPixelToRGBVec;Multiport Switch;Pixel Stream Aligner;Pixel-Stream Output;R;RGB;RGB Concatenate;RGB Select;RGBVecToMultiPixel;RIn;ROut;Reference;Reshape;Selector;SubSystem;Terminator;Vector Concatenate;Video Capture HDMI;ctrlIn;ctrlOut;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelOut;refpixelIn

BLOCKTYPE:
Color Space Converter;Compare To Constant;Concatenate;Constant;CustomCallbackButton;Delay;ForEach;From Multimedia File;Image Filter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;MultiPortSwitch;Outport;Reshape;Selector;Sum;Terminator;To Video Display;VariantSource;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzPotholeDetection_PixelStream
BLOCKTYPE_FREQUENCY: 4;57;9;1;1;9;6;3;31;1;17;82;1;1;1;3;1;1;1;4;10;1;1;93;27;5;2;4;3;79;1;6;9;9;8;20;20;4;6;1;1;1;1;1;1
CHECKSUM: 48704CA0A22875601ADBB40DEC81EE29
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzPotholeDetection_PixelStream.slx

ANNOTATION:
Check for updated string wait one frame, then trigger at the start of all other frames Processor Algorithm Conversion Copyright 2017 The MathWorks, Inc. Source Pixel-Stream Algorithm Compare and Display Conversion  Pothole Detection and Text Overlay Pixel-Stream Algorithm with Zynq-Based Hardware Frame Buffer Model

BLOCK:
1-D Lookup Table;?;Add;Align;Area Threshold;AreaThresh;AreaThreshOut;B;BFromFrameBuf;BIn;BOut;BToFrameBuf;BWCtrlIn;BWIn;Bilateral Filter;Bit Concat;Bit Slice;Cartoon RGB;Centroid;CentroidKernel;Closing;Color Space Converter;Compare To Constant;Compare To Zero;Constant;CtrlIn;CtrlOut;CtrlOut ;Data Type Conversion;Delay;DetectAndHold;DetectOut;Display;Dual Port RAM;Edge Detector;EnTapDelay;Enable;ExpandData;Fiducial31x;For Each;For Each Subsystem;FrameBoundary;From Multimedia File;G;GFromFrameBuf;GIn;GOut;GToFrameBuf;Gain;GradThresh;Gradient Threshold;HDL Counter;HVCounters;Image Frame To Pixels ;Image Pixels To Frame;Image Source;In;Index Vector;KeyIn;LED;Line Buffer;LineCount;LineRGB;Logical Operator;Matrix Concatenate;MinMax;Mux;OR;Out;Overlay;Overlay32x;OverlayRGB;OverlayTransp;Pixel Control Bus Creator;Pixel Control Bus Selector;Pixel-Stream Output;PixelCount;PixelOut;Pothole Detection Algorithm;Product;R;RFromFrameBuf;RGB Concatenate;RGB Select;RGBCtrlIn;RGBIn;RGBOut;RGBin;RGBout;RIn;ROut;RToFrameBuf;Reference;Relational Operator;Select B;Select G;Select R;Selector;Show Raw;ShowRaw;ShowRawIn;State Control;StringIn;SubSystem;Subsystem;Subtract;Sum;Switch;SwitchStream;Tapped Delay;Terminator;Text String;TextString;ThreshIn;ThreshOut;ToBits;TrapezoidalMask;UpdateText;Vector Concatenate;Video Capture HDMI;Video Frame Buffer;area;areaIn;areaThresh;bottomEdge;char ROM;ctrl;ctrlFromFrameBuf;ctrlIn;ctrlOut;ctrlToFrameBuf;curLine;dataIn;dataOut;detectIn;detectOut;en;enable;enableLD;fiducial ROM;genTrigger;hCount;in;isValidIdx;leftEdge;leftIdxValid;maxReg;notvEnd;overlayAlpha;overlayRGB;pixelCtrl;pixelCtrlIn;pixelCtrlOut;pixelData;pixelIn;pixelVectIn;popFrame;posOnly;posOut;rgbIn;rgbOut;rightEdge;rightIdxValid;shiftIn;showRaw;sum;sumOut;textString;topEdge;triggerOut;vCount;wrAddr;wrData;wrEn;xCenter;xLoc;xLocIn;xLocOut;yCenter;yLoc;yLocIn;yLocOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusSelector;Closing;Color Space Converter;Compare To Constant;Compare To Zero;Concatenate;Constant;CustomCallbackButton;DataTypeConversion;Delay;Display;Dual-port RAM;Edge Detector;EnablePort;ForEach;Frame Buffer Simulation;From Multimedia File;Gain;HDL Counter;Image Pixels To Frame;Image Y Frame To Pixels;Inport;Logic;Lookup_n-D;MinMax;MultiPortSwitch;Mux;Outport;Pixel Control Bus Creator;Product;RelationalOperator;Selector;StateControl;Sum;Switch;Tapped Delay Line;Terminator;To Video Display;VariantSource;visionhdl.BilateralFilter;visionhdl.LineBuffer;visionhdl.PixelStreamAligner;visionzynq.internal.VideoCaptureHDMI


MODELNAME: vzSharpen_PixelStream
BLOCKTYPE_FREQUENCY: 1;3;3;1;1;15;1;1;1;1;1;3;1;16;6;10;1;1;1;1;1;2;2;1;2;1;1;1;1
CHECKSUM: 712226EF4310C0DE943F23853F0B9F2D
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzSharpen_PixelStream.slx

ANNOTATION:
Conversion Copyright 2016-2023 The MathWorks, Inc. Pixel-Stream Algorithm Compare and Display Conversion  Image Sharpening Pixel-Streaming Algorithmwith Zynq-Based Hardware Source

BLOCK:
 Demux ; SFunction ; Terminator ;?;Align Video;Bit Slice;Blur Image;Constant;CtrlIn;CtrlOut;DIPSwitch;DS0 Sharpen;Data Type Conversion Inherited;Delay;Display;FIFO;From;From Multimedia File;Goto;HDL Counter;Image Filter;Image Sharpening Algorithm;Image Source;ImageIn;ImageOut;In;LED;Logical Operator;Out;Pixel Control Bus Selector;Pixel-Stream Output;Pop;Push;Rate Transition;Reference;Signal Specification;Simple Dual Port RAM;Source Output;SubSystem;Switch;Terminator;Unit Delay Enabled Resettable;Video Capture HDMI;Y Frame To Pixels;Y Pixels To Frame;Y Resize;YIn;YOut;YOutOrig;YOutSharp;ctrlIn;ctrlInDelayed;ctrlOut;dsSharpen;original;pixel;pixelInDelayed;rst_FIFO;sharpened;switch

BLOCKTYPE:
Bit Slice;BusSelector;Constant;Conversion Inherited;CustomCallbackButton;Delay;Demux;Display;From;From Multimedia File;Goto;HDL Counter;Image Filter;Inport;Logic;Outport;RateTransition;S-Function;SignalSpecification;Simple Dual-port RAM;Switch;Terminator;Unit Delay Enabled Resettable;VariantSource;VideoViewer;Y Frame To Pixels;Y Pixels To Frame;Y Resize;visionzynq.internal.VideoCaptureHDMI

PRODUCT:
Computer Vision Toolbox;Image Processing Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: vzVisionAlgorithmWorkflow
BLOCK: ?;SubSystem;Subsystem
BLOCKTYPE: CustomCallbackButton
BLOCKTYPE_FREQUENCY: 1
CHECKSUM: 3C6D0239D4F0571B66D78A11EDC979B5
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/zynq_vision/visionzynqexamples/visionzynqexamples/vzVisionAlgorithmWorkflow.slx

ANNOTATION:
 This example shows how to use the Xilinx Zynq-Based Vision Support Package with Simulink for developing vision algorithms. It uses several models to show the gradual progression from a behavioral algorithm to a fully deployed target system running that algorithm. Open the full write-up by double clicking the Info block. Open individual models in the workflow by clicking the appropriate blocks below. Developing Vision Algorithms for Zynq-Based Hardware Copyright 2016 The MathWorks, Inc.


MODELNAME: soc_hdmi_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hdmi/soc_hdmi_top.slx
BLOCKTYPE: HDMI Rx;HDMI Tx;Inport;ModelReference;Outport
BLOCKTYPE_FREQUENCY: 1;1;2;2;2
CHECKSUM: 7D26D3E183C93038730900BA159BB9A2
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_hdmi_fpga_frame.slx___Model_Block___soc_hdmi_fpga_pixel.slx___Model_Block___
ANNOTATION:
 To add your FPGA Algorithm, open the referenced models and replace contents of subsystem marked in green FPGA HDMI Input  Double-click FPGA block to select Sample/Frame based simulation mode Follow instructions below to add your FPGA algorithm HDMI Output  Copyright 2019 The MathWorks, Inc.  ?   Click here to open FPGA model - Pixel based processing  Click here to open FPGA model - Frame based processing

BLOCK:
FPGA;Frame based processing;HDMI Rx;HDMI Tx;Pixel based processing;Reference;SubSystem;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut


MODELNAME: soc_hdmi_fpga_frame
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hdmi/referencedmodels/soc_hdmi_fpga_frame.slx
ANNOTATION: Add your FPGA Algorithm inside FPGA Algorithm subsystem Copyright 2019 The MathWorks, Inc.
BLOCKTYPE: Delay;Inport;Outport
BLOCKTYPE_FREQUENCY: 2;4;4
CHECKSUM: 8EE56F68A93CD0C0CD2161F4001A47F1
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
CtrlIn;CtrlOut;Delay;FPGA Algorithm;FrameOut;SubSystem;frameIn;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut


MODELNAME: soc_hdmi_fpga_pixel
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hdmi/referencedmodels/soc_hdmi_fpga_pixel.slx
BLOCKTYPE: Constant;Delay;Inport;Outport;Terminator;Video Stream Connector
BLOCKTYPE_FREQUENCY: 1;4;8;8;1;2
CHECKSUM: 7D9D8A8E1D533E7024A21E2EF35D9D82
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 Add your FPGA Algorithm in above subsystem  NOTE: You must use Video Stream Connector blocks between subsystems to implement as separate IP cores with Video Stream interface during code generation.   Add your FPGA Algorithm inside FPGA Algorithm Wrapper subsystem  Terminate the wrCtrlOut as it is not handled by HDMI input  Create an always HIGH signal for ready as it is not generated by HDMI Output. Copyright 2019 The MathWorks, Inc.

BLOCK:
AlwaysReady;CtrlIn;CtrlOut;Delay;FPGA Algorithm;FPGA Algorithm Wrapper;Reference;SubSystem;Terminator;Video Stream Connector;Video Stream FIFO;YOut;ctrlIn;ctrlOut;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;pixelIn;pixelOut;rdyFromDown;rdyToUp


MODELNAME: soc_hdmi_framebuffer_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hdmi_framebuffer/soc_hdmi_framebuffer_top.slx
BLOCKTYPE: AXI4 Video Frame Buffer;HDMI Rx;HDMI Tx;Inport;ModelReference;Outport
BLOCKTYPE_FREQUENCY: 1;1;1;5;2;5
CHECKSUM: 224F30FCE17600BCEFBDE66779554278
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
ANNOTATION:
 To add your FPGA Algorithm, open the referenced models and replace contents of subsystem marked in green HDMI Output HDMI Input  Click here to open FPGA model - Pixel based processing Memory FPGA   ?   Double-Click FPGA block to select Sample/Frame based simulation mode Follow instructions below to add your FPGA algorithm   Copyright 2019-2020 The MathWorks, Inc.  Click here to open FPGA model - Frame based processing

BLOCK:
 frBufRdCtrlOut; frBufWrCtrlOut; frBufWrData;FPGA;Frame Buffer;Frame based processing;HDMI Rx;HDMI Tx;Pixel based processing;Reference;SubSystem;frBufRdCtrlIn ;frBufRdData ;frBufWrCtrlIn ;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut

EXTERNALFILE_REFERENCE:
soc_hdmi_framebuffer_fpga_frame.slx___Model_Block___soc_hdmi_framebuffer_fpga_pixel.slx___Model_Block___


MODELNAME: soc_hdmi_framebuffer_fpga_frame
ANNOTATION: Add your FPGA Algorithm inside the FPGA Algorithm subsystem Copyright 2019 The MathWorks, Inc.
BLOCKTYPE: Bus Creator;Bus Selector;Constant;Inport;Outport;Terminator
BLOCKTYPE_FREQUENCY: 1;1;2;10;11;1
CHECKSUM: 85D12B385AF95103C19BFE41BA340C2B
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
PATH:
toolbox/soc/templates/prjtemplates/templatessrc/soc_hdmi_framebuffer/referencedmodels/soc_hdmi_framebuffer_fpga_frame.slx

BLOCK:
Bus Creator;Bus Selector;Constant;FPGA Algorithm;Reference;SubSystem;Terminator;ctrlFromFrameBuf;ctrlIn;ctrlOut;ctrlToFrameBuf;dataFromFrameBuf;dataIn;dataOut;dataToFrameBuf;frBufRdCtrlIn;frBufRdCtrlOut;frBufRdData;frBufWrCtrlIn;frBufWrCtrlOut;frBufWrData;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;rdyFromFrameBuf;rdyToFrameBuf;syncToFrameBuf


MODELNAME: soc_hdmi_framebuffer_fpga_pixel
BLOCKTYPE_FREQUENCY: 1;1;1;1;4;15;16;1;2
CHECKSUM: F4488FE21921768FB20EF5587CB6128D
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
PATH:
toolbox/soc/templates/prjtemplates/templatessrc/soc_hdmi_framebuffer/referencedmodels/soc_hdmi_framebuffer_fpga_pixel.slx

ANNOTATION:
 Add your FPGA Algorithm in above subsystem  Create an always HIGH signal for ready as it is not generated by HDMI Output.  Terminate the wrCtrlOut (ready signal) as it is not handled by HDMI input  Add your FPGA Algorithm inside the FPGA Algorithm Wrapper subsystem Copyright 2019 The MathWorks, Inc.  NOTE: You must use Video Stream Connector blocks between subsystems to implement as separate IP cores with Video Stream interface during code generation.

BLOCK:
AlwaysReady;Bus Creator;Bus Selector;Delay;FPGA Algorithm;FPGA Algorithm Wrapper;Pixel Control Bus Selector;Reference;SubSystem;Terminator;Video Stream Connector;Video Stream FIFO;ctrlFromFrameBuf;ctrlIn;ctrlOut;ctrlToFrameBuf;ctrllIn;frBufRdCtrlIn;frBufRdCtrlOut;frBufRdData;frBufWrCtrlIn;frBufWrCtrlOut;frBufWrData;frameBufferReadSync;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;pixelFromFrameBuf;pixelIn;pixelOut;pixelToFrameBuf;rdyFromFrameBuf;rdyFromSink;rdyToFrameBuf;rdyToSrc

BLOCKTYPE:
Bus Creator;Bus Selector;BusSelector;Constant;Delay;Inport;Outport;Terminator;Video Stream Connector


MODELNAME: soc_hwsw_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hwsw/soc_hwsw_top.slx
BLOCKTYPE_FREQUENCY: 1;4;3;5;1;1;1;1
CHECKSUM: 9ABF05C789A503E01E27657FA77BE9FD
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 To add your FPGA Algorithm and Test Source, open the referenced models and replace contents of subsystem marked in green  A DSP System Toolbox license is required for Frame based processing  To add your Processor Algorithm and Test Source, open the referenced model and replace contents of subsystem marked in blue  Click here to open FPGA model - Sample based processing Processor Memory FPGA Testbench Output  2. Follow instructions below to add your FPGA algorithm  ?   1. Double-click FPGA block to select Sample/Frame based simulation mode   Click here to open FPGA model - Frame based processing  3. Follow instructions below to add your Processor algorithm   Click here to open Processor model Copyright 2019 The MathWorks, Inc.

BLOCK:
 dataOut; rdCtrlOut;AXI4-Stream to Software;Done;FPGA;Frame based processing;Processor;Processor - Frame based processing;RT;Reference;Register Channel;Sample based processing;SubSystem;Task Manager;Vector Scope;configReg;dataIn;dataOut;dataTask;fpgaParam;rdCtrlIn 

BLOCKTYPE:
AXI4-Stream to Software;Inport;ModelReference;Outport;RateTransition;Register Channel;Scope;Task Manager

EXTERNALFILE_REFERENCE:
soc_hwsw_fpga_frame.slx___Model_Block___soc_hwsw_fpga_sample.slx___Model_Block___soc_hwsw_proc.slx___Model_Block___


MODELNAME: soc_hwsw_fpga_frame
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hwsw/referencedmodels/soc_hwsw_fpga_frame.slx
BLOCKTYPE_FREQUENCY: 1;1;2;1;1;1;9;11;1;1;1
CHECKSUM: C3E2841A2167BB545DACF252C1DF78FD
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
NOTE: Data output must be 32 bits   Add your FPGA Algorithm in above subsystem  Replace Test data (counter) source with your test source  Add your Test Source inside this subsystem  Add your Test Source inside Test Source Wrapper subsystem  Add your FPGA Algorithm inside FPGA Algorithm Wrapper subsystem  NOTES: To add additional registers to your algorithm IPs, add new Inports blocks to this model. Since this is a reference model, you must specify explicitly the signal attributes on the new Inport blocks such as Data type, Dimension and Sample Time. See Signal Attributes tab properties on configReg block as an example. You must use Stream Connector block to separate the IPs Copyright 2019 The MathWorks, Inc.

BLOCK:
All data is valid;Cast;Enable;FPGA Algorithm;FPGA Algorithm Wrapper;Multiply;No-Op Tlast;Reference;SoC Bus Creator;SoC Bus Selector;Stream Connector;SubSystem;TLast;Terminator;Test Source;Test Source Wrapper;Test data (counter);Tlast;TlastOut;configReg;dataIn;dataOut;out;rdCtrlIn;rdCtrlOut;ready;testData;valid;validOut

BLOCKTYPE:
Bus Creator;Bus Selector;Constant;Counter;DataTypeConversion;EnablePort;Inport;Outport;Product;Stream Connector;Terminator


MODELNAME: soc_hwsw_fpga_sample
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hwsw/referencedmodels/soc_hwsw_fpga_sample.slx
BLOCKTYPE_FREQUENCY: 1;1;3;1;1;1;9;12;1;1;1;1
CHECKSUM: BA9B0656AEEADF292473B9F6111BD99F
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 Add your FPGA algorithm in above subsystem  NOTE: Data output must be 32 bits   Replace Test data (counter) source with your test source  Add your Test Source in the above subsystem  Add your FPGA Algorithm inside the FPGA Algorithm Wrapper subsystem  Add your Test Source inside Test Source Wrapper subsystem  NOTES: To add additional registers to your algorithm IPs, add new Inports blocks to this model. Since this is a reference model, you must specify explicitly the signal attributes on the new Inport blocks such as Data type, Dimension and Sample Time. See Signal Attributes tab properties on configReg block as an example. You must use Stream Connector block to separate the IPs Copyright 2019 The MathWorks, Inc.

BLOCK:
Add;All data is valid;Cast;Constant;Delay;Enable;FPGA Algorithm;FPGA Algorithm Wrapper;Multiply;No-Op Tlast;Reference;SoC Bus Creator;SoC Bus Selector;Stream Connector;SubSystem;TLast;TLastOut ;Terminator;Test Source;Test Source Wrapper;Test data (Counter);Tlast;configReg;count;dataIn;dataOut;out;rdCtrlIn;rdCtrlOut;ready;testData;valid;validOut

BLOCKTYPE:
Bus Creator;Bus Selector;Constant;DataTypeConversion;Delay;EnablePort;Inport;Outport;Product;Stream Connector;Sum;Terminator


MODELNAME: soc_hwsw_proc
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_hwsw/referencedmodels/soc_hwsw_proc.slx
BLOCKTYPE_FREQUENCY: 1;1;1;5;8;1;1;1;1
CHECKSUM: 930F3B7A04BA5246CF98048DDE6BDAF0
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
NOTE: Data input is always 32 bits.  Add your Processor Algorithm in above subsystem  Add your Processor Algorithm inside Processor Algorithm Wrapper subsystem Copyright 2019 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Data Type Conversion;Done;In;MultiplicationFactor;Out;Processor Algorithm;Processor Algorithm Wrapper;Reference;Register Channel Write;Register Write;Stream Read;SubSystem;Terminator;Trigger;dataIn;dataOut;dataTask;fpgaParam

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;DataTypeConversion;Inport;Outport;Register Write;Stream Read;Terminator;TriggerPort


MODELNAME: soc_multiproc_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_multiproc/soc_multiproc_top.slx
BLOCK: CPU1 Executable;CPU2 Executable;Interprocess Data Channel ;Reference;Task Manager
BLOCKTYPE: Interprocess Data Channel;ModelReference;Task Manager
BLOCKTYPE_FREQUENCY: 2;2;2
CHECKSUM: 9DD96DA5A46B31E6FA3CF8A1B0FEE793
PRODUCT: C2000 Microcontroller Blockset;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_multiproc_ref1.slx___Model_Block___soc_multiproc_ref2.slx___Model_Block___
ANNOTATION:
CPU1 IPC Channel CPU2 Copyright 2021 The MathWorks, Inc.  Click here to open CPU1 model  1. Follow instructions below to add your algorithm for CPU1   ?   2. Follow instructions below to add your algorithm for CPU2   Click here to open CPU2 model


MODELNAME: soc_multiproc_ref1
ANNOTATION: Add your Processor Algorithm in above subsystem Copyright 2021 The MathWorks, Inc.
BLOCKTYPE: Constant;Inport;Interprocess Data Read;Interprocess Data Write;Outport;Sum
BLOCKTYPE_FREQUENCY: 1;2;1;1;2;1
CHECKSUM: 518A4AD3B6A10F702D9FABDF2F8D26BB
PRODUCT: C2000 Microcontroller Blockset;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
PATH:
toolbox/soc/templates/prjtemplates/templatessrc/soc_multiproc/referencedmodels/soc_multiproc_ref1.slx

BLOCK:
Add;Constant;IPC Ch1 Write;IPC Ch2 Read;IPCCh;Processor Algorithm;Reference;SubSystem;dataIn;dataOut


MODELNAME: soc_multiproc_ref2
BLOCKTYPE_FREQUENCY: 1;4;1;1;3;1
CHECKSUM: 7AEB89B6C06C72A9955B5BFF0091926F
PRODUCT: C2000 Microcontroller Blockset;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
PATH:
toolbox/soc/templates/prjtemplates/templatessrc/soc_multiproc/referencedmodels/soc_multiproc_ref2.slx

ANNOTATION:
 Add your Processor Algorithm in above subsystem Copyright 2021 The MathWorks, Inc. Copyright 2021 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;IPC Ch1 Read;IPC Ch2 Write;IPCCh;Processor Algorithm;Reference;SubSystem;Task;Trigger;dataIn;dataOut;task1FcnCall

BLOCKTYPE:
AsynchronousTaskSpecification;Inport;Interprocess Data Read;Interprocess Data Write;Outport;TriggerPort


MODELNAME: soc_rfsoc_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_rfsoc/soc_rfsoc_top.slx
BLOCKTYPE_FREQUENCY: 1;1;3;2;3;1;1;1;1
CHECKSUM: 0B4B3639DBD438DBCA01A32A90079F1C
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_rfsoc_fpga.slx___Model_Block___soc_rfsoc_proc.slx___Model_Block___
ANNOTATION:
ADC is of 12 bits. To simulate that behavior, shift the sample to right by 2 bits.  To add your processor algorithm, open the referenced model soc_rfsoc_proc and replace the contents of the subsystem marked in blue.  Click here to open FPGA model RF I/O Copyright 2020 The MathWorks, Inc. Memory Processor FPGA Testbench Sink   ?   1. Follow instructions below to add your FPGA algorithm  2. Follow instructions below to add your Processor algorithm  Click here to open Processor model

BLOCK:
AXI4-Stream to Software;Channel;FPGA;Processor;Processor - Frame based processing;RF Data Converter;RT;Reference;Rx;Simple channel;SubSystem;Task Manager;Time Scope;Tx;data;dataOut;dataTask;done

BLOCKTYPE:
AXI4-Stream to Software;Delay;Inport;ModelReference;Outport;RF Data Converter;RateTransition;Scope;Task Manager


MODELNAME: soc_rfsoc_fpga
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_rfsoc/referencedmodels/soc_rfsoc_fpga.slx
BLOCKTYPE_FREQUENCY: 7;1;1;2;2;2;2;9;1;4;1;52;2;3;50;2;3;1
CHECKSUM: 8E0CE1BADBAAC0D8C2DEA2CBF7C14982
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Since sample1 and sample2 are consecutive samples, consider only one of them for writing to the processor during down sampling.   FPGA is operating at a very high clock rate. Since the processor cannot handle such high rates, down sampling the data before writing to the processor.  Add your receiver algorithm in above subsystem When SrcSel is 0, data from ADC is sent to Rx Algorithm. When SrcSel is 1, data from Tx Algorithm is sent to Rx Algorithm. Transmit a test 500kHz complex sinusoid Generating first sample for every 32-bit packed data Generating second sample for every 32-bit packed data In top model, Samples per clock cycle parameter in RF Data Converter block is 2, that means the DUT must pack two 16 bit samples into 32 bit data before sending to RF Data Converter.  Add your transmitter algorithm in above subsystem  Add your receiver algorithm inside the Receiver Algorithm subsystem.  Add your Test Source inside Test Source subsystem  Add your test source and transmitter algorithm inside Test Source and Transmitter Algorithm subsystems respectively.  IP Core Register Read block gets initialized by the block soc_rfsoc_proc/Initialize Function/Register Write.  Add your FPGA Algorithm inside FPGA Tx-Rx Alg Wrapper subsystem  NOTE: To add registers to your algorithm IPs, add new IP Core Register Read blocks inside the DUT. Since this is a reference model, you must specify explicitly the signal attributes such as Data type, Port dimensions and Sample time for new Inport blocks. See Signal Attributes tab properties on adc1IData block as a reference. Copyright 2020 The MathWorks, Inc.  ready signal is not modeled, so it is terminated. In this case, HDL Coder detects that there is no ready signal and models it during code generation.  tlast signal is not modeled. Instead, used a constant to drive the tlast signal. In this case, HDL Coder detects that there is no tlast signal and models it during code generation.

BLOCK:
 Second I sample;500KHz Wave;AND;Algorithm;Bit Concat;Bus Creator;Bus Selector;Compare To Constant;Complex to Real-Imag;Constant;Counter Limited;DataI_In;DataI_Out;DataOut;DataQ_In;DataQ_Out;DataValidOut;Delay;Down Sampler;Enable;Enabled Delay;FPGA Tx-Rx Alg Wrapper;First I sample;First Q sample;IData;IData_FPGALoopback;IData_RF;IP Core Register Read;IQValid;IQValid_FPGALoopback;ISample;ISample1In_FPGALoopback;ISample1In_RF;ISample1Out_FPGALoopback;ISample1Out_RF;ISample2In_FPGALoopback;ISample2In_RF;ISample2Out_FPGALoopback;ISample2Out_RF;I_in;I_out;Logical Operator;Multiport Switch;Pack samples;QData;QData_FPGALoopback;QData_RF;QSample;QSample1In_FPGALoopback;QSample1In_RF;QSample1Out_FPGALoopback;QSample1Out_RF;QSample2In_FPGALoopback;QSample2In_RF;QSample2Out_FPGALoopback;QSample2Out_RF;Q_in;Q_out;Receiver Algorithm;Reference;Rx Algorithm;Second Q sample;Source Select;SrcSel;SubSystem;Subsystem;Terminator;Test Source;Transmitter Algorithm;Trigger;Tx Algorithm;Unpack;Valid;Valid_Out;Valid_out;adc1IData;adc1QData;adc1Valid;chCtrlIn;chCtrlOut;chData;count;dac1IData;dac1QData;dac1Valid;dataOut;validOut;y

BLOCKTYPE:
Bit Concat;Bus Creator;Bus Selector;Compare To Constant;ComplexToRealImag;Constant;Counter Limited;Delay;EnablePort;Extract Bits;IP Core Register Read;Inport;Logic;MultiPortSwitch;Outport;Sine Wave;Terminator;TriggerPort


MODELNAME: soc_rfsoc_proc
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_rfsoc/referencedmodels/soc_rfsoc_proc.slx
BLOCKTYPE_FREQUENCY: 1;2;1;1;1;4;5;6;1;1;6;1;1;1
CHECKSUM: 5F07918870E2EC9C2A61431893E211B9
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 Add a Register Write block for each IP Core Register Read block in the FPGA model.  When SrcSel is 0, data from the ADC is sent to the Rx algorithm in FPGA. When SrcSel is 1, data from the Tx Algorithm is sent to the Rx algorithm in FPGA.  Rearrange the frame data to get consecutive samples as a frame. Re-arrange  Add your Processor Algorithm in above subsystem  Add your processor algorithm inside Processor Algorithm subsystem.  Add your processor algorithm inside the Processor Algorithm Wrapper subsystem. Copyright 2020 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Data Type Conversion;Event Listener;Extract Bits;Initialize Function;Processor Algorithm;Processor Algorithm Wrapper;Real-Imag to Complex;Reference;Register Write;Reshape;SrcSel;Stream Read;SubSystem;Terminator;Trigger;Vector Concatenate;data;dataIn;dataOut;dataTask;done

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;EventListener;Extract Bits;Inport;Outport;RealImagToComplex;Register Write;Reshape;Stream Read;Terminator;TriggerPort


MODELNAME: soc_sdr_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_sdr/soc_sdr_top.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;6;1;3;9;1;1;1;1
CHECKSUM: 5A6CC10E5192EBFCFD7DB2206DEE0F26
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
ANNOTATION:
 To add your FPGA Algorithm and Test source, open the referenced models and replace contents of subsystem marked in green  To add your Processor Algorithm, open the referenced model and replace contents of subsystem marked in blue  Click here to open FPGA model - Sample based processing External I/O Copyright 2019 The MathWorks, Inc. Memory Processor FPGA Testbench Sink  1. Double-click FPGA block to select Sample/Frame based simulation mode  ?   2. Follow instructions below to add your FPGA algorithm  Click here to open FPGA model - Frame based processing  3. Follow instructions below to add your Processor algorithm  Click here to open Processor model

BLOCK:
 LED; RFTxData; RFTxValid; chCtrlOut; chData;AD9361Rx;AD9361Tx;AXI4-Stream to Software;Channel;FPGA;Frame based processing;LED;Processor;Processor - Frame based processing;RFRxData ;RT;Reference;Register Channel;Rx;Sample based processing;Simple channel;SrcSel ;SrcSelect;SubSystem;Task Manager;Tx;Vector Scope;chCtrlIn ;data;dataOut;dataTask;done

BLOCKTYPE:
AD9361 Rx Playback;AD9361 Tx Playback;AXI4-Stream to Software;Delay;Inport;LED;ModelReference;Outport;RateTransition;Register Channel;Scope;Task Manager

EXTERNALFILE_REFERENCE:
soc_sdr_fpga_frame.slx___Model_Block___soc_sdr_fpga_sample.slx___Model_Block___soc_sdr_proc___Model_Block___


MODELNAME: soc_sdr_fpga_frame
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_sdr/referencedmodels/soc_sdr_fpga_frame.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;3;3;4;2;22;1;1;31;4;1;1;4
CHECKSUM: 30F37A722E3BE37FA2FEBEAC22B6349B
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
ADC data has 12 bits. Apply gain to take full advantage of 16 bits  Add your receiver algorithm in above subsystem Transmit a test 10kHz sinusoid  Models the AD9361 transmit interface core, which takes the top 12 bits of the 16-bit transmit data value  Add your transmitter algorithm in above subsystem Add your Receiver Algorithm inside the Receiver Algorithm subsystem.  Add your Test Source and Transmitter Algorithm inside Test Source and Transmitter Algorithm subsystems respectively LED will light when data is dropped.  Add your FPGA Algorithm inside the FPGA Tx-Rx Alg Wrapper subsystem  NOTE: To add additional registers to your algorithm IPs, add new Inports blocks to this model. Since this is a reference model, you must specify explicitly the signal attributes on the new Inport blocks such as Data type, Dimension and Sample Time. See Signal Attributes tab properties on SrcSel block as an example. Copyright 2019 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;10KHz Wave;AD9361 Tx Interface;Algorithm;Assertion;Bus Creator;Bus Selector;Ch1Q_Ch1I;Ch1Q_Ch1I_FPGA_Loopback;Ch1Q_Ch1I_FPGA_LoopbackIn;Ch1Q_Ch1I_FPGA_LoopbackOut;Ch1Q_Ch1I_RF;Ch1Q_Ch1I_RFIn;Ch1Q_Ch1I_RFOut;Complex to Real-Imag;Constant;DataOut;DataValidOut;Delay;Enabled Delay;FPGA Tx-Rx Alg Wrapper;Gain;I;I_In;I_in;I_out;LED;Logical Operator;Multiport Switch;Out;Q;Q_In;Q_in;Q_out;RFRxData;RFTxData;RFTxValid;Receiver Algorithm;Reference;RfDataIn;Rfdata;Rx Algorithm;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_Out;Scope;SliceIQ;SrcSel;SubSystem;Test Source;Transmitter Algorithm;Tx Algorithm;ValidLogic;Valid_out;chCtrlIn;chCtrlOut;chData;concatIQ;dataDropped;dataOut;readyFromDown;u;validOut;y

BLOCKTYPE:
Assertion;Bus Creator;Bus Selector;ComplexToRealImag;Constant;Delay;Demux;Gain;Inport;Logic;MultiPortSwitch;Outport;S-Function;Scope;Sine Wave;Terminator


MODELNAME: soc_sdr_fpga_sample
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_sdr/referencedmodels/soc_sdr_fpga_sample.slx
BLOCKTYPE_FREQUENCY: 1;2;2;1;1;1;3;2;3;1;2;17;1;1;27;1;1;1
CHECKSUM: DE3332C56216F11A80DFC0C8E78CADFA
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 ADC data has 12 bits. Apply gain to take full advantage of 16 bits  Add your receiver algorithm in above subsystem Transmit a test 10kHz sinusoid Models the AD9361 transmit interface core, which takes the top 12 bits of the 16-bit transmit data value  Add your transmitter algorithm in above subsystem  Add your Receiver Algorithm inside the Receiver Algorithm subsystem.  Add your Test Source inside Test Source subsystem  Add your Test Source and Transmitter Algorithm inside Test Source and Transmitter Algorithm subsystems respectively  NOTE: To add additional registers to your algorithm IPs, add new Inports blocks to this model. Since this is a reference model, you must specify explicitly the signal attributes on the new Inport blocks such as Data type, Dimension and Sample Time. See Signal Attributes tab properties on SrcSel block as an example.  Add your FPGA Algorithm inside FPGA Tx-Rx Alg Wrapper subsystem Copyright 2019 The MathWorks, Inc.  LED will light when data is dropped.

BLOCK:
 Demux ; SFunction ; Terminator ;10KHz Wave;AD9361 Tx Interface;Algorithm;Assertion;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Ch1Q_Ch1I;Ch1Q_Ch1I_FPGA_Loopback;Ch1Q_Ch1I_FPGA_LoopbackIn;Ch1Q_Ch1I_FPGA_LoopbackOut;Ch1Q_Ch1I_RF;Ch1Q_Ch1I_RFIn;Ch1Q_Ch1I_RFOut;Complex to Real-Imag;Constant;Data Type Conversion;DataOut;DataValidOut;Delay;Enabled Delay;FPGA Tx-Rx Alg Wrapper;Gain;I_In;I_in;I_out;LED;Logical Operator;Multiport Switch;Out;Q_In;Q_in;Q_out;RFRxData;RFTxData;RFTxValid;Receiver Algorithm;Reference;RfDataIn;Rfdata;Rx Algorithm;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_Out;SrcSel;SubSystem;Test Source;Transmitter Algorithm;Tx Algorithm;ValidLogic;Valid_out;chCtrlIn;chCtrlOut;chData;dataDropped;dataOut;readyFromDown;u;validOut;y

BLOCKTYPE:
Assertion;Bit Concat;Bit Slice;Bus Creator;Bus Selector;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Gain;Inport;Logic;MultiPortSwitch;Outport;S-Function;Sine Wave;Terminator


MODELNAME: soc_sdr_proc
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_sdr/referencedmodels/soc_sdr_proc.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;6;10;1;1;1;1;2;1;1;1
CHECKSUM: E93BE12FAFF37AC047A5E1C689A62AD3
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
ANNOTATION:
Select RF data (0) or FPGA loopback data (1)  Add your Processor Algorithm in above subsystem  Add your Processor Algorithm inside Processor Algorithm subsystem  Add your Processor Algorithm inside Processor Algorithm Wrapper subsystem Copyright 2019 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Asynchronous Task Specification;Constant;Event Listener;I;Initialize Function;Processor Algorithm;Processor Algorithm Wrapper;Q;Real-Imag to Complex;Reference;Register Write;SliceIQ;SourceSelect;Stream Read;SubSystem;Terminator;Trigger;Zynq and FMCOMMS2/3/4 Receiver;Zynq and FMCOMMS2/3/4 Transmitter;data;dataIn;dataOut;dataTask;done;u

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;Demux;EventListener;Inport;Outport;RealImagToComplex;Register Write;S-Function;Stream Read;Terminator;TriggerPort;comm.internal.SDRRxZC706FMC234RFSL;comm.internal.SDRTxZC706FMC234RFSL


MODELNAME: soc_swhw_top
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_swhw/soc_swhw_top.slx
BLOCKTYPE: Inport;LED;LampBlock;ModelReference;Outport;Register Channel;Software to AXI4-Stream;Task Manager
BLOCKTYPE_FREQUENCY: 2;1;4;2;2;1;1;1
CHECKSUM: EFC14937C5B738D1BB6DDE730B9ECE45
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_swhw_fpga.slx___Model_Block___soc_swhw_proc.slx___Model_Block___
ANNOTATION:
 To add your processor algorithm and test source, open the referenced model and replace contents of subsystem marked in blue. External I/O  Click here to open FPGA model Processor Memory FPGA  1. Follow instructions below to add your FPGA algorithm  ?   2. Follow instructions below to add your Processor algorithm   Click here to open Processor model Copyright 2020 The MathWorks, Inc.

BLOCK:
FPGA;LED;Lamp;Processor;Processor - Frame based processing;Reference;Register Channel;Software to AXI4-Stream;SubSystem;Task Manager;dataOut;dataTask;done;streamEnable


MODELNAME: soc_swhw_fpga
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_swhw/referencedmodels/soc_swhw_fpga.slx
BLOCKTYPE: Bus Creator;Bus Selector;DataTypeConversion;EnablePort;Extract Bits;Inport;Outport;Terminator
BLOCKTYPE_FREQUENCY: 1;1;4;1;4;10;19;1
CHECKSUM: B8931363E74ACFFAE95C14D63A0102AD
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
The algorithm in the above subsystem uses four bits of the input data from the processor to drive the LEDs. Replace the above subsystem with your algorithm.  Add your FPGA algorithm in above subsystem  Add your FPGA algorithm inside the FPGA Algorithm Wrapper subsystem Copyright 2020 The MathWorks, Inc.  NOTE: To add registers to your algorithm IPs, add new Inport blocks to this model. Since this is a reference model, you must specify explicitly the signal attributes such as Data type, Port dimensions, and Sample time for the new Inport blocks. See Signal Attributes tab properties on dataIn block as a reference.

BLOCK:
Algorithm;Data Type Conversion;Enable;Extract Bits;FPGA Algorithm;FPGA Algorithm Wrapper;LED;Reference;SoC Bus Creator;SoC Bus Selector;SubSystem;Terminator;dataIn;rdCtrlIn;rdCtrlOut;ready;streamEnable;valid;validIn


MODELNAME: soc_swhw_proc
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_swhw/referencedmodels/soc_swhw_proc.slx
BLOCKTYPE_FREQUENCY: 1;3;1;2;1;4;1;9;1;1;1;1;1;2
CHECKSUM: 52567F436845DFAC2BB99CF2F54BB237
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
To ensure that memory channel is primed before continuous streaming is begun, streamEnable signal is asserted high after available buffers in the memory channel are completely filled.  Add your processor algorithm in above subsystem  Add your test source in above subsystem  Add your processor algorithm inside Processor Algorithm Wrapper subsystem Copyright 2020 The MathWorks, Inc.

BLOCK:
Add;Asynchronous Task Specification;Constant;CountToNumBuffers;Counter Limited;Delay;Enable;Equal;NOT;Out;Processor Algorithm;Processor Algorithm Wrapper;Reference;Register Write;SendCmd;Stream Enable for DUT;Stream Write;SubSystem;Terminator;Test Source;Trigger;data;dataIn;dataOut;dataTask;done;streamEnable

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;Counter Limited;Delay;EnablePort;Inport;Logic;Outport;Register Write;RelationalOperator;Stream Write;Sum;Terminator;TriggerPort


MODELNAME: soc_sw_architecture
PATH: toolbox/soc/templates/prjtemplates/templatessrc/soc_syscomposer/soc_sw_architecture.slx
BLOCK: Bus Element In;Bus Element Out;SubSystem;aperiodicTask;periodicTask
BLOCKTYPE: Inport;Outport
BLOCKTYPE_FREQUENCY: 2;2
CHECKSUM: 1B873DB0658DF408922B7CC27BB434F9
PRODUCT: Simulink;SoC Blockset;System Composer
PRODUCT_BASECODE: HW
ANNOTATION:
 Follow documentation to linkyour model for periodicTask1  Follow documentation to linkyour model for periodicTask2  Follow documentation to linkyour model for aperiodicTask1  ?   Follow documentation to linkyour model for aperiodicTask2  Create SoC Blockset model 


MODELNAME: ASLoop
PATH: toolbox/stateflow/tools/AtomicSubchartMappingTool/mapmanager/mapmanager/ASLoop.slx
ANNOTATION: Copyright 2018 The MathWorks, Inc.
BLOCKTYPE: DataStoreMemory;Demux;Inport;Merge;Outport;S-Function;Terminator;TriggerPort
BLOCKTYPE_FREQUENCY: 2;4;11;7;14;4;3;3
CHECKSUM: 996D53178CE3A00E45DE9B6ADAED9A14
PRODUCT: MATLAB;Simulink;Stateflow
PRODUCT_BASECODE: SL;SF
BLOCK:
 ; Demux ; Merge ; SFunction ; Terminator ;Chart;SubSystem;a;aa;abdcefg;b;bb;d;e;f;g;h;i;inevt;j;l;m;mainevt;n;r;s;u;v;x;y


MODELNAME: bus
PATH: toolbox/stateflow/tools/AtomicSubchartMappingTool/mapmanager/mapmanager/bus.slx
ANNOTATION: Copyright 2018 The MathWorks, Inc.
BLOCKTYPE: BusCreator;BusSelector;Constant;Demux;Display;Inport;Merge;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 3;2;5;3;5;5;2;7;3;3
CHECKSUM: E768A7DE2B672FB4B7253D20AE98056B
PRODUCT: MATLAB;Simulink;Stateflow
PRODUCT_BASECODE: SL;SF
BLOCK:
 Demux ; Merge ; SFunction ; Terminator ;Bus Creator;Bus Selector;Chart;Constant;Display;Out;SubSystem;a;aa;b;in;out;s


MODELNAME: iobuilder
PATH: toolbox/target/shared/ioserver/template/iobuilder/iobuilder.slx
ANNOTATION: Switch case logic Switch case logic
BLOCKTYPE_FREQUENCY: 6;6;24;7;2;2;21;11;1;6;24;6;2;10;1;5
CHECKSUM: 6EE9E95FA8E700F38E704C5EC256262B
PRODUCT: Embedded Coder;Image Processing Toolbox;MATLAB;Simulink
PRODUCT_BASECODE: ML
BLOCK:
 Demux ; SFunction ; Terminator ;Action Port;C Function;Demux;From;Function-Call Subsystem;Goto;If Action Subsystem;MATLAB Function;MATLAB System;Merge;Mux;SubSystem;Subsystem;Switch Case;Terminator;Variant Source;autoGeneratedPeripherals;emptyPayloadBufferTx;emptyPeripheralDatasizeResponse;emptyStatus;emptyfunNotFound;funNotFound;function;out;payloadBufferRx;payloadBufferTx;peripheralDataSizeResponse;requestID;requestId;status;u;y

BLOCKTYPE:
ActionPort;CFunction;Constant;Demux;From;Goto;Inport;MATLABSystem;Merge;Mux;Outport;S-Function;SwitchCase;Terminator;TriggerPort;VariantSource


MODELNAME: iobuilder
PATH: toolbox/target/supportpackages/arduinobase/iobuilder/iobuilder.slx
ANNOTATION: Analog output Input capture WiFi initialization WiFi TCP WiFiUDP Analog output
BLOCKTYPE_FREQUENCY: 27;1;26;64;17;33;27;55;36;3;14;70;16;6;2;7;18;1;14
CHECKSUM: F0957CD770A73F5C10F6517E1D223290
PRODUCT_BASECODE: ARDUINO
BLOCK:
 Demux ; SFunction ; Terminator ;Action Port;Byte Unpack;C Function;Demux;From;Function-Call Subsystem;Goto;If Action Subsystem;In;MATLAB Function;MATLAB System;Merge;Mux;Reference;Selector;SubSystem;Subsystem;Sum;Switch Case;Terminator;Variant Source;autoGeneratedPeripherals;emptyPayloadBufferTx;emptyPeripheralDatasizeResponse;emptyStatus;emptyfunNotFound;emptypayloadBufferTx;funNotFound;function;out;payloadBufferRx;payloadBufferTx;peripheralDataSizeResponse;requestID;requestId;status;u;y

BLOCKTYPE:
ActionPort;Byte Unpack;CFunction;Constant;Demux;From;Goto;Inport;MATLABSystem;Merge;Mux;Outport;S-Function;Selector;Sum;SwitchCase;Terminator;TriggerPort;VariantSource

PRODUCT:
Embedded Coder;Image Processing Toolbox;MATLAB;Simulink;Simulink Support Package for Arduino Hardware


MODELNAME: tc3x_2ledsBlinky
PATH: toolbox/target/supportpackages/aurixtc3x/aurix_examples/tc3x_2ledsBlinky.slx
BLOCKTYPE_FREQUENCY: 2;1;4;3;2;1;4;1;1;1;3;1;2;1;3;2;1;1;1;1
CHECKSUM: C385ADDD39CE2BD1BC5E0896F5594322
PRODUCT: Embedded Coder;Embedded Coder Support Package for Infineon AURIX TC3x Microcontrollers;Simulink
PRODUCT_BASECODE: IFX_AURIX_TC3x
ANNOTATION:
 Running-Light Pattern Switch On the next LED  LEDs have reverse polarity, e.g. low = LED On  Alternate-Light Pattern  LEDs have reverse polarity, e.g. low = LED On Set Ts = 1e-3 for VP simulation or Ts = 0.5 for hardware deployment. You can consider reducing the Ts for hardware deployment if the GPIO P00.7 button press needs to be captured quickly.  Algorithm Different LED pattern Input Leading-Edge-Flip-Flop Copyright 2023 The MathWorks, Inc.  Getting Started with Infineon AURIX TC3x  Led Panel

BLOCK:
Action Port;Add;Bitwise NOT;Bitwise XOR;Constant;Counter Free-Running;D Flip-Flop;Data Type Conversion;Demux;Digital Port Read;Digital Port Write;Extract Bits;If;If Action Subsystem;Merge;Mux;Out;P00.;Reference;Shift Arithmetic;Step;SubSystem;Switch;Variant Source

BLOCKTYPE:
ActionPort;ArithShift;Bitwise Operator;Constant;Counter Free-Running;DFlipFlop;DataTypeConversion;Demux;DigitalPortRead;DigitalPortWrite;Extract Bits;If;LampBlock;Merge;Mux;Outport;Step;Sum;Switch;VariantSource


MODELNAME: tc3x_external_mode
PATH: toolbox/target/supportpackages/aurixtc3x/aurix_examples/tc3x_external_mode.slx
ANNOTATION: External Mode Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;1;1;1;1;2;1;1;1
CHECKSUM: DD5AFC316EE818910519AB0FB063C7F6
PRODUCT: Embedded Coder;Embedded Coder Support Package for Infineon AURIX TC3x Microcontrollers;Simulink
PRODUCT_BASECODE: IFX_AURIX_TC3x
BLOCK:
Constant;Dashboard Scope;Digital Port Write;Gain;Manual Switch;Pulse Generator;Reference;Scope;Sine Wave;Slider

BLOCKTYPE:
Constant;DashboardScope;DigitalPortWrite;DiscretePulseGenerator;Gain;ManualSwitch;Scope;Sin;SliderBlock


MODELNAME: hexagon_audio_eq
PATH: toolbox/target/supportpackages/hexagon/hexagonexamples/hexagon_audio_eq.slx
ANNOTATION: Parameteric Audio Equalizer on Hexagon Simulator Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;9;18;1;1;6;18;1;6;7;3
CHECKSUM: 1A413F4E558C0DA1FCBF4C9EAC794AE6
PRODUCT: DSP System Toolbox;Embedded Coder;MATLAB;MATLAB Coder;Simulink
EXTERNALFILE_REFERENCE: hexagon_audio_eq_mdlref.slx___Model_Block___
BLOCK:
Audio Device Writer;BW_;Constant;Display;Equalizer;Fc_;Filter Visualizer;From Multimedia File;Gain;Gain_;Knob;Out;Output;Reference;SubSystem;panelInfo;untitledPanel

BLOCKTYPE:
Audio Device Writer;Constant;DisplayBlock;Filter Visualizer;From Multimedia File;Gain;KnobBlock;ModelReference;Normalize Frequency;Outport;PanelWebBlock


MODELNAME: hexagon_top_model_pil
PATH: toolbox/target/supportpackages/hexagon/hexagonexamples/hexagon_top_model_pil.slx
DESCRIPTION: Example model reference component.
BLOCKTYPE: Constant;EnablePort;Inport;Logic;Outport;RelationalOperator;Sum;Switch;UnitDelay
BLOCKTYPE_FREQUENCY: 3;2;8;3;4;1;2;3;2
CHECKSUM: 5E7587766D8ABAAF915EDFDF0493FE23
PRODUCT: Embedded Coder;MATLAB;MATLAB Coder;Simulink
ANNOTATION:
 Copyright 2023 The MathWorks, Inc.   Copyright 2023 The MathWorks, Inc.   Copyright 2023 The MathWorks, Inc.  Top Model PIL


MODELNAME: flightControlSystem
CHECKSUM: D468006389600F491BA0AC5B42DD974D
PRODUCT_BASECODE: MINIDRONES
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/parrotHoverTemplate/controller/flightControlSystem.slx

ANNOTATION:
PID Controller for Altitude  ALTITUDE CONTROLLER Inner loop PID controls angular velocity Outer Proportional loop controls the pitch and roll angle  ATTITUDE CONTROL Position controller requires good estimate of Yaw orientation to work properly. Incase position control is not needed, the outer loop can be removed and velocity setpoint can be given directly  Inner loop controls linear velocity error Outer loop controls the position error Yaw angle is not constrained between -180 to 180 degrees Yaw estimation is done solely using the gyroscope and it may drift with time. When the land_drone flag is not set, pass a 0 to the flag to indicate no error  If the land_flag is set, wait till the drone reaches a height of -0.3m and then shut down the drone using a 255 flag  If the land_flag is set, then disable Optical Flow check Vision-based Data from the Image Processing System  The Minidrone presently takes off to (0,0,-1.1) co-ordinate and stays there. Estimated Values from the State Estimator Update the pos_ref (X,Y, Z) position co-ordinates This subsystem contains the logic to land the drone. The drone starts landing if the land_drone flag is set by clicking on the Land button on the Parrot_FlightInterface. The drone also starts landing, if the time_remaining is less than 5s. Gyroscopes bias is susceptible to factors like temperature and Gyro bias stability and it can vary during the flight. It is therefore estimated using this Kalman filter making use of Accelerometer data Linear Kalman filter is used for the Pitch and Roll estimation. The states are the corresponding Euler angle and Angular rate bias respectively Linear Kalman filter is used for the Pitch and Roll estimation. The states are the corresponding Euler angle and Angular rate bias respectively Gyroscopes bias is susceptible to factors like temperature and Gyro bias stability and it can vary during the flight. It is therefore estimated using the Kalman filter making use of accelerometer data Yaw angle is not constrained between -180 to 180 degrees Currently yaw angle is obtained solely by integrating the gyroscope output. This yaw estimate can drift with time.  ACCELEROMETER CHECK  This estimator algorithm is developed for linearized kinematic model (model is linearized about hovering condition)This estimator may not work for large angle / aggressive maneuvers.   Gyroscopes bias is affected by temperature.This wont be a problem for Pitch and Roll angle estimation as the actual gyroscope bias in the Pitch and Roll axis are estimated during the flight. However the yaw orientation is obtained by integrating the gyroscope output and it may drift with time. Even the preflight calibration which is done cannot compensate for this problem as the gyro bis varies during the flight.    IMU Optical flow readings are affected by both linear and angular velocity of the drone. We need to subtract the effect of angular velocity before using the flow data prevents use of optical flow with large angles, angular rates or accelerations enables OF for very low angular rates checks if angular dynamics and altitude allow for reasonable use of optical flow measurement, also checks against current estimate checks new measurement vs current estimate requires minimum altitude  Optical flow raw readings are converted to velocity in m/s based on the estimated altitude Switching from orientationControl to Position control reset the current world position estimate (happens when using no markers) Derived frrom the work by Sertac Karaman and Fabian Riether Use 1 for X, Y, Z and Yaw control Use 0 for Pitch, Roll and Yaw control Position or Orientation Control Use this subsystem to change the path of the Minidrone using the Vision-based Data as an additional input. Derived from the work by Sertac Karaman and Fabian Riether  Note: The PARROT Image Conversion block takes the raw Y1UY2V data provided by the drones downward-facing camera, and converts the color space to the desired RGB or YUV output.   Note: Develop the image processing algorithm and use the Vision-based Data outport to send the processed data to the Flight Control System. The output data can be of any type and size (Try to avoid large data transfers).  Copyright 2018-2022 The MathWorks, Inc. Flight Control System

BLOCK:
 ; Demux ; Disable OF check; SFunction ; Terminator ;0.5 meters;50 continuous OF errors ;AC cmd;AND;Abs;Abs ;Absestdiff;AccelerationHandling;Accelerometer;Action Port;Actuators;Add;Alt_error;Alt_prs;Altitude Controller;Altitude Estimator;Altitude error check;Angle control loop;Angular velocity compensation for optical flow;Angular velocity control loop;Angular velocity w/o bias;Assuming that the preflight calibration was done at level orientation;Attitude Controller;Attitude Estimator;Bus Assignment;Bus Creator;Bus Selector;Check error condition;Check if the drone is 0.3m above ground;Compare To Constant;Compare with Stop time;Constant;Control Mode Update;ControlMixer;Controller;Counter Free-Running;Crash Prediction Flags;D_yaw;D_z;Data Type Conversion;DataHandling;Deactivate Acceleration If OF is not used due to low altitude;Delay;Delay One Step;Demux;Diff;Difference between sonar and pressure;Disable temperature compensation;Discrete-Time Integrator;DiscreteDerivative;Divide;Enable_Alt_Check;Enable_OF_Check;EstimatedVal;EstimatorVelocity;EstimatorXYPosition;FIR_IMUaccel;Flag;Flight Control System;Gain;Geofencing error;GreaterThan;GreaterThan ;Gyro Temperature;Gyroscope;HAL_acc_SI;HAL_gyro_SI;HAL_pressure_SI;HAL_ultrasound_SI;HAL_vbat_SI;IIR_IMUgyro_r;IIRgyroz;I_pr;I_yaw;If;Image Data;Image Processing System;In;In Bus Element;Kalman Filter;KalmanFilter_altitude;KalmanFilter_dxdy;LPF 8Hz Cutoff Filter to avoid oscillations induced by position controller;LPF Fcutoff = 40Hz;Land;Land Flag;Landed;Landing Enable;Landing Logic;Landing look-ahead distance;Logical Operator;Manual Switch;Math Function;Merge;MotorDirections;Multiport Switch;Mux;NOT;No optical flow ;No_error;Normal condition and landing;OF_Error;OF_status;OR;Optical flow error check;Out;Out Bus Element;OutlierHandling;PARROT Image Conversion;P_yaw;P_z;Path Planning;Pitch correction;Pitch_Kalman;PosZ;Position Controller;Position controller;Position error transformation (Earth to Body frame);Product;Rate Transition;Reference;ReferenceValueServerCmds;Roll_Kalman;Rotation Angles to Direction Cosine Matrix;Saturation;SaturationSonar;SaturationThrust;Select Accel;Select dxy;Select pqr;SelectPlanarddxy;SelectdXY;Selector;Selectpitchroll;SensorPreprocessing;Sensors;SimplyIntegrateVelocity;Sqrt;State Estimator;States;SubSystem;Subtract;Sum;Sum of Elements;Switch;Switch_refAtt;TakeoffOrControl_Switch;Temperature Compensation;Terminator;ThrustToMotorCommand;Time remaining;To Workspace;TorqueTotalThrustToThrustPerMotor;Trigger;Triggered Subsystem;Trigonometric Function;Ultrasound improper;UpdatedReferenceCmds;Variant Source;Velocity controller;Vision-based Data;Wait 3 Seconds;X;XY Position Estimator;XY velocity w/o angular velocity compensation;XYZ;XY_estimout;Y;Yaw Controller;Yaw_integrator;Z_estimin;Z_estimout;acceleration_world;altPrs_datin;altSonar_datin;altSonar_datout;altitude_cmd;angular velocity;angular velocity compensation;angular velocity correction;axyz;check for min altitude;controlModePosVSOrient_flagin;controlModePosVsOrient;currentEstimateVeryOffFromPressure;currentStateVeryOffsonarflt;do not use acc if optical flow never available (Note OF@60Hz but ZOH to 200!);dorient_estimaout;dxyOF_datin;dxy_estimin;dxy_estimout;dz_estimin;dz_estimout;enableKFmeasupdate_flagout;enable_flag;enable_update;estimator/Optical flow error;findingoutliers;gainaccinput;gravity;gyro_x_bias;gyro_y_bias;gyro_z_bias;imu_abs;inverseIMU_gain;invertzaxisGain;land_flag;maxdw;maxp;maxq;maxw;minHeightforOF;motorCmds;motors_cmdout;motors_refout;newupdateneeded;nicemeasurementor newupdateneeded;norm(accelerometer);opticalFlowErrorCorrect;opticalFlow_datin;optical_flow;optical_flow_dx_dy;orient_estimaout;orient_estimin;outlierBelowFloor;outlierJump;pitch;pitch_rate;pitch_roll_cmd;posXY;pressureFilter_IIR;prod;prsDelta_datin;prsDelta_datout;prsToAltGain;r;refAttitude;roll;roll_rate;sensorCalibration_datin;sensorIMU;sensorIMU_datin;sensorIMU_datout;sensor_data_in;sensordata_datin;sensordata_group;single;sonarFilter_IIR;states_estim;takeoff_flag;takeoff_gain;tau_pitch;tau_roll;tau_yaw;thrustsToMotorCommands;thrusts_refin;thrusts_refout;totalThrust;uncompensated_gyro_z_rate;w;xValue;xy_err_body;xy_err_earth;yValue;yaw;yaw_rate;yaw_ref;zValue;z_estimate;zero correction

BLOCKTYPE:
Abs;ActionPort;Ang2DCM;Bias;BusAssignment;BusCreator;BusSelector;Compare To Constant;Constant;Counter Free-Running;DataTypeConversion;Delay;Demux;Discrete Derivative;DiscreteFilter;DiscreteFir;DiscreteIntegrator;DiscreteTransferFcn;Gain;If;Inport;InportShadow;Logic;ManualSwitch;Math;Merge;MultiPortSwitch;Mux;Outport;PID 1dof;Product;RateTransition;RelationalOperator;S-Function;Saturate;Selector;Sqrt;Sum;Switch;Terminator;ToWorkspace;TriggerPort;Trigonometry;VariantSource;ctrlKalmanFilter;parrot.ImageProcess

BLOCKTYPE_FREQUENCY:
21;5;3;1;2;1;32;34;26;4;19;4;19;1;4;1;4;3;21;1;109;8;17;2;3;1;1;17;82;4;10;1;2;1;4;25;1;28;7;16;1;2;2;1;4;1

PRODUCT:
Embedded Coder;Simulink;Simulink Support Package for Parrot Minidrones;System Identification Toolbox;Vehicle Dynamics Blockset


MODELNAME: linearAirframe
ANNOTATION: Copyright 2013-2019 The MathWorks, Inc. Linear Airframe Model
BLOCKTYPE: Bias;BusCreator;BusSelector;Concatenate;DataTypeConversion;Inport;Mux;Outport;Selector;StateSpace
BLOCKTYPE_FREQUENCY: 16;1;1;1;1;13;1;3;12;1
CHECKSUM: CB81039782F07FF2B8D1121871D10A05
PRODUCT: Simulink;Simulink Support Package for Parrot Minidrones
PRODUCT_BASECODE: MINIDRONES
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/parrotHoverTemplate/linearAirframe/linearAirframe.slx


MODELNAME: trimNonlinearAirframe
BLOCKTYPE: BusCreator;BusSelector;Inport;ModelReference;Outport
BLOCKTYPE_FREQUENCY: 2;1;9;2;10
CHECKSUM: AFB23248470D43F80DB3DAA83B2D3514
PRODUCT: Simulink;Simulink Support Package for Parrot Minidrones
PRODUCT_BASECODE: MINIDRONES
EXTERNALFILE_REFERENCE: linearAirframe.slx___Model_Block___nonlinearAirframe.slx___Model_Block___
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/parrotHoverTemplate/linearAirframe/trimNonlinearAirframe.slx


MODELNAME: parrotMinidroneHover
CHECKSUM: 25DDC2E77A78A3FFAAF6BB2DEA38B511
PRODUCT_BASECODE: MINIDRONES
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/parrotHoverTemplate/mainModels/parrotMinidroneHover.slx

ANNOTATION:
VSS_COMMAND = 0 will select Signal Builder VSS_COMMAND =1 will select Joystick + Signal Builder VSS_COMMAND = 2 will select pre-saved data from .mat file VSS_COMMAND = 3 will select pre-saved data from a spreadsheet VSS_ENVIRONMENT = 0 will select constant environment variables VSS_ENVIRONMENT = 1 will select environment variables depending on position VSS_VEHICLE = 0 will select linear airframe VSS_VEHICLE = 1 will select nonlnear airframe Optical flow is measured by using a camera and is calculated based on how the image actually moves. It is thus dependant on body angular velocity and bodys linear velocity. This is a crude simulation of optical flow (vx,vy,vz) as fed into the c-function rsedu_optical_flow() on the Rolling Spider by internal, inaccessible code of Parrots firmware. This is assumed to be far from what optical flow (vx,vy,vz) actually is! IMU block simulates the 6DOF sensor MPU6050 that we have on board. Please note that this model cannot simulate the gyros bias change over time! This is a crude simulation of optical flow (vx,vy,vz) as fed into the c-function rsedu_optical_flow() on the Rolling Spider by internal, inaccessible code of Parrots firmware. This is assumed to be far from what optical flow (vx,vy,vz) actually is! VSS_SENSORS = 0 will select feedthrough sensors VSS_SENSORS = 1 will select dynamics sensors with noise Flight Visualization Simulation Model Flight Control System - Code Generation Flight Commands Quadcopter Flight Simulation Model - Mambo

PRODUCT:
Aerospace Blockset;Computer Vision Toolbox;Embedded Coder;MATLAB;Simulink;Simulink 3D Animation;Simulink Support Package for Parrot Minidrones


MODELNAME: nonlinearAirframe
ANNOTATION: Copyright 2013-2019 The MathWorks, Inc. Nonlinear Airframe Model
BLOCKTYPE_FREQUENCY: 1;1;1;1;7;1;1;1;6;38;2;15;3;1;1;1;1;3;1
CHECKSUM: 7AAFBF62868EF25C9F2481D90704255D
PRODUCT: Aerospace Blockset;Simulink;Simulink Support Package for Parrot Minidrones
PRODUCT_BASECODE: MINIDRONES
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/parrotHoverTemplate/nonlinearAirframe/nonlinearAirframe.slx


MODELNAME: flightControlSystem
BLOCKTYPE_FREQUENCY: 6;3;16;6;3;25;5;2;2;7;1;23;3;4;1;5;32;2;7;7
CHECKSUM: C544614190244ACA92F30B2F690DF2A1
PRODUCT: Embedded Coder;Simulink;Simulink Support Package for Parrot Minidrones
PRODUCT_BASECODE: MINIDRONES
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/slQuadcopter/controller/flightControlSystem.slx

ANNOTATION:
Derived frrom the work by Sertac Karaman and Fabian Riether  Design your own Estimator and Controller in the framework provided  Copyright 2013-2020 The MathWorks, Inc. Flight Control System

BLOCK:
AC cmd;Abs;Action Port;Actuators;Bus Selector;Commands;Compare To Constant;Constant;Controller;Crash Predictor Flags;Data Type Conversion;Demux;Estimator;Flag;Flight Control System;Gain;Geofencing error;Ground;HAL_acc_SI;HAL_gyro_SI;HAL_pressure_SI;HAL_ultrasound_SI;HAL_vbat_SI;If;Logging;Logical Operator;Merge;Mux;Normal condition;Out;Out Bus Element;Pulse Generator;Reference;ReferenceValueServerBus;ReferenceValueServerCmds;SensorCalibration;Sensors;SubSystem;Subtract;Terminator;To Workspace;Vision Sensors;estimator/Optical flow error;motorCmds;motorsCmd;posRef;sensordata_datin;sensordata_group;sensors_dat_in;state_estim;states_estim

BLOCKTYPE:
Abs;ActionPort;BusSelector;Compare To Constant;Constant;DataTypeConversion;Demux;DiscretePulseGenerator;Gain;Ground;If;Inport;InportShadow;Logic;Merge;Mux;Outport;Sum;Terminator;ToWorkspace


MODELNAME: slQuadcopter
BLOCKTYPE_FREQUENCY: 1;3;6;3;1;1;3;9;1;7;3;1;2;11;2;1;1;3;12;1;6;1;4;1;1;1;1
CHECKSUM: B36B5B77FC33F7EC3EBF6F02698C6EF6
PRODUCT: MATLAB;Simulink;Simulink Support Package for Parrot Minidrones
PRODUCT_BASECODE: MINIDRONES
EXTERNALFILE_REFERENCE: flightControlSystem.slx___Model_Block___
PATH:
toolbox/target/supportpackages/parrot/templates/projecttemplate/slQuadcopter/mainModels/slQuadcopter.slx

ANNOTATION:
You can find a full implementation of this template in the Aerospace Blockset Documentation Quadcopter Flight Simulation Template Copyright 2013-2017 The MathWorks, Inc.

BLOCK:
AC Cmd;Actuators;Air Density;Air Temp;Airframe;Assertion;Assumes takeoff was level;Bias;Bus Creator;Bus Selector;Camera;Clock;Command;Commands;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Demux;Environment;Euler;FCS;Flag;FromWs;Gravity;HAL_acquisition_creator;IMU_Pressure;Live Time Ticks;Logical Operator;Magnetic Field;Memory;Motors;Mux;Pitch;Position/Attitude Reference;Pressure;Product;Rate Transition;Reference;Roll;Saturation;Selector;Sensor System;Sensors;Speed of Sound;States;Stop Simulation;SubSystem;Sum;Terminator;V_body;Visualization;X;X_ned;Y;Yaw;Z;_DUMMY_FLAG_usePosVIS;_DUMMY_posVIS;altToprs_gain;opticalFlow_data;sensordata_data;sensordata_datout;states_datin

BLOCKTYPE:
Assertion;Bias;BusCreator;BusSelector;Clock;Compare To Constant;Compare To Zero;Constant;Counter Free-Running;DataTypeConversion;Demux;FromWorkspace;Gain;Inport;Logic;Memory;ModelReference;Mux;Outport;Product;RateTransition;Saturate;Scope;Selector;Sigbuilder block;Sum;Terminator


MODELNAME: raspberrypi_multicore_audio
BLOCKTYPE_FREQUENCY: 1;2;3;3;1;1;2;1;1;1
CHECKSUM: 38EA0AB36E5FBCCC2CE93ED46D513982
PRODUCT: Audio Toolbox;DSP System Toolbox;Simulink;Simulink Support Package for Raspberry Pi Hardware
PRODUCT_BASECODE: RASPPI
PATH:
toolbox/target/supportpackages/raspberrypi/raspberrypitemplates/projecttemplate/raspberrypi_Multicore/models/raspberrypi_multicore_audio.slx

ANNOTATION:
Output Function1 Input  Control audio frequency bands  Copyright 2020 The MathWorks, Inc. Function2  This model allows users to control the Left and Right audio channels. Follow the steps mentioned in the documentation to do explicit partitioning and concurrently execute tasks on a multicore Raspberry Pi

BLOCK:
 ;ALSA Audio Playback;Audio File Read;Crossover Filter;Gain-Final;Gain-HF;Gain-LF;Graphic EQ-HF;Graphic EQ-LF;Limiter-Final;Reference;Slider;Variable Selector;Vector Concatenate

BLOCKTYPE:
Concatenate;DataTypeConversion;Gain;SliderBlock;Variable Selector;audio.simulink.DynamicRangeLimiter;audio.simulink.GraphicEQ;audio.simulink.crossover;codertarget.raspi.internal.RaspiALSAAudioPlayback;codertarget.raspi.internal.RaspiAudioFileRead


MODELNAME: raspberrypi_multicore_audio_tasks_mapped
BLOCKTYPE_FREQUENCY: 1;2;3;4;4;3;1;1;2;1;1;1
CHECKSUM: BFBBA85760FD3FB113D83A5F53C9250C
PRODUCT_BASECODE: RASPPI
PATH:
toolbox/target/supportpackages/raspberrypi/raspberrypitemplates/projecttemplate/raspberrypi_Multicore/models/raspberrypi_multicore_audio_tasks_mapped.slx

ANNOTATION:
 This model allows users to control the Left and Right audio channels. The model is partitioned to execute concurrently on a multicore Raspberry Pi  Copyright 2020 The MathWorks, Inc.  Control audio frequency bands (multicore)

BLOCK:
 ;ALSA Audio Playback;Audio File Read;Crossover Filter;Function;Gain-Final;Gain-HF;Gain-LF;Graphic EQ-HF;Graphic EQ-LF;In;Input;Limiter-Final;Out;Output;Reference;Slider;SubSystem;Variable Selector;Vector Concatenate

BLOCKTYPE:
Concatenate;DataTypeConversion;Gain;Inport;Outport;SliderBlock;Variable Selector;audio.simulink.DynamicRangeLimiter;audio.simulink.GraphicEQ;audio.simulink.crossover;codertarget.raspi.internal.RaspiALSAAudioPlayback;codertarget.raspi.internal.RaspiAudioFileRead

PRODUCT:
Audio Toolbox;DSP System Toolbox;Embedded Coder;Simulink;Simulink Support Package for Raspberry Pi Hardware


MODELNAME: raspberrypi_multicore_simple
BLOCK: Counter Limited;LED;Multiply;Random Number;Reference;Relational Operator;Threshold
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1
CHECKSUM: F8F61E08DD103C5A4C6CFEBE989CB0CE
PRODUCT: Embedded Coder;Simulink;Simulink Support Package for Raspberry Pi Hardware
PRODUCT_BASECODE: RASPPI
PATH:
toolbox/target/supportpackages/raspberrypi/raspberrypitemplates/projecttemplate/raspberrypi_Multicore/models/raspberrypi_multicore_simple.slx

ANNOTATION:
Input Function Output Raspberry Pi Multicore Simple Copyright 2020 The MathWorks, Inc.  Follow the steps mentioned in the documentation to do explicit partitioning and concurrently execute tasks on a multicore Raspberry Pi

BLOCKTYPE:
Constant;Counter Limited;Product;RandomNumber;RelationalOperator;codertarget.raspi.internal.LEDBlock


MODELNAME: raspberrypi_multicore_simple_tasks_mapped
BLOCKTYPE_FREQUENCY: 1;1;3;3;1;1;1;1
CHECKSUM: 4669489820AE36006C1AACA22BD2FBA9
PRODUCT: Embedded Coder;Simulink;Simulink Support Package for Raspberry Pi Hardware
PRODUCT_BASECODE: RASPPI
PATH:
toolbox/target/supportpackages/raspberrypi/raspberrypitemplates/projecttemplate/raspberrypi_Multicore/models/raspberrypi_multicore_simple_tasks_mapped.slx

ANNOTATION:
 The model is partitioned to execute concurrently on a multicore Raspberry Pi Copyright 2020-2021 The MathWorks, Inc. Raspberry Pi Multicore Simple (tasks mapped)

BLOCK:
Counter Limited;Function;In;Input;LED;Multiply;Out;Output;Random Number;Reference;Relational Operator;SubSystem;Threshold ;y

BLOCKTYPE:
Constant;Counter Limited;Inport;Outport;Product;RandomNumber;RelationalOperator;codertarget.raspi.internal.LEDBlock


MODELNAME: HWIBlockTemplate
PATH: toolbox/target/supportpackages/targetsdk/templates/hwi/HWIBlockTemplate.slx
ANNOTATION: Copyright 2017 The MathWorks, Inc. Hardware Interrupt Block
BLOCK: Hardware Interrupt;Out;Reference;SubSystem;Task;Variant Source
BLOCKTYPE: ESB Task;ESB Task Hardware Interrupt;Interrupt Block;Outport;S-Function;VariantSource
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1
CHECKSUM: F7C43F3C2B100C80D3D514E402341D05
PRODUCT_BASECODE: ECCORTEXA;ECCORTEXM;ECCORTEXR;IFX_AURIX_TC4x;INFINEON_AURIX;IFX_AURIX_TC3x;NVIDIA
PRODUCT:
Embedded Coder Support Package for Infineon AURIX TC3x Microcontrollers;MATLAB;Simulink;SoC Blockset


MODELNAME: BTReferenceApplication
PATH: toolbox/vdynblks/vdynsolution/projectsrc/BrakingTest/System/BTReferenceApplication.slx
CHECKSUM: 35B0A52E0AEB6BAD7A8E94C9ED4647CE
PRODUCT: MATLAB;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear  1) Add additional chassis Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Placeholder for introducing faults, detailed actuator behavior, interactions of other systems with a human interface such as changes in power steering and braking assistance.   1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Vehicle Response Driver Commands Copyright 2020-2024 The MathWorks, Inc.

BLOCK:
 Demux ; Driver; Gear; SFunction ; Terminator ;1-D Lookup Table;10ms Function-Call Generator;2-D Lookup Table;2D Lookup Tbl for Scaling Fctr (Lambda);3D Engine;3D Engine Disabled;3D Engine Source;<Accel>;<Kappa>;<WhlAccel>;<xdot>;ABSCtrlForEach;ABSFlag;ABSForEachWheel;Abs;Acc to Torque Request;AccCmd;AccFdbk;Accel;AccelCmd;AccelFdbk;AccelGround;Acceleration Cmd;Active Differential Control;Add;AllParts;Antilock Brake System;AxlTrq;Bang Bang ABS;Bang-bang controller;Body;Body Ptich;Body Roll;Body Yaw;Body, Suspension, Wheels;BodyX;BodyY;BodyZ;Brake;Brake Cmd;Brake Pedal;Brake Pressure Control;BrakeGround;BrkCmd;BrkCtrl;BrkFlag;BrkPrs;BrkPrsCmd;Bus Creator;Bus Element In;Bus Selector;Bus to Vector;Calculate Downshift Threshold;Calculate Upshift Threshold;Cg;Chassis Input;Chassis Output;Clock;Cnst Lambda;Cntrl;CntrlRx;CntrlTx;Compare To Constant;Compare To Zero;ConcatOut;Constant;Controllers;Creating Inertial Frm Bpt;Current Gear;DCM;Data Type Conversion;Dead Zone;Debounce;DecelCmd;DecelFdbk;Demux;Detect Increase;DiffPrsCmd;DiffTrqCmd;Disabled;Discrete-Time Integrator;Display;Divide;DownReq;Driveline;Driveline Ideal Fixed Gear;Driveline Input;Driveline Output;Driver;Driver - No Clutch;Driver Commands;ECU;Electronic Stability;En at t = ;Enable;Enabled;Enb;Eng;EngSpd;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Input;Engine Output;Engine Tach [rpm];Env;Environment;First Order Hold;Five-State ABS and TCS;Flag;For Each;For Each Subsystem;FricCoeffLambda;Friction;FrntAxlLftX;FrntAxlLftY;FrntAxlRghtX;FrntAxlRghtY;From;Gain;Gear;GearCmd;GearFdbk;GearGround;GearReq;Gnd;Goto;Ground;Ground Feedback;Handwheel Angle [deg];Highbeam;ISO 15037-1:;Ideal Mapped Engine;In Bus Element;Integrator;Internal Tire Contact Plotter;Interpreted MATLAB Function;IsNegative;Kappa;KappaEst;Lambda (t = 0) ;Lambda for each whl;Lateral Acceleration [g];Left Signal;Linear Predictive Driver;Logical Operator;Longitudinal Driver;Lowbeam;MATLAB Function;Matrix Concatenate;Max;Multiple Points;Mux;Neutral;Neutral Select;No Control;OR;Omega;Open Loop;OperatorFdbk;Out;Out Bus Element;PID Controller;PRNDL Controller;Paddles;Part Rotation Concatenation;Part Translation Concatenation;PartConcatenation;PassVeh14DOF;PassVeh7DOF;Passenger Vehicle;Pb;PbFdbk;PbOutput;Pedal Cluster Input;Pedal Cluster Output;Pedal Cluster and Cabin;Predictive Driver;Pref;Product;PropShftSpd;Range Limiter;Rate Transition;Rear Diff Controller;RearAxlLftX;RearAxlLftY;RearAxlRghtX;RearAxlRghtY;Reference;Relational Operator;Reshape;Rev Limiter Control;Reverse;Right Signal;Road Track Friction;Rotation Angles to Direction Cosine Matrix;SG Diff;Saturation;Scale;ScaleOut;Selector;Sensors;Signal Copy;Signal Specification;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Single Point;SpdThr;Speed LPF;Speed [mph];Steer;SteerCmd;SteerFdbk;SteerGround;SteerHWCmd;Steering;Steering, Transmission, Driveline and Brakes;StrWhlTrq;Straight Maneuver Reference Generator;SubSystem;Subsystem;Subtract;Sum;Sum of Elements;Switch;TCM;TCM Shift Controller;TCSCtrlForEach;TCSFlag;Terminator;Three-axis Inertial Measurement Unit;Torque Cmd;Transmission Controller;Transmission Controller PRNDL;TrqCmd;TrqCmdRevLimited;Unary Minus;Unit Conversion;UpReq;Vector Concatenate;Veh;VehFdbk;VehRef;VehSpd;Vehicle XY Plotter;Visualization;Wheel Accel;Wheel Accel and Slip Estimator;Wheel Coordinates;WheelDCM;WheelFrontLeft;WheelFrontLeft Pitch;WheelFrontLeft Roll;WheelFrontLeft Yaw;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRight Pitch;WheelFrontRight Roll;WheelFrontRight Yaw;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeft Pitch;WheelRearLeft Roll;WheelRearLeft Yaw;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRight Ptich;WheelRearRight Roll;WheelRearRight Yaw;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels;WhlAccel;WhlAng;WhlSlip;Wind;WindXYZ;XBpt;XCg;XWhl;YBpt;YCg;YWhl;Yaw Rate, Brake Pressure, Velocity, Lat Accel;Zend Select;axayaz;axle distance;calc;calc_down;calc_up;div0protect - poly;down_th;e;f;function;gear;in_;mu;out_;pedal;phi,theta,psi;pqr;speed;steer ratio;up_th;wheel radius;xdot;z;zero

BLOCKTYPE:
3D Engine;Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;CircularGaugeBlock;Clock;Compare To Constant;Compare To Zero;Concatenate;Constant;DataTypeConversion;DeadZone;Debounce;Demux;Detect Increase;DiscreteIntegrator;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;Display;Driver Commands;EnablePort;FirstOrderHold;Five-State ABS Control;Five-State TCS Control;ForEach;From;Function-Call Generator;Gain;Goto;Ground;ISO 15037-1:2006;Inport;Integrator;LampBlock;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;MATLABFcn;Memory;MinMax;ModelReference;Mux;Outport;PID 1dof;Predictive Driver;Product;RateTransition;RelationalOperator;Reshape;Road Track Friction;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalConversion;SignalSpecification;Simplified Savitzky-Golay Differentiator;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Straight Maneuver Source;Sum;Switch;Terminator;Terrain Source;Three-axis Inertial Measurement Unit;Tire Contact Plotter;Transmission Controller PRNDL;TriggerPort;UnaryMinus;UnitConversion;UnitDelay;Vehicle XY Plotter

BLOCKTYPE_FREQUENCY:
1;4;1;21;46;7;2;1;11;2;28;55;22;6;3;17;1;2;1;1;1;1;1;12;1;1;7;13;1;10;9;9;1;265;4;2;2;10;1;6;1;1;1;4;5;134;1;1;4;14;5;6;1;5;14;1;14;2;1;1;44;1;1;2;1;1;19;8;40;1;1;1;1;4;3;28;1;1

EXTERNALFILE_REFERENCE:
Driveline___Model_Block___PassVeh14DOF___Model_Block___PassVeh7DOF___Model_Block___SiMappedEngineV___Model_Block___


MODELNAME: CiEngineMappedCntrlV
PATH: toolbox/vdynblks/vdynsolution/projectsrc/CI/Controller/CiEngineMappedCntrlV.slx
ANNOTATION: Copyright 2017-2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;3;7;1;1;10;26;3;19;2;4;12;2
CHECKSUM: A5AD977CCE0CF600C905BD39C7820D78
PRODUCT: Powertrain Blockset;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
BLOCK:
Add;AmbPrs;Bus Selector;CI Controller;Compare To Constant;Constant;Ect;EgrVlvAreaPct;EgrVlvAreaPctCmd;EgrVlvDeltaPrs;EgrVlvInTemp;EngSpd;EstIntkPortFlw;ExhCamPhase;ExhCamPhaseCmd;From;FuelMainSoi;Goto;Ground;Iat;IgSw;InjPw;InjPwIn;IntkCamPhase;IntkCamPhaseCmd;IntkSwirlVlvPos;IntkSwirlVlvPosCmd;IntkVlvLift;IntkVlvLiftCmd;LoadCmd;Logical Operator;Map;Mat;Reference;SpkAdv;Start Stop Logic;SubSystem;Switch;Terminator;ThrPosPct;ThrPosPctCmd;TrqCmd;TrqCmdISC;TrqCmdIsc;TrqCmdIscIn;TurboRackPos;TurboRackPosCmd;TurboSpd;Unit Delay;VarCompRatioPos;VarCompRatioPosCmd;VarIntkManPos;VarIntkManPosCmd;VarIntkRunLen;VarIntkRunLenCmd;WgAreaPct;WgAreaPctCmd

BLOCKTYPE:
BusSelector;CI Controller;Compare To Constant;Constant;From;Goto;Ground;Inport;Logic;Outport;Sum;Switch;Terminator;UnitDelay


MODELNAME: CiMappedEngineV
PATH: toolbox/vdynblks/vdynsolution/projectsrc/CI/Plant/CiMappedEngineV.slx
ANNOTATION: Copyright 2017-2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;2;14;34;1;1;4;52;2;1;1;6;13
CHECKSUM: 9F6B6C62B6FF441A8728863D9281BA01
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
BLOCK:
Accessory Load Model;Accessory Load Power;Accessory Torque;Actuators;Afr;AmbPrs;AmbTemp;BSFC;Bus Selector;CompPrsRatio;CompTempOut;Constant;Divide;EGR Valve Dynamics;Ect;EgrCoolerTempOut;EgrMassFlwRate;EgrPct;EgrVlvAreaPct;EgrVlvAreaPctCmd;EgrVlvDeltaPrs;EgrVlvInTemp;Electronic Throttle Actuator Dynamics;EngSpd;EngSpdOut;EngTrq;Engine Speed;ExhCamPhase;ExhCamPhaseCmd;ExhManGasTemp;Exhaust Cam Phaser Actuator Dynamics;FuelFlw;FuelMainSoi;FuelMainSoiCmd;Ground;Iat;InjPw;InjPwCmd;Injector Pulsewidth Dynamics;Injector Slope;Intake Cam Phaser Actuator Dynamics;Intake Manifold Flap Actuator Dynamics;IntercoolerTempOut;IntkCamPhase;IntkCamPhaseCmd;IntkPortFlw;IntkSwirlVlvPos;IntkSwirlVlvPosCmd;IntkVlvLift;IntkVlvLiftCmd;Kw to w;Lumped Torque Dynamics;Map;Mapped CI Engine;Mat;Mux;Net Torque;NormAirChrg;Product;Reference;Saturation;SpkAdv;SpkAdvCmd;SubSystem;Swirl Valve Actuator Dynamics;TP CO;TP HC;TP NOx;Terminator;ThrPosPct;ThrPosPctCmd;TrqCmd;TurbPrsRatio;TurbTempOut;TurboRackPos;TurboRackPosCmd;TurboSpd;UndHdFlwVel;VGT Actuator Dynamics;VarCompRatioPos;VarCompRatioPosCmd;VarIntkManPos;VarIntkManPosCmd;VarIntkRunLen;VarIntkRunLenCmd;Variable Compression Ratio Actuator Dynamics;Variable Intake Runner Length Actuator Dynamics;Variable Intake Valve Lift Actuator Dynamics;Wastegate Actuator Dynamics;WgAreaPct;WgAreaPctCmd;rpm to rad/s

BLOCKTYPE:
BusSelector;Constant;Gain;Ground;Inport;Lookup_n-D;Mapped CI Engine;Mux;Outport;Product;Saturate;Sum;Terminator;TransferFcn


MODELNAME: CRReferenceApplication
PATH: toolbox/vdynblks/vdynsolution/projectsrc/ConstRadius/System/CRReferenceApplication.slx
CHECKSUM: 188ED8FBAB77C959009A37FFB2E5FAE8
PRODUCT: MATLAB;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear The Ground Feedback variant subsystem is automatically enabled/disabled according to the 3D Engine settings found in the Reference Generator. Manually overriding this variant may result in initialization errors.  1) Add additional chassis Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add additional Engine Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Placeholder for introducing faults, detailed actuator behavior, interactions of other systems with a human interface such as changes in power steering and braking assistance.   1) Add additional Driveline Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Vehicle Response Driver Commands Copyright 2018-2023 The MathWorks, Inc.

BLOCK:
 Demux ; Driver; Fdbk; Gear; Ref; SFunction ; Terminator ; Vis;1-D Lookup Table;10ms Function-Call Generator;3D Engine;3D Engine Disabled;3D Engine Source;<Accel>;<Kappa>;<WhlAccel>;<xdot>;ABSCtrlForEach;ABSFlag;ABSForEachWheel;Abs;Acc to Torque Request;AccCmd;AccFdbk;Accel;AccelCmd;AccelFdbk;AccelGround;Acceleration Cmd;Active Differential Control;Add;AllParts;AxlTrq;Bang Bang ABS;Bang-bang controller;Body;Body Ptich;Body Roll;Body Yaw;Body, Suspension, Wheels;BodyX;BodyY;BodyZ;Brake;Brake Cmd;Brake Pedal;Brake Pressure Control;BrakeCmd;BrakeGround;BrkCmd;BrkCtrl;BrkFlag;BrkPrs;BrkPrsCmd;Bus Creator;Bus Element In;Bus Selector;Bus to Vector;Calculate Downshift Threshold;Calculate Upshift Threshold;Chassis Input;Chassis Output;Cntrl;CntrlRx;CntrlTx;Compare To Constant;ConcatOut;Constant;Constant Radius;Cont LPF;Controllers;Current Gear;DCM;DLC;Data Type Conversion;Dead Zone;Debounce;DecelCmd;DecelFdbk;Demux;Detect Increase;DiffPrsCmd;DiffTrqCmd;Disabled;Discrete-Time Integrator;Divide;Double Lane Change;DownReq;Driveline;Driveline Ideal Fixed Gear;Driveline Input;Driveline Output;Driver;Driver - No Clutch;Driver Commands;ECU;Enabled;Enb;Eng;EngSpd;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Input;Engine Output;Engine Tach [rpm];Env;Environment;First Order Hold;Fishhook;Five-State ABS and TCS;Flag;For Each;For Each Subsystem;Friction;From;Gain;Gear;GearCmd;GearFdbk;GearGround;GearReq;Gnd;Goto;Ground;Ground Feedback;Handwheel Angle [deg];Highbeam;ISO 15037-1:;Ideal Mapped Engine;Increasing Steer;Integrator;Internal Tire Contact Plotter;Interpreted MATLAB Function;IsNegative;Kappa;KappaEst;Lane Change;Lateral Acceleration [g];Left Signal;Linear Predictive Driver;Logical Operator;Longitudinal Driver;Lowbeam;MATLAB Function;Max;Memory;Multiple Points;Mux;Neutral;Neutral Select;No Control;None;OR;Omega;Open Loop;OperatorFdbk;Out Bus Element;PID Controller;PRNDL Controller;Paddles;Part Rotation Concatenation;Part Translation Concatenation;PartConcatenation;PassVeh14DOF;PassVeh7DOF;Passenger Vehicle;Pb;PbFdbk;PbOutput;Pedal Cluster Input;Pedal Cluster Output;Pedal Cluster and Cabin;Predictive Driver;Predictive Stanley Driver;Pref;Product;PropShftSpd;Range Limiter;Rate Transition;Rear Diff Controller;Ref;Ref ;Reference;Reference Generator;Relational Operator;Reshape;Rev Limiter Control;Reverse;Right Signal;Rotation Angles to Direction Cosine Matrix;SG Diff;Saturation;Scale;ScaleOut;Scope Type;Selector;Sensors;Signal Copy;Signal Specification;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Sine With Dwell;Sine with Dwell;Single Point;SpdThr;Speed LPF;Speed [mph];Steer;Steer, Velocity, Lat Accel;SteerCmd;SteerFdbk;SteerGround;SteerHWCmd;Steering;Steering, Transmission, Driveline and Brakes;StrWhlTrq;SubSystem;Subsystem;Subtract;Sum;Sum of Elements;Swept Sine;Switch;TCM;TCM Shift Controller;TCSCtrlForEach;TCSFlag;Terminator;Three-axis Inertial Measurement Unit;Torque Cmd;Transmission Controller;Transmission Controller PRNDL;TrqCmd;TrqCmdRevLimited;Unary Minus;Unit Conversion;UpReq;Vector Concatenate;Veh;VehFdbk;VehFdbk ;VehRef;VehSpd;Vehicle XY Plotter;Vis;Vis ;Visualization;Wheel Accel;Wheel Accel and Slip Estimator;Wheel Angle Limit * Steer Ratio;WheelDCM;WheelFrontLeft;WheelFrontLeft Pitch;WheelFrontLeft Roll;WheelFrontLeft Yaw;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRight Pitch;WheelFrontRight Roll;WheelFrontRight Yaw;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeft Pitch;WheelRearLeft Roll;WheelRearLeft Yaw;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRight Ptich;WheelRearRight Roll;WheelRearRight Yaw;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels;WhlAccel;WhlAng;WhlSlip;Wind;WindXYZ;XY View;XY View Ref;XYZ;Yaw Rate and Steer;Zend Select;axayaz;axle distance;calc;calc_down;calc_up;div0protect - poly;down_th;e;f;function;gear;in_;mu;out_;pedal;phi,theta,psi;pqr;speed;steer ratio;up_th;wheel radius;xdot;z;zero

BLOCKTYPE:
3D Engine;Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;CircularGaugeBlock;Compare To Constant;Compare To Zero;Concatenate;Constant;DataTypeConversion;DeadZone;Debounce;Demux;Detect Increase;DiscreteIntegrator;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;Double Lane Change Source;FirstOrderHold;Five-State ABS Control;Five-State TCS Control;ForEach;From;Function-Call Generator;Gain;Goto;Ground;ISO 15037-1:2006;Inport;Integrator;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;MATLABFcn;Memory;MinMax;ModelReference;Mux;Outport;PID 1dof;Predictive Driver;Product;RateTransition;Reference Generator;RelationalOperator;Reshape;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalConversion;SignalSpecification;Simplified Savitzky-Golay Differentiator;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Sine With Dwell;Slowly Increasing Steer Maneuver;Sum;Swept Sine Steer;Switch;Terminator;Terrain Source;Three-axis Inertial Measurement Unit;Tire Contact Plotter;Transmission Controller PRNDL;TriggerPort;UnaryMinus;UnitConversion;UnitDelay;Vehicle XY Plotter

BLOCKTYPE_FREQUENCY:
1;4;1;27;55;11;2;11;1;26;49;22;6;3;17;1;2;1;1;1;12;1;1;6;13;1;11;9;22;1;269;4;2;8;1;5;1;1;1;4;5;153;1;2;3;16;1;5;6;5;14;3;14;2;1;4;41;1;1;2;1;2;1;17;1;6;41;1;1;1;1;4;3;25;1;2

EXTERNALFILE_REFERENCE:
Driveline___Model_Block___PassVeh14DOF___Model_Block___PassVeh7DOF___Model_Block___SiMappedEngineV___Model_Block___


MODELNAME: DLCReferenceApplication
PATH: toolbox/vdynblks/vdynsolution/projectsrc/DblLaneChange/System/DLCReferenceApplication.slx
CHECKSUM: 7CE67905FAB91CDA8ACF924E79F5054B
PRODUCT: MATLAB;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear The Ground Feedback variant subsystem is automatically enabled/disabled according to the 3D Engine settings found in the Reference Generator. Manually overriding this variant may result in initialization errors.  1) Add additional chassis Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add additional Engine Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Placeholder for introducing faults, detailed actuator behavior, interactions of other systems with a human interface such as changes in power steering and braking assistance.   1) Add additional Driveline Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Vehicle Response Driver Commands Copyright 2018-2023 The MathWorks, Inc.

BLOCK:
 Demux ; Driver; Gear; SFunction ; Terminator ;1-D Lookup Table;10ms Function-Call Generator;3D Engine;3D Engine Disabled;3D Engine Source;<Accel>;<Kappa>;<WhlAccel>;<xdot>;ABSCtrlForEach;ABSFlag;ABSForEachWheel;Abs;Acc to Torque Request;AccCmd;AccFdbk;Accel;AccelCmd;AccelFdbk;AccelGround;Acceleration Cmd;Active Differential Control;Add;AllParts;AxlTrq;Bang Bang ABS;Bang-bang controller;Body;Body Ptich;Body Roll;Body Yaw;Body, Suspension, Wheels;BodyX;BodyY;BodyZ;Brake;Brake Cmd;Brake Pedal;Brake Pressure Control;BrakeGround;BrkCmd;BrkCtrl;BrkFlag;BrkPrs;BrkPrsCmd;Bus Creator;Bus Element In;Bus Selector;Bus to Vector;Calculate Downshift Threshold;Calculate Upshift Threshold;Chassis Input;Chassis Output;Cntrl;CntrlRx;CntrlTx;Compare To Constant;ConcatOut;Constant;Cont LPF;Controllers;Current Gear;DCM;Data Type Conversion;Dead Zone;Debounce;DecelCmd;DecelFdbk;Demux;Detect Increase;DiffPrsCmd;DiffTrqCmd;Disabled;Discrete-Time Integrator;Divide;DownReq;Driveline;Driveline Ideal Fixed Gear;Driveline Input;Driveline Output;Driver;Driver - No Clutch;Driver Commands;ECU;Enabled;Enb;Eng;EngSpd;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Input;Engine Output;Engine Tach [rpm];Entered Gate;Env;Environment;First Order Hold;Five-State ABS and TCS;Flag;For Each;For Each Subsystem;Friction;From;Gain;Gear;GearCmd;GearFdbk;GearGround;GearReq;Gnd;Goto;Grade;Ground;Ground Feedback;Handwheel Angle [deg];Highbeam;ISO 15037-1:;Ideal Mapped Engine;Integrator;Internal Tire Contact Plotter;Interpreted MATLAB Function;IsNegative;Kappa;KappaEst;Lane Change;Lane Change Reference Generator;Lateral Acceleration [g];Left Signal;Linear Predictive Driver;Logical Operator;Longitudinal Driver;Lowbeam;MATLAB Function;Max;Memory;Multiple Points;Mux;Neutral;Neutral Select;No Control;OR;Omega;Open Loop;OperatorFdbk;Out Bus Element;PID Controller;PRNDL Controller;Paddles;Part Rotation Concatenation;Part Translation Concatenation;PartConcatenation;PassVeh14DOF;PassVeh7DOF;Passenger Vehicle;Pb;PbFdbk;PbOutput;Pedal Cluster Input;Pedal Cluster Output;Pedal Cluster and Cabin;Predictive Driver;Predictive Stanley Driver;Pref;Product;PropShftSpd;Range Limiter;Rate Transition;Rear Diff Controller;Reference;Relational Operator;Reshape;Rev Limiter Control;Reverse;Right Signal;Rotation Angles to Direction Cosine Matrix;SG Diff;Saturation;Scale;ScaleOut;Selector;Sensors;Signal Copy;Signal Specification;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Single Point;SpdThr;Speed LPF;Speed [mph];Steer;Steer, Velocity, Lat Accel;SteerCmd;SteerFdbk;SteerGround;SteerHWCmd;Steering;Steering, Transmission, Driveline and Brakes;StrWhlTrq;SubSystem;Subsystem;Subtract;Sum;Sum of Elements;Switch;TCM;TCM Shift Controller;TCSCtrlForEach;TCSFlag;Terminator;Three-axis Inertial Measurement Unit;Torque Cmd;Transmission Controller;Transmission Controller PRNDL;TrqCmd;TrqCmdRevLimited;Unary Minus;Unit Conversion;UpReq;Vector Concatenate;Veh;VehFdbk;VehRef;VehSpd;Vehicle XY Plotter;Visualization;Wheel Accel;Wheel Accel and Slip Estimator;WheelDCM;WheelFrontLeft;WheelFrontLeft Pitch;WheelFrontLeft Roll;WheelFrontLeft Yaw;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRight Pitch;WheelFrontRight Roll;WheelFrontRight Yaw;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeft Pitch;WheelRearLeft Roll;WheelRearLeft Yaw;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRight Ptich;WheelRearRight Roll;WheelRearRight Yaw;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels;WhlAccel;WhlAng;WhlSlip;Wind;WindXYZ;Z;Zend Select;axayaz;axle distance;calc;calc_down;calc_up;div0protect - poly;down_th;e;f;function;gear;in_;mu;out_;pedal;phi,theta,psi;pqr;speed;steer ratio;up_th;wheel radius;xdot;z;zero

BLOCKTYPE:
3D Engine;Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;CircularGaugeBlock;Compare To Constant;Compare To Zero;Concatenate;Constant;DataTypeConversion;DeadZone;Debounce;Demux;Detect Increase;DiscreteIntegrator;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;Double Lane Change Source;Driver Commands;FirstOrderHold;Five-State ABS Control;Five-State TCS Control;ForEach;From;Function-Call Generator;Gain;Goto;Ground;ISO 15037-1:2006;Inport;Integrator;LampBlock;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;MATLABFcn;Memory;MinMax;ModelReference;Mux;Outport;PID 1dof;Predictive Driver;Product;RateTransition;RelationalOperator;Reshape;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalConversion;SignalSpecification;Simplified Savitzky-Golay Differentiator;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Sum;Switch;Terminator;Terrain Source;Three-axis Inertial Measurement Unit;Tire Contact Plotter;Transmission Controller PRNDL;TriggerPort;UnaryMinus;UnitConversion;UnitDelay;Vehicle XY Plotter

BLOCKTYPE_FREQUENCY:
1;4;1;22;48;7;2;11;1;26;54;22;7;3;17;1;2;1;1;1;1;12;1;1;6;13;1;10;9;9;1;249;4;1;2;8;1;5;1;3;1;4;8;128;1;2;3;14;5;6;5;14;2;14;2;1;3;41;1;1;2;1;17;6;38;1;1;1;1;4;3;27;1;1


MODELNAME: Driveline
PATH: toolbox/vdynblks/vdynsolution/projectsrc/Driveline/Plant/Driveline.slx
ANNOTATION: Copyright 2018-2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;7;2;1;10;1;8;1;28;1;3;1;1;24;1;1;13;13;1
CHECKSUM: B84B1F77755F7C5D1AE58D5E931E7071
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
BLOCK:
Active Differential;All Wheel Drive;AxlTrq;Brake Hydraulics;BrkPrs;BrkPrsCmd;Bus Selector;Dead Zone;Demux;DiffPrsCmd;Driveline Model;DrvShfTrq;EngSpd;EngTrq;Front Bias;Front Wheel Drive;Gain;Gear;GearCmd;Ground;Ideal;Ideal Fixed Gear Transmission;Info;Kinematic Steering;Limited Slip Differential;Mux;Omega;Open Differential;Product;Prop Shaft;PropShaftSpd;PropShftSpd;Rear Bias;Rear Wheel Drive;Rear Wheel Drive Active Differential;Reference;Selector;SteerHWCmd;StrWhlTrq;SubSystem;Terminator;Torsional Compliance;Transfer Case;Transmission;Valve;Vector Concatenate;WhlAng

BLOCKTYPE:
Active Slip Differential;BusSelector;Concatenate;Constant;DeadZone;Demux;Gain;Ground;Ideal Fixed Gear Transmission;Inport;Kinematic Steering;Limited Slip Differential;Mux;Open Differential;Outport;Product;Selector;Terminator;Torsional Compliance;Transfer Case


MODELNAME: ISReferenceApplication
PATH: toolbox/vdynblks/vdynsolution/projectsrc/IncreasingSteer/System/ISReferenceApplication.slx
CHECKSUM: DF8E8F031A9DC71461F63E81EAAB40A2
PRODUCT: MATLAB;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear The Ground Feedback variant subsystem is automatically enabled/disabled according to the 3D Engine settings found in the Reference Generator. Manually overriding this variant may result in initialization errors.  1) Add additional chassis Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add additional Engine Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Placeholder for introducing faults, detailed actuator behavior, interactions of other systems with a human interface such as changes in power steering and braking assistance.   1) Add additional Driveline Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. dt3D  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Driver Commands Vehicle Response Copyright 2018-2023 The MathWorks, Inc.

BLOCK:
 Demux ; Driver; Gear; SFunction ; Terminator ;1-D Lookup Table;10ms Function-Call Generator;3D Engine;3D Engine Disabled;3D Engine Source;<Accel>;<Kappa>;<WhlAccel>;<xdot>;ABSCtrlForEach;ABSFlag;ABSForEachWheel;Abs;Acc to Torque Request;AccCmd;AccFdbk;Accel;AccelCmd;AccelFdbk;AccelGround;Acceleration Cmd;Active Differential Control;Add;AllParts;AxlTrq;Bang Bang ABS;Bang-bang controller;Body;Body Ptich;Body Roll;Body Yaw;Body, Suspension, Wheels;BodyX;BodyY;BodyZ;Brake;Brake Cmd;Brake Pedal;Brake Pressure Control;BrakeCmd;BrakeGround;BrkCmd;BrkCtrl;BrkFlag;BrkPrs;BrkPrsCmd;Bus Creator;Bus Element In;Bus Selector;Bus to Vector;Calculate Downshift Threshold;Calculate Upshift Threshold;Chassis Input;Chassis Output;Cntrl;CntrlRx;CntrlTx;Compare To Constant;ConcatOut;Constant;Cont LPF;Controllers;Current Gear;DCM;Data Type Conversion;Dead Zone;Debounce;DecelCmd;DecelFdbk;Demux;Detect Increase;DiffPrsCmd;DiffTrqCmd;Disabled;Discrete-Time Integrator;Divide;DownReq;Driveline;Driveline Ideal Fixed Gear;Driveline Input;Driveline Output;Driver;Driver - No Clutch;Driver Commands;ECU;Enabled;Enb;Eng;EngSpd;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Input;Engine Output;Engine Tach [rpm];Env;Environment;First Order Hold;Five-State ABS and TCS;Flag;For Each;For Each Subsystem;Friction;From;Gain;Gear;GearCmd;GearFdbk;GearGround;GearReq;Gnd;Goto;Ground;Ground Feedback;Handwheel Angle [deg];Highbeam;ISO 15037-1:;Ideal Mapped Engine;Integrator;Internal Tire Contact Plotter;Interpreted MATLAB Function;IsNegative;Kappa;KappaEst;Lateral Acceleration [g];Left Signal;Linear Predictive Driver;Logical Operator;Longitudinal Driver;Lowbeam;MATLAB Function;Max;Multiple Points;Mux;Neutral;Neutral Select;No Control;OR;Omega;Open Loop;OperatorFdbk;Out Bus Element;PID Controller;PRNDL Controller;Paddles;Part Rotation Concatenation;Part Translation Concatenation;PartConcatenation;PassVeh14DOF;PassVeh7DOF;Passenger Vehicle;Pb;PbFdbk;PbOutput;Pedal Cluster Input;Pedal Cluster Output;Pedal Cluster and Cabin;Predictive Driver;Pref;Product;PropShftSpd;Range Limiter;Rate Transition;Rear Diff Controller;Reference;Relational Operator;Reshape;Rev Limiter Control;Reverse;Right Signal;Rotation Angles to Direction Cosine Matrix;SG Diff;Saturation;Scale;ScaleOut;Selector;Sensors;Signal Specification;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Single Point;Slowly Increasing Steer;SpdThr;Speed LPF;Speed [mph];Start Steering Command;Steer;Steer, Velocity, Lat Accel;SteerCmd;SteerFdbk;SteerGround;SteerHWCmd;Steering;Steering, Transmission, Driveline and Brakes;StrWhlTrq;SubSystem;Subsystem;Subtract;Sum;Sum of Elements;Switch;TCM;TCM Shift Controller;TCSCtrlForEach;TCSFlag;Terminator;Three-axis Inertial Measurement Unit;Torque Cmd;Transmission Controller;Transmission Controller PRNDL;TrqCmd;TrqCmdRevLimited;Unary Minus;Unit Conversion;UpReq;Vector Concatenate;Veh;VehFdbk;VehRef;VehSpd;Vehicle XY Plotter;Visualization;Wheel Accel;Wheel Accel and Slip Estimator;WheelDCM;WheelFrontLeft;WheelFrontLeft Pitch;WheelFrontLeft Roll;WheelFrontLeft Yaw;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRight Pitch;WheelFrontRight Roll;WheelFrontRight Yaw;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeft Pitch;WheelRearLeft Roll;WheelRearLeft Yaw;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRight Ptich;WheelRearRight Roll;WheelRearRight Yaw;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels;WhlAccel;WhlAng;WhlSlip;Wind;WindXYZ;Yaw Rate and Steer;Zend Select;axayaz;axle distance;calc;calc_down;calc_up;div0protect - poly;down_th;e;f;function;gear;in_;mu;out_;pedal;phi,theta,psi;pqr;speed;steer ratio;up_th;wheel radius;xdot;z;zero

BLOCKTYPE:
3D Engine;Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;CircularGaugeBlock;Compare To Constant;Compare To Zero;Concatenate;Constant;DataTypeConversion;DeadZone;Debounce;Demux;Detect Increase;DiscreteIntegrator;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;FirstOrderHold;Five-State ABS Control;Five-State TCS Control;ForEach;From;Function-Call Generator;Gain;Goto;Ground;ISO 15037-1:2006;Inport;Integrator;LampBlock;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;MATLABFcn;MinMax;ModelReference;Mux;Outport;PID 1dof;Predictive Driver;Product;RateTransition;RelationalOperator;Reshape;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalSpecification;Simplified Savitzky-Golay Differentiator;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Slowly Increasing Steer Maneuver;Sum;Switch;Terminator;Terrain Source;Three-axis Inertial Measurement Unit;Tire Contact Plotter;Transmission Controller PRNDL;TriggerPort;UnaryMinus;UnitConversion;UnitDelay;Vehicle XY Plotter

BLOCKTYPE_FREQUENCY:
1;4;1;21;44;7;2;11;1;26;49;22;6;3;17;1;2;1;1;12;1;1;6;13;1;10;9;8;1;245;4;1;2;8;1;5;1;1;4;2;127;1;1;3;14;5;6;5;14;2;14;2;1;42;1;1;2;1;1;17;6;37;1;1;1;1;4;3;28;1;1


MODELNAME: KandCVirtualTestLab
PATH: toolbox/vdynblks/vdynsolution/projectsrc/KandCVirtualTestLab/System/KandCVirtualTestLab.slx
CHECKSUM: F44C7E6B3F9D9102E8D32BC2544B7574
PRODUCT: MATLAB;Simscape Multibody;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant 1) Only subsystems can be added as variant choices at this level 2) Blocks cannot be connected at this level as connectivity is automatically determined at simulation, based on the active variant  Virtual Kinematics and Compliance Test Laboratory Copyright 2020-2024 The MathWorks, Inc.

BLOCK:
1 Rev;2 Rev;A;Actuator LF;Actuator LR;Actuator RF;Actuator RR;Ang Velocity Vector;AxS;Axle;Axle Coordinate Sensor;B;BS;Base;Base to Spindle Sensor;Body;Body CG Sensor;Body Clamp;Body Geometry;Body Inertia;Bolt_1_RIGID;Bus Creator;Bus Selector;Bushing Joint;CG;CPIForce;CPIMoment;Camber;Cast;Clock;Combined Slip Wheel STI;Compare To Constant;Conn;Constant;Cyl_Base_1_RIGID;Cyl_Base_2_RIGID;Cylindrical Bolt Cyl;Cylindrical Cyl Low Up;Demux;Derivative;Direction Cosine Matrix to Rotation Angles;Displacement Vector;DoE;DoE Chirp Test;Enable;External Force and Torque;F;Flat Road;From;Gain;Goto;Ground;H;Hub xyz;ISO 8855 Global Sensors;ISO 8855 Platform Forces and Torques;ISO 8855 Platform to Spindle Sensor LF;ISO 8855 Platform to Spindle Sensor LR;ISO 8855 Platform to Spindle Sensor RF;ISO 8855 Platform to Spindle Sensor RR;Independent Suspension - Mapped;Inertia;Integrator;K & C Actuator;LArm Base;LF;LR;Lab;LabCtrl;Left Front Camber Sign;Left Front Spindle World Coordinates;Left Front Steer Sign;Left Rear Camber Sign;Left Rear Steer Sign;Left Tire Patch World Coordinates;Lower_Arm_1_RIGID;Lower_Base_1_RIGID;Lower_Cyl_1_RIGID;Matrix Multiply;Mechanism Configuration;Mux;NOT;Omega;PS;PS-Simulink Converter;Patch xyz;Physical Actuators;Piston;Platform;Platform F;Platform T;Platform to Spindle Sensor;Prismatic Joint;Prismatic Rack;Product;RF;RR;Ra;RaH;Rack;Rack Housing;Reference;ReferenceFrame;Relational Operator;Reshape;Revolute Cyl Up Base;Revolute Cyl Up Base ;Revolute LArm Base;Revolute LArm BaseF;Revolute LArm BaseR;Revolute LArm Sp;Revolute SpinLF;Revolute SpinLR;Revolute SpinRF;Revolute SpinRR;Revolute UArm Base;Revolute UArm BaseF;Revolute UArm BaseR;Right Front Camber Sign;Right Front Steer Sign;Right Rear Camber Sign;Right Rear Spindle World Coordinates;Right Rear Steer Sign;Right Spindle World Coordinates;Right Tire Patch World Coordinates;Rigid Transform;Rim;Road Friction;S;S Rack;STI Tire Left;STI Tire Right;Scope;Selector;Sensing;Signal Actuators;Simscape Bus;Simscape Multibody Vehicle;Simscape Multibody Wheel + Tire;Simulink-PS Converter;Sin;Solid;Solver Configuration;Sph TiRa;Sph TiSp;Spherical LArm Sp;Spherical Spindle TiL;Spherical Spindle TiR;Spherical TiL Rack;Spherical TiR Rack;Spherical UArm Sp;Spindle_1_RIGID;Spindle_rear_1_RIGID;Steering;Steering Input;Stop Simulation;SubSystem;Subsystem;Sum;Susp LF;Susp LF H;Susp LF S;Susp LR;Susp LR H;Susp LR S;Susp RF;Susp RF H;Susp RF S;Susp RR;Susp RR H;Susp RR S;T;Terminator;Test Control;Test System;TiL;TiR;Tie Rod;Tie RodL;Tie RodR;Tire;Tire FB;Tire Forces;Tire Moments;To Wksp Arm Sensing;Transform;Transform (F);Transform Axle;Transform Base;Transform Base LAFCtr;Transform Base LARCtr;Transform Base UAFCtr;Transform Base UARCtr;Transform Body Geometry;Transform Camera Frame;Transform Cyl Up Base;Transform Geometry;Transform Hub;Transform LAFCtr;Transform LARCtr;Transform LowerBase;Transform Piston;Transform Platform;Transform RaHoCtrB;Transform RaHoCtrF;Transform Rack Housing;Transform RackCtr;Transform RackHous;Transform Sensor-LocalBodyCS;Transform Sensor-WorldCS;Transform Spin Axis;Transform SuspLF;Transform SuspLR;Transform TieRod;Transform TieRodCtr;Transform TieRodF;Transform UAFCtr;Transform UARCtr;Transform UpperBase;Trigonometric Function;UArm Base;Upper_Arm_1_RIGID;Upper_Base_1_RIGID;Upper_Cyl_1_RIGID;VDBS Vehicle;Variant Subsystem;Veh;VehCG;VehPhys;Vehicle;Wheel and Actuator LF;Wheel and Actuator LR;Wheel and Actuator RF;Wheel and Actuator RR;WheelBase Sensor-World;With Wheels;Without Wheels;World Clamp;World Frame;dx;dy;dz;efreq;h;handwheel rad to mm rack;sfreq;simtime;swa;time;wx;wxyz;wy;wz;z;z-position;zamp

BLOCKTYPE:
Brick Solid;BusCreator;BusSelector;Bushing Joint;Clock;Combined Slip Wheel STI;Compare Mapped and Simscape Suspension Performance;Compare To Constant;Constant;Create Mapped Suspension from Spreadsheet;Cylindrical Joint;Cylindrical Solid;DCM2Ang;DataTypeConversion;Demux;Derivative;EnablePort;External Force and Torque;File Solid;From;Gain;Generate a Mapped Suspension calibration;Goto;Ground;Inport;Integrator;Logic;Mechanism Configuration;Mux;Outport;PMIOPort;PS-Simulink Converter;Prismatic Joint;Product;Reference Frame;RelationalOperator;Reshape;Revolute Joint;Rigid Transform;Scope;Selector;SimscapeBus;Simulink-PS Converter;Solver Configuration;Spherical Joint;Spherical Solid;Stop;Sum;Terminator;ToWorkspace;Transform Sensor;Trigonometry;Vehicle suspension;World Frame

BLOCKTYPE_FREQUENCY:
5;2;16;4;3;4;1;3;32;1;8;28;10;2;45;1;1;10;45;24;65;1;24;10;84;2;2;2;42;38;441;184;11;23;36;1;4;34;216;3;21;2;29;2;10;4;1;29;189;24;30;9;1;20


MODELNAME: MotoLongBTReferenceApplication
CHECKSUM: B88230FC02AFF5B92982BE3499139740
PRODUCT: MATLAB;Simscape Multibody;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
PATH:
toolbox/vdynblks/vdynsolution/projectsrc/MotoLongBrakingTest/System/MotoLongBTReferenceApplication.slx

ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Placeholder for introducing faults, detailed actuator behavior, interactions of other systems with a human interface such as changes in power steering and braking assistance.   1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Vehicle Response Driver Commands Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
; Demux ; Frame_CP; Frame_CPRr; Gear; SFunction ; Terminator ;.5.*A.*Pabs./R./T;1-D Lookup Table;10ms Function-Call Generator;3D Engine;3D Engine Disabled;6-DOF Joint;6dof;<Accel>;<Kappa>;<VCPr>;<WhlAccel>;<adf>;<amu>;<amur>;<axCPRr>;<phi>;<pzFr>;<thetasteer>;<xdot>;A;A,V,P;A,V,P_FrmAng;A,V,P_Roll;A,V,P_WhlRoll;A,V,P_X;A,V,P_Y;A,V,P_Yaw;A,V,P_Z;A,V,P_str;ABSCtrlForEach;ABSFlag;ABSForEachWheel;Abs;AccCmd;AccFdbk;Accel;AccelCmd;Acceleration Cmd;Active Differential Control;Add;Add_Torque;Aero;AeroFrame;AeroFrame_Frm;Alpha;Ancillary;Ancillary_sub;AngAWhlR;AngAWhlR.;AngStr;AngVSprtR;Angle Constraint;Antilock Brake System;ArmRr;ArmRrAng;ArmRrAngA_comp;ArmRrVx;ArmRrVy;ArmRrVz;AxlTrq;B;Bang Bang ABS;Bang-bang controller;BdyFrm;Bias;Body Axis Vel;Body Axis Wind;Body, Suspension, Wheels;Brake;Brake Cmd;Brake Hydraulics;Brake Pedal;Brake Pressure Control;Brake model;Brakes;BrkCmd;BrkCtrl;BrkFlag;BrkPrs;BrkPrsCmd;BrkPrsFr;BrkPrsRr;BrkPrsf;BrkPrsr;BrkTrq;Bus Creator;Bus Element In;Bus Selector;Bus to Vector;CG;CGCoord.;CG_ArmRr;CG_FrkLw;CG_FrkUp;CG_Frm;CG_Rdr;CG_Solid;CG_WhlFr;CG_WhlRr;CHASSIS;CP;CP2HubRr;CPRr;CPRr (dofXZ);CPSensor;Calc. part Vertical load & SideSlipAngle;Calculate Downshift Threshold;Calculate Upshift Threshold;Camber stiffness;Camera;Camera_W;Cartesian Joint;Cg;Chain reaction;ChangeAxis X_-pi/;Chassis;Chassis Input;Chassis Output;Chassis&Tires;Circuit;Clutch;Cntrl;CntrlRx;CntrlTx;CofGCoord.;CofGCoord.Frm;CofGCoord.Rdr;Combined Slip Wheel CPI;Compare To Constant;Compare To Zero;Connection Label;Constant;Contact model;Controllers;Cornering stiffness;Course shape;CpX;CpZ;Crm;Cs;Current Gear;Cylindrical Solid;Cym;Data Type Conversion;Dead Zone;Debounce;DecelCmd;DecelFdbk;Demux;Detect Increase;DiffPrsCmd;DiffTrqCmd;Discrete Derivative;Discrete-Time Integrator;Display;Divide;DownReq;Drag Force;Driveline;Driveline Input;Driveline Output;Driver;Driver - No Clutch;Driveshaft Compliance;Driving/Braking stiffness;Dummy mass;ECU;Eng;EngSpd;EngTmp Signal Spec;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Input;Engine Output;Engine Tach [rpm];Env;Environment;Equal Front Rear Bias;Ext.F_T;ExtForceFrame;External;External FM;External Force and Torque;F;FCpR;FCpR.;FFork;FMExt;FRdrdef;FSusf;FSusfin;FSuspension;Fd;FdExt;Fdrag;Fext;Fext_BF;Fg;Fg (MainFrame);Fgx;Fgz;First Order Hold;Five-State ABS for Motorcycle;Flag;For Each;For Each Subsystem;Forces;Fork;Fork Rotation;Fork Translation;Fork dof;Fork len;Fpre;FrSus F&M;Frame;Friction Model;Friction model;Frk;FrkFz;FrkFz_comp;FrkLw;FrkLwVx;FrkLwVy;FrkLwVz;FrkUp;FrkUpVx;FrkUpVy;FrkUpVz;Frm;FrmAng;FrmAngA_comp;FrmRotInfo;FrmVx;FrmVy;FrmVz;From;Front;Front Bias;Front tire (VDBS&Simscape Multibody);Front tire CPI;FrontTireRadius [m];Fx;Fxext;Fxf;Fxin;Fxr;Fy;Fyin;Fz;Fzext;Fzf;Fzin;Fzr;Gain;Gear;GearCmd;GearFdbk;GearReq;Genrl;Geom;Geom sensor;GeomInfo;Goto;Grade;Graphic;Gravity;Ground;Ground Feedback;Grvty;Hand Levers and Pedals;Highbeam;Hub;Hub2Pivo;HubFr;HubFr_sensor;HubJoint;HubJointFr_B;HubJointFr_F;HubJointRr_B;HubJointRr_F;HubJoint_B;HubJoint_F;HubRr;Ideal Fixed Gear Transmission;InPlane vertical;InertFrm;Inertial;Inertial Frame;Info;Info In;Info_CP;Info_sub;Initial frame pitch;Inplane vertical;Integrator;JointHubRr;Kappa;KappaEst;LB;LPF;Left Signal;Lfrk;LfrkA_comp;Linear;Linear Front tire (Simscape Multibody);Linear Rear tire (Simscape Multibody);Local;LocalGravity;Logical Operator;Longitudinal;Longitudinal Acceleration [g];Longitudinal Rider;Lowbeam;M;MATLAB Function;MBrk;MBrkR;MBrkR.;MBrkin;MDrvArmR;MDrvArmR.;MDrvFrm;MDrvFrm.;MDrvSprtR;MDrvSprtR.;MDshaft;MRdrdef;MSteer;MStrDmp;MStrDmpin;MStrExt;MSusr;MSusrin;MW Brake;MWh;MWhFr;MWhf;MWhr;Mapped;Math Function;Matrix Concatenate;Max;Mbrk;Mcr;Mcrf;Md;MdExt;Mdrag;Mdragy;Mechanism Configuration;Mext;Minus;Moments;Motorcycle Body Longitudinal In-Plane;Motorcycle Body Longitudinal In-Plane (Simscape Multibody);Motorcycle Chain;Motorcycle Vehicle;Mux;Mx;Mxin;My;MyBrk;Myb;Myext;Myin;Mz;Mzin;Neutral;Neutral Select;No Control;None;OR;Omega;Omegadot;Open Loop;OperatorFdbk;Origin;Origin&Env;Out Bus Element;P;PID Controller;PRNDL Controller;PS-Simulink Converter;Paddles;Pb;PbOutput;Pedal Cluster Input;Pedal Cluster Output;Performance;Pitch dof;Pivo2HP;PosInfo;Pref;Pref_dot;Prismatic Joint;Product;Pythagorean theorem;Q,A,V,P_Rdr;Quaternions to Rotation Angles;R;Range Limiter;Rate Transition;Rdr;RdrCG_Solid;RdrConnType;RdrVx;RdrVy;RdrVz;Re;Reaction Torque;Rear;Rear Bias;Rear Diff Controller;Rear tire (VDBS&Simscape Multibody);Rear tire CPI;RearArm;Rectangular Joint;Ref;RefFdbk;Reference;Relational Operator;Rev;Rev Limiter Control;Revolute Joint;Rider;Rider position info;Right;Right Signal;Rigid;Rigid Transform;Road Vel.;Road velocity;RoadVelocity;Roll;Roll dof;Roll limitation;Roll limited;Roll locked;Roll no limit;Rot.Velocity;RotInfo;Rotation;Rotation Angles to Direction Cosine Matrix;RrSus F&M;SAE origin;SSMB;Saturation;Sbb;Sbd;ScaleFactrs;Scope;Selector;Sensor;Sensor_ArmRr;Sensor_FrkLw;Sensor_FrkUp;Sensor_Frm;Sensor_HubFr;Sensor_HubRr;Sensor_Rdr;Sensor_WhlFr;Sensor_WhlRr;Sensor_origin;Sensors;Shk;ShkMy;ShkMy_comp;SideSlipAngle [rad];Sign;Signal Copy;Signal Specification;Signal routine;Signal routing;Simple 1.0L V2 Naturally Aspirated Motorcycle Engine;Simple damper;Simple spring and damper;Simscape;Simscape Multibody Lateral;Simscape Multibody Longitudinal;Simscape Multibody Rim&Wheel;Simscape Multibody model;Simulation 3D Motorcycle;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation Control;Simulink-PS Converter;Slip Ratio _ Braking;Slip Ratio _ Driving;SlipAngle;SlipRatio;Solver Configuration;SpdThr;Speed LPF;Speed [mph];Spherical Solid;Spline;Spool;SprktGearRatio (SprktRrR/SprktFrR);Sqrt;Standard preset;Standard preset OLD;Steer;Steer Angle [deg];Steer dof;Steer locked;SteerAng;SteerCmd;SteerFdbk;Steering;Steering damper;Steering, Transmission, Driveline and Brakes;Stop Simulation;Str dof;Str limitation;Str limited;Str no limit;StrAngV;StrDmpC;StrRotInfo;StrWhlTrq;Straight Maneuver Reference Generator;SubSystem;Subsystem;Subsystem Info Busses;Subtract;Sum;Sum of Elements;Susp;Suspension F&M;Switch;Switch flag;T;TCM;TCM Shift Controller;TSuspension;Tanh;TauBD;TauShock;Temp;TempConstant;Terminator;Tfmaxk;Tfmaxs;ThetaArmR;ThetaArmR.;ThetaFrm;ThetaFrm.;Three-axis Inertial Measurement Unit;Tin;Tire radius;TireFdbk;TireFrame;Tire_Rim_wth_transient;Torque Cmd;Tout;Transfer Fcn;Transform Sensor;Translation;Transmission;Transmission Controller;Transmission Controller PRNDL;Transpose;Trigonometric Function;TrqCmd;TrqCmdRevLimited;Twist2Acc;Twist2Torque;Two Wheels Chain Driven;Two-Way Connection;UE4orig2HubFr;UE4orig2HubRr;Unary Minus;Unit Conversion;UpReq;VB;VDBS;Valve;Vector Concatenate;Veh;VehFdbk;VehRef;VehSpd;Velocities;VerticalFrame;Visualization;Volume;Vx limitation;Vx limited;Vx no limit;VxVz;Vx_l;Vx_vf;Vy_vf;Vz_l;Vz_vf;WVFrame_ArmRr;WVFrame_FrkLw;WVFrame_FrkUp;WVFrame_Frm;WVFrame_Rdr;WVFrame_WhlFr;WVFrame_WhlRr;Weld Joint;Wheel Accel;Wheel Accel and Slip Estimator;Wheel Module;Wheel Module with Braking;Wheel Rotations;Wheels;WheelsSignal;Whl;WhlAccel;WhlCpVPsi;WhlCpX;WhlCpY;WhlCpZ;WhlFr;WhlFrCpAx_comp;WhlFrCpAz_comp;WhlFrCpPz_comp;WhlFrCpX;WhlFrCpY;WhlFrCpZ;WhlFrVx;WhlFrVy;WhlFrVz;WhlHubFr;WhlHubFr_B;WhlHubFr_F;WhlHubRr;WhlHubRr_B;WhlHubRr_F;WhlRr;WhlRrCpAx_comp;WhlRrCpAz_comp;WhlRrCpX;WhlRrCpY;WhlRrCpZ;WhlRrVx;WhlRrVy;WhlRrVz;WhlSlip;Wind;WindXYZ;World Frame;World vertical;World vertical frame;World vertical frame Frm;World vertical frame Rdr;X;X+pi;XYZ;XYZ dof;X_-pi/;X_pi/;Y;Y locked;Y+Grade;YAW;Y_-pi/;Y_o;Y_pi/;Yaw;Yaw Rate, Brake Pressure, Velocity, Accel;Yaw dof;Yaw locked;Zend Select;a;adjust;apply forces and moments;ax;axCPFr;axayaz;axle distance;ay;az;azCPFr;azCPRr;b;base;calc;calc_down;calc_up;cam;cam Frame;centripetal;contact decision;delta;df;div0protect - poly;dofPitch;down_th;e;f;fork;fork (dofPrism);fork locked;ft;function;gear;in_;inclination angle [rad];latOff;longOff;mass;mass_ArmRr;mass_FrkLw;mass_FrkUp;mass_Frm;mass_array;none;offset;omega;omegadot;origin;originX_w;originZ_w;out_;p;pdf;pedal;phi;phi theta psi;pivo;pivo (dofPitch);pivo locked;pivo2UE4orig_trans;pivo2world_rot;pos;posFw_l;posOrigin_w;posRw_l;posX_fw_l;posX_rw_l;posZ_fw_l;posZ_rw_l;pqr;psi;px;py;pz;q;r;rev;rho;rhoz;road_surface;road_surface_grid;rotation;rx;ry;rz;setSAE;speed;spline;sqrt(X^2+Y^2);steer ratio;t;tExt;target;theta;thetadot;thetafrm;thetara;transform to body axes;tt;up_th;v;vel;vel.;vertOff ;vx;vy;vz;w;wheel radius;wxR;x;x_-pi/;x_pi/;xddot;xdot;xyz;y;yddot;ydot;z;zddot;zdot;zero

BLOCKTYPE:
3D Engine;6-DOF Joint;Abs;Ang2DCM;Angle Constraint;Bias;Brick Solid;BusCreator;BusSelector;BusToVector;Cartesian Joint;CircularGaugeBlock;Combined Slip Wheel CPI;Compare To Constant;Compare To Zero;Concatenate;ConnectionLabel;Constant;CrossProduct;Cylindrical Solid;DataTypeConversion;DeadZone;Debounce;Demux;Detect Increase;Discrete Derivative;DiscreteIntegrator;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;Display;External Force and Torque;File Solid;FirstOrderHold;Five-State ABS Control;ForEach;From;Function-Call Generator;Gain;Goto;Graphic;Ground;Ideal Fixed Gear Transmission;Inport;Integrator;LampBlock;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;Math;Mechanism Configuration;MinMax;Motorcycle Body Longitudinal In-Plane;Motorcycle Body Out-of-Plane without suspensions;Motorcycle Chain;Mux;Outport;PID 1dof;PMIOPort;PS-Simulink Converter;Prismatic Joint;Product;Quat2Ang;RateTransition;Rectangular Joint;RelationalOperator;Revolute Joint;Rigid Transform;Rotation;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalConversion;SignalSpecification;Signum;Simple Engine;Simulation 3D Motorcycle;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulink-PS Converter;Solver Configuration;Spherical Solid;Spline;Sqrt;Stop;Straight Maneuver Source;Sum;Switch;Terminator;Three-axis Inertial Measurement Unit;Torsional Compliance;TransferFcn;Transform Sensor;Transmission Controller PRNDL;TriggerPort;Trigonometry;TwoWayConnection;UnaryMinus;UnitConversion;UnitDelay;Vector Transformation;Weld Joint;Wheel Module with Braking;World Frame

BLOCKTYPE_FREQUENCY:
1;1;10;3;16;12;3;244;130;5;1;2;4;10;1;24;19;172;1;4;7;4;3;111;1;2;2;1;1;1;20;2;7;1;11;106;1;72;63;48;72;1;837;7;1;2;10;1;16;11;2;1;1;1;1;109;708;1;316;215;2;73;1;10;2;5;41;155;3;5;11;2;46;2;1;1;221;10;1;1;1;1;37;2;22;2;7;3;1;115;23;71;1;1;6;40;1;4;20;2;65;11;1;3;1;4;45


MODELNAME: PassVeh14DOF
PATH: toolbox/vdynblks/vdynsolution/projectsrc/PassVeh14DOF/Plant/PassVeh14DOF.slx
BLOCKTYPE_FREQUENCY: 4;5;38;179;2;5;70;34;1;8;1;5;3;8;3;6;291;6;5;20;154;2;13;115;2;1;169;15;1;20;113;6;2;1;1;8
CHECKSUM: EE1E56784E53BA79F475881A1961F19D
PRODUCT: MATLAB;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Copyright 2017-2023 The MathWorks, Inc.

BLOCK:
; Demux ; SFunction ; Terminator ; Wheels;3DOF;6DOF;<Alpha>;<M>;<Mz>;<Re>;<z>;<zdot>;Abs;Add;AngVel;AxlTrq;Axle;Axle Torque;AxleTrq;Brake;Brake Press;Brake Pressure;Brake Pressure ;BrkPrs;Bus Creator;Bus Element Out;Bus Selector;Bus to Vector;Bushings;Calculate dynamic track width from lateral wheel center displacement change;Camber;Camber ;Camber Angle;Combined Slip Wheel 2DOF;Constant;Cont LPF;Cross Product;DCM;Demux;Divide;Double Wishbone Suspension;DriveTorque;DriveTorque ;Dugoff Tires Vector;Dugoff Wheel 2DOF;Estimated Unsprung Mass Orientation;Fext;Fiala Tire;Fiala Tires;Fiala Tires Vector;For Each;Forces;Friction;FrntAxlF;From;Front;Front Left select;Front Right select;Front Track;Front Track Calculation;Fs;FsB;Fx;Fy;Fz;FzSusp;FzSusp ;Gain;GemoXYZIn;GeomXYZ;Gnd;Gnd ;Goto;Ground;Ground Input;Ground Level;In;Independent K and C Suspension;Independent Mapped Front Suspension Mapped Solid Axle Rear Suspension;Independent Suspension - Mapped;Independent Suspension – Double Wishbone;Inertial Frame CG to Axle Offset;Inertial to Body;Kappa;Kinematics and Compliance Independent Suspension;M;MF Tires;MF Tires Vector;MacPherson Front Suspension Solid Axle Rear Suspension;MacPherson Suspension;Mapped Suspension;Math Function;Matrix Concatenate;Ms;MsB;Mux;Mx;My;Mz;Omega;Out;P;Permute Dimensions;Press;Press ;Pressure;Product;Re;Rear Left select;Rear Right select;Rear Track;Rear Track Calculation;RearAxlF;Reference;Reshape;Rotation Angles to Direction Cosine Matrix;Saturation;Selector;Sign;Signal Specification;Solid Axle Suspension - Coil Spring;Solid Axle Suspension - Mapped;Steer;Steer Rate Adapter;SteerRates;Steering;Steering Adapter;StrgAng;SubSystem;Subtract;Sum;Susp2Body;SuspAng;SuspFrame;SuspWhlPz;SuspWhlVz;Suspension;Suspension Routing;Suspension to Chasiss Transforms;T;Terminator;Tire2Veh;Tires;Transpose;Unary Minus;Unsprung Masses;VDBS;Variant Subsystem;Vector Concatenate;Veh;Veh2Tire;VehAng;VehFdbk;VehSusp;VehVbody;VehVel;Vehicle;Vehicle Adapter;Vehicle Body 3DOF Dual Track;Vehicle Body 6DOF;VelVeh;Vertical;Vx;Vx ;Vy;Vy ;Wheel;Wheel Adapter;Wheel Angles;Wheel Routing;Wheel to Body Transform;WheelAngles;Wheels;Wheels and Tires;Wheels2Susp;WhlAng;WhlCmb;WhlFx;WhlFy;Wind;WindXYZ;alpha;angleIn;angles;camber;dWhlY;dWhlZ;independent Suspensions - MacPherson;kappa;lambda;lambda ;lambdas;lamda_mu_x;lamda_mu_y;omega;ones;psidot;r;r ;scale factors with friction;sign;steer;transform to Inertial axes ;u;w;w_front;w_rear;xdotAxle;xdotWheel;y;ydotAxle;ydotWheel;z;zdot;zdotAxle;zdotWheel

BLOCKTYPE:
Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;Combined Slip Wheel 2DOF;Concatenate;Constant;CrossProduct;Demux;Dugoff 2DOF;Fiala Wheel 2DOF;ForEach;From;Gain;Goto;Inport;InportShadow;Math;Mux;Outport;PermuteDimensions;Product;Reshape;S-Function;Saturate;Selector;SignalSpecification;Signum;Sum;Terminator;UnaryMinus;Vector Transformation;Vehicle Body 3DOF Lateral;Vehicle Body 6DOF 2 Axle;Vehicle suspension


MODELNAME: PassVeh3DOF
PATH: toolbox/vdynblks/vdynsolution/projectsrc/PassVeh3DOF/Plant/PassVeh3DOF.slx
ANNOTATION: Copyright 2017-2023 The MathWorks, Inc.
BLOCKTYPE: BusSelector;Gain;Inport;Outport;Selector;Sum;Terminator;Vehicle Body 3DOF Lateral
BLOCKTYPE_FREQUENCY: 1;1;3;8;1;1;2;1
CHECKSUM: 209DF0F999F3949045FB8C3B53719D58
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
BLOCK:
Bus Selector;Gain;Reference;Selector;Sum of Elements;Terminator;Vehicle Body 3DOF Single Track;WheelAngle;WindXYZ;X;Y;Z;ay;psi;r;xdot;xdotin;ydot


MODELNAME: PassVeh7DOF
PATH: toolbox/vdynblks/vdynsolution/projectsrc/PassVeh7DOF/Plant/PassVeh7DOF.slx
BLOCKTYPE_FREQUENCY: 5;1;6;26;8;1;18;12;10;1;1;3;3;90;4;2;52;3;17;1;2;7;2;20;10;30;1;2
CHECKSUM: 4ACCFBE62A088CE49679AE1269F84AA0
PRODUCT: MATLAB;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Copyright 2017-2023 The MathWorks, Inc.

BLOCK:
; Demux ; Info; SFunction ; Terminator ;Add;AxlTrq;Axle Forces;Bicycle;Bicycle Fz;Bicycle V;BrkPrs;Bus Assignment;Bus Creator;Bus Element In;Bus Element Out;Bus Selector;Bus to Vector;Camber;Combined Slip Wheel 2DOF;Constant;Cont LPF;Demux;Divide;Dual;Dual Fz;Dual V;Fiala;Fiala Tire;For 3D Visualization;For Each;Forces;Friction;FrntAxlF;Front;FwF ;FwR ;Fx;Fy;Fz;Gain;GemoXYZIn;GeomXYZ;Ground;In;Info;Longitudinal Wheels 4DOF;MF;Math Function;Mux;Out;P;RearAxlF;Reference;Reshape;Rotation Angles to Direction Cosine Matrix;Saturation;Selector;Signal Copy;Signal Specification;SubSystem;Subtract;Sum of Elements;T;Terminator;TirePrs;Tires;Transpose;Unary Minus;Unsprung Mass;Vector Concatenate;Veh;Veh2Tire;VehFdbk;VehVel;Vehicle;Vehicle Body 3DOF Dual Track;Vehicle Body 3DOF External Longitudinal Wheels;Vehicle Body 3DOF Single Track;Vehicle Signal Routing;VelVeh;Velocity and Vertical Load;Vx;Vy;Wheel;Wheel Angles;Wheel to Body Transform;WheelAngles;Wheels;WhlAng;WhlAngB;WindXYZ;angleIn;angles;camber;lambdas;lamda_mu_x;lamda_mu_y;ones;psidot;r;scale factors with friction;steer;xdotAxle;xdotWheel;ydotAxle;ydotWheel;zdotAxle;zdotWheel

BLOCKTYPE:
Ang2DCM;BusAssignment;BusCreator;BusSelector;BusToVector;Combined Slip Wheel 2DOF;Concatenate;Constant;Demux;Example 3DOF vehicle model;Fiala Wheel 2DOF;ForEach;Gain;Inport;Math;Mux;Outport;Product;Reshape;S-Function;Saturate;Selector;SignalConversion;SignalSpecification;Sum;Terminator;UnaryMinus;Vehicle Body 3DOF Lateral


MODELNAME: SiEngineMappedCntrlV
PATH: toolbox/vdynblks/vdynsolution/projectsrc/SI/Controller/SiEngineMappedCntrlV.slx
ANNOTATION: Copyright 2015-2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;3;6;1;1;7;26;3;19;1;2;4;9;2
CHECKSUM: 7414DB939BA5D26B386347C6DAC328DE
PRODUCT: Powertrain Blockset;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
BLOCK:
Add;AmbPrs;Bus Selector;Compare To Constant;Constant;Ect;EgrVlvAreaPct;EgrVlvAreaPctCmd;EgrVlvDeltaPrs;EgrVlvInTemp;EngSpd;EstIntkPortFlw;ExhCamPhase;ExhCamPhaseCmd;From;FuelMainSoi;Goto;Ground;Iat;IgSw;InjPw;InjPwIn;IntkCamPhase;IntkCamPhaseCmd;IntkSwirlVlvPos;IntkSwirlVlvPosCmd;IntkVlvLift;IntkVlvLiftCmd;LoadCmd;Logical Operator;Map;Mat;Reference;SI Controller;SpkAdv;Start Stop Logic;SubSystem;Switch;Terminator;ThrPosPct;ThrPosPctCmd;TrqCmd;TrqCmdISC;TrqCmdIsc;TrqCmdIscIn;TurboRackPos;TurboRackPosCmd;TurboSpd;Unit Delay;VarCompRatioPos;VarCompRatioPosCmd;VarIntkManPos;VarIntkManPosCmd;VarIntkRunLen;VarIntkRunLenCmd;WgAreaPct;WgAreaPctCmd

BLOCKTYPE:
BusSelector;Compare To Constant;Constant;From;Goto;Ground;Inport;Logic;Outport;SI Controller;Sum;Switch;Terminator;UnitDelay


MODELNAME: SiMappedEngineV
PATH: toolbox/vdynblks/vdynsolution/projectsrc/SI/Plant/SiMappedEngineV.slx
ANNOTATION: Copyright 2018-2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;4;1;1;2;1;1;1;1;1;1
CHECKSUM: 719085B48E49B3A19BB0292A8BBE1089
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
BLOCK:
Accessory Load Model;Accessory Load Power;Divide;Electronic Throttle Actuator Dynamics;EngSpd;EngTrq;EngTrqIn;EngTrqOut;Engine Response;Kw to w;Mapped SI Engine;Net Torque;Reference;Saturation;Signal Specification;SubSystem;Terminator;TrqCmd;Unit Conversion;rpm to rad/s

BLOCKTYPE:
Gain;Inport;Lookup_n-D;Mapped SI Engine;Outport;Product;Saturate;SignalSpecification;Sum;Terminator;UnitConversion


MODELNAME: SCRReferenceApplication
PATH: toolbox/vdynblks/vdynsolution/projectsrc/SceneCameraRay/System/SCRReferenceApplication.slx
BLOCKTYPE_FREQUENCY: 3;2;1;11;5;1;6;8;30;1;4;1;2;8;7;7;56;1;1;1;4;1;1;1;4;4;37;5;10;3;4;1;9;7;1;1;1;1;2;11;4;12;4;1;1
CHECKSUM: 36799141F3D61E123688F6882C33ED37
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
Longitudinal Command Logic Brakes Powertrain & Driveline Vehicle Feedback Displays Dynamics and Controls Sensors Controls Copyright 2017-2023 The MathWorks, Inc.

BLOCK:
; Multiport Switch;AWD;Abs;Acc;Accelerator;Add;AxlPwr;AxlTrq;Brake;Brake Hydraulics;Brakes and Wheels;BrkPrs;BrkPrsCmd;Bus Creator;Bus Selector;Bus to Vector;Camber;Circuit;Combined Slip Wheel 2DOF;Compare To Constant;Constant;Cont LPF;Data Type Conversion;Decel;Demux;Diff Torque;Display;Divide;Driveline;DriverCmd;Dual;Dual Fz;Dual V;EngPwr;FWD;For Each;Forces;Friction;FrntWhl;From;Front;Front Bias;Front Force;FrontF;FwF;FwR;Fx;FxyF;FxyR;Fy;Fz;Gain;Gamma;Gear;Gnd;Goto;Headlights;High Beams;HndWhl;Idx;Image;ImageDisplay;In;Kinematic Steering;Knob;Level-2 MATLAB S-Function;Light Controls;Low Beams;Math Function;Max;Multiport Switch;Mux;Omega;Out;P;Powertrain;Powertrain & Driveline;Product;Prs;RWD;Rear Bias;Rear Force;RearF;Reference;Reshape;Reverse;Rotary Switch;Rotation;Rotation Angles to Direction Cosine Matrix;Saturation;Saturation Dynamic;Scale;Selector;Signal Lights;Signal Specification;Simulation 3D Actor Transform Get;Simulation 3D Camera Get;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;Slider;Spool;Steer;Steering;SubSystem;Subsystem;Subtract;Sum of Elements;Switch;T;TAxles;TPowertrain;Terminator;Tip Out;Tire2Veh;TransformDisplay;Translation;Turn Signal Left;Turn Signal Right;Unary Minus;Unit Conversion;Unsprung Mass;Valve;Vector Concatenate;Veh2Tire;VehFdbk;VehVel;Vehicle;Vehicle Body 3DOF Dual Track;VelVeh;Volume;Wheel Angles;Wheel to Body Transform;WheelAngles;WhlAng;WhlAngB;WhlAngF;WhlCmb;YawRate;camber;div0protect;lambdas;lamda_mu_x;lamda_mu_y;ones;psidot;r;scale factors with friction;steer;xdotAxle;xdotWheel;ydotAxle;ydotWheel;zdotAxle;zdotWheel

BLOCKTYPE:
Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;Combined Slip Wheel 2DOF;Compare To Constant;Concatenate;Constant;DataTypeConversion;Demux;Display;ForEach;From;Gain;Goto;Inport;Integrator;Kinematic Steering;KnobBlock;LampBlock;M-S-Function;Math;MinMax;MultiPortSwitch;Mux;Outport;Product;Reshape;RotarySwitchBlock;Saturate;Saturation Dynamic;Selector;SignalSpecification;Simulation 3D Actor Transform Get;Simulation 3D Camera Get;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral


MODELNAME: SSSReferenceApplication
PATH: toolbox/vdynblks/vdynsolution/projectsrc/SweptSineSteering/System/SSSReferenceApplication.slx
CHECKSUM: 87F269166805C2B855B43A29368E5EB6
PRODUCT: MATLAB;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear The Ground Feedback variant subsystem is automatically enabled/disabled according to the 3D Engine settings found in the Reference Generator. Manually overriding this variant may result in initialization errors.  1) Add additional chassis Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add additional Engine Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Placeholder for introducing faults, detailed actuator behavior, interactions of other systems with a human interface such as changes in power steering and braking assistance.   1) Add additional Driveline Model reference blocks as valid variant choices for your specific use cases. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Vehicle Response Driver Commands Copyright 2018-2023 The MathWorks, Inc.

BLOCK:
 Demux ; Driver; Gear; SFunction ; Terminator ;1-D Lookup Table;10ms Function-Call Generator;3D Engine;3D Engine Disabled;3D Engine Source;<Accel>;<Kappa>;<WhlAccel>;<xdot>;ABSCtrlForEach;ABSFlag;ABSForEachWheel;Abs;Acc to Torque Request;AccCmd;AccFdbk;Accel;AccelCmd;AccelFdbk;AccelGround;Acceleration Cmd;Active Differential Control;Add;AllParts;AxlTrq;Bang Bang ABS;Bang-bang controller;Body;Body Ptich;Body Roll;Body Yaw;Body, Suspension, Wheels;BodyX;BodyY;BodyZ;Brake;Brake Cmd;Brake Pedal;Brake Pressure Control;BrakeCmd;BrakeGround;BrkCmd;BrkCtrl;BrkFlag;BrkPrs;BrkPrsCmd;Bus Creator;Bus Element In;Bus Selector;Bus to Vector;Calculate Downshift Threshold;Calculate Upshift Threshold;Chassis Input;Chassis Output;Cntrl;CntrlRx;CntrlTx;Compare To Constant;ConcatOut;Constant;Cont LPF;Controllers;Current Gear;DCM;Data Type Conversion;Dead Zone;Debounce;DecelCmd;DecelFdbk;Demux;Detect Increase;DiffPrsCmd;DiffTrqCmd;Disabled;Discrete-Time Integrator;Divide;DownReq;Driveline;Driveline Ideal Fixed Gear;Driveline Input;Driveline Output;Driver;Driver - No Clutch;Driver Commands;ECU;Enabled;Enb;Eng;EngSpd;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Input;Engine Output;Engine Tach [rpm];Env;Environment;First Order Hold;Five-State ABS and TCS;Flag;For Each;For Each Subsystem;Friction;From;Gain;Gear;GearCmd;GearFdbk;GearGround;GearReq;Gnd;Goto;Ground;Ground Feedback;Handwheel Angle [deg];Highbeam;ISO 15037-1:;Ideal Mapped Engine;Integrator;Internal Tire Contact Plotter;Interpreted MATLAB Function;IsNegative;Kappa;KappaEst;Lateral Acceleration [g];Left Signal;Linear Predictive Driver;Logical Operator;Longitudinal Driver;Lowbeam;MATLAB Function;Max;Multiple Points;Mux;Neutral;Neutral Select;No Control;OR;Omega;Open Loop;OperatorFdbk;Out Bus Element;PID Controller;PRNDL Controller;Paddles;Part Rotation Concatenation;Part Translation Concatenation;PartConcatenation;PassVeh14DOF;PassVeh7DOF;Passenger Vehicle;Pb;PbFdbk;PbOutput;Pedal Cluster Input;Pedal Cluster Output;Pedal Cluster and Cabin;Predictive Driver;Pref;Product;PropShftSpd;Range Limiter;Rate Transition;Rear Diff Controller;Reference;Relational Operator;Reshape;Rev Limiter Control;Reverse;Right Signal;Rotation Angles to Direction Cosine Matrix;SG Diff;Saturation;Scale;ScaleOut;Selector;Sensors;Signal Specification;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Single Point;SpdThr;Speed LPF;Speed [mph];Start Steering Command;Steer;Steer vs Ay;Steer, Velocity, Lat Accel;SteerCmd;SteerFdbk;SteerGround;SteerHWCmd;Steering;Steering, Transmission, Driveline and Brakes;StrWhlTrq;SubSystem;Subsystem;Subtract;Sum;Sum of Elements;Swept Sine Reference Generator;Switch;TCM;TCM Shift Controller;TCSCtrlForEach;TCSFlag;Terminator;Three-axis Inertial Measurement Unit;Torque Cmd;Transmission Controller;Transmission Controller PRNDL;TrqCmd;TrqCmdRevLimited;Unary Minus;Unit Conversion;UpReq;Vector Concatenate;Veh;VehFdbk;VehRef;VehSpd;Vehicle XY Plotter;Visualization;Wheel Accel;Wheel Accel and Slip Estimator;WheelDCM;WheelFrontLeft;WheelFrontLeft Pitch;WheelFrontLeft Roll;WheelFrontLeft Yaw;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRight Pitch;WheelFrontRight Roll;WheelFrontRight Yaw;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeft Pitch;WheelRearLeft Roll;WheelRearLeft Yaw;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRight Ptich;WheelRearRight Roll;WheelRearRight Yaw;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels;WhlAccel;WhlAng;WhlSlip;Wind;WindXYZ;Yaw Rate and Steer;Zend Select;axayaz;axle distance;calc;calc_down;calc_up;div0protect - poly;down_th;e;f;function;gear;in_;mu;out_;pedal;phi,theta,psi;pqr;speed;steer ratio;up_th;wheel radius;xdot;z;zero

BLOCKTYPE:
3D Engine;Abs;Ang2DCM;BusCreator;BusSelector;BusToVector;CircularGaugeBlock;Compare To Constant;Compare To Zero;Concatenate;Constant;DataTypeConversion;DeadZone;Debounce;Demux;Detect Increase;DiscreteIntegrator;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;FirstOrderHold;Five-State ABS Control;Five-State TCS Control;ForEach;From;Function-Call Generator;Gain;Goto;Ground;ISO 15037-1:2006;Inport;Integrator;LampBlock;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;MATLABFcn;MinMax;ModelReference;Mux;Outport;PID 1dof;Predictive Driver;Product;RateTransition;Record;RelationalOperator;Reshape;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalSpecification;Simplified Savitzky-Golay Differentiator;Simulation 3D Scene Configuration;Simulation 3D Terrain Sensor;Simulation 3D Vehicle;Sum;Swept Sine Steer;Switch;Terminator;Terrain Source;Three-axis Inertial Measurement Unit;Tire Contact Plotter;Transmission Controller PRNDL;TriggerPort;UnaryMinus;UnitConversion;UnitDelay;Vehicle XY Plotter

BLOCKTYPE_FREQUENCY:
1;4;1;21;44;7;2;11;1;26;49;22;6;3;17;1;2;1;1;12;1;1;6;13;1;10;9;8;1;245;4;1;2;8;1;5;1;1;4;2;127;1;1;3;16;1;5;6;5;14;2;14;2;1;42;1;1;2;1;17;1;6;37;1;1;1;1;4;3;28;1;1


MODELNAME: ltehdlCellSearch
PATH: toolbox/whdl/whdlexamples/ltehdlCellSearch.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;7;1;7;3;1;10;2;1;24
CHECKSUM: D40FB53FC00D98F53EFD86F9C19817B3
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: ltehdlDownlinkSyncDemod___Model_Block___
ANNOTATION:
 Stop the simulation when either: subframeNum exceeds 5, cell search is done, however no cell was detected LTE HDL Cell Search

BLOCK:
Bus Selector;Cell Search HDL;Compare To Constant;Constant;Data Type Conversion;Delay;Diagnostics To Workspace;Display;Downlink Sync Demod;Logical Operator;NCellID;Reference;Signal From Workspace ;Stop Condition;Stop Simulation;SubSystem;TDDMode;To Hz;To Workspace;cellDetected;cellSearchDone;dataIn;diagnostics;freqEst;gridData;gridValid;start;stop;subframeNum;timingOffset;validIn

BLOCKTYPE:
BusSelector;Compare To Constant;Constant;DataTypeConversion;Delay;Display;Gain;Inport;Logic;ModelReference;Outport;Signal From Workspace;Stop;ToWorkspace


MODELNAME: ltehdlChannelEqualizer
PATH: toolbox/whdl/whdlexamples/ltehdlChannelEqualizer.slx
BLOCKTYPE_FREQUENCY: 6;1;1;1;2;38;4;97;3;1;3;1;4;4;86;1;4;2;14;2;48;10;3;2;3;1;1;16;12;1;5
CHECKSUM: 588DB50725EAE4A4BC11BB1CA9CA081C
PRODUCT: DSP System Toolbox;Fixed-Point Designer;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
subframe 0 symbol 8 subframe 5 symbol 8 subframe 0 symbol 1 subframe 5 symbol 1 subframe 0 symbol 0 subframe 5 symbol 0 subframe 0 symbol 4 subframe 5 symbol 4 subframe 0 symbol 7 subframe 5 symbol 7 subframe 5 symbol 11 subframe 0 symbol 11  See 36.211 section 6.10.1.1 for Cinit calculation Scale to keep output in +/-1 range 1-bit counter to toggle on odd and even bits toggle on n 2nd channel estimate, h2 1st channel estimate, h1 Received Symbols A*.R - delay(B.R*) delay(A*.R) + B.R* B.R* A*.R get difference between RS average difference across 3 locations multiply by 2 to get 2/3rds if first RS repeat current RS downwards if last RS repeat previous RS upwards Averaging two values

BLOCK:
 Demux ; SFunction ; Terminator ; cellRefGen;A;AND;Add;B;Bit Shift;Bus Creator;Bus Selector;Compare To Constant;Complex shift;Complex to Real-Imag;Conjugate;Constant;Data Type Conversion;Delay;Demux;Detect Rise Positive;Downsample;Equal;Extract Bits;Gain;Gold Sequence Generator;HDL Counter;In;InterpCalculation;LTE Gold Seq upsampling;Multiply;Multiport Switch;Mux;NCellID;NDLRB;NOT;NSubframe;NcellID;Ncp;Nsubframe;OR;Out;Product;RS Counter;Real-Imag to Complex;Reference;Repeat;S;SValid;State Control;Sub;SubSystem;Subsystem;Subtract;Switch;Symb Counter;TxDivDecode;addr;addrBank;addrBias;addr_in;addr_mapper;address;ant0ram;ant1ram;average;c_initGen;cellDetected;cellID;cellMod;cellRef;chEst;cinit;complex;current;dOut;dOut_RS;dataIn;dataValid;doAverage;doInterp;doInterp ;downsampling seq2complex;enGold;enOut;en_GoldCode;enable;eqSymbols;gold;gridData;gridWriteDone;hEst;hEstControl;hEstInterpAndStore;hEstRdy;hEstValid;hEst_a;hestDone;hestRS;hestRdAddr;hestRdEnable;hestRdy;interpValid;isFirstRS;isLastRS;load;memory_addr;memory_num;mod3HDL;mod6HDL;ndlrb;noRs;ofdmSymb;ofdmSymbol;outValid;previous;quotient;ramAddr;rdAddr;rdEn;readAddress;readEnable;refRS;reminder;reset;resetCount;rsBank;rsBankSymbolCount;rsCount;rsData;rsValid;rsbank;rscount;rxRS;sequence;slot_0_sym_;slot_10_sym_;slot_11_sym_;slot_1_sym_;subframe;trigger cinit load;valid;validOut;wrtA;wrtAddr;wrtAddrBase;wrtEnA

BLOCKTYPE:
Bit Shift;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;DownSample;Extract Bits;Gain;HDL Counter;Inport;LTE Gold Sequence Generator;Logic;Math;MultiPortSwitch;Mux;Outport;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;StateControl;Sum;Switch;Terminator;hdl.RAM


MODELNAME: ltehdlDCIResourceAllocation
PATH: toolbox/whdl/whdlexamples/ltehdlDCIResourceAllocation.slx
BLOCKTYPE: DataTypeConversion;Demux;Detect Rise Positive;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;2;1;23;19;2;5
CHECKSUM: 2216FF30A70550698BC0306A3EDEC6C3
PRODUCT: Fixed-Point Designer;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
 Demux ; SFunction ; Terminator ;AllocationType;DCI Format;DCIBits;DCIFormat;DCILen;DCIbits;Data Type Conversion;Detect Rise Positive;Gap_out;NDLRB;NFrame;RIV;RIV_out;RV;RV_out;Reference;Start;SubSystem;Terminator;aType_out;clear;dciResourceAlloc;done;duplexMode;formatType;gapBool;hdllteDCI;rbSet;rb_cols;rb_rows;rbset;rbsize;reset;state_wire;trblkLen;trblklen_out;validIn;validOut;validOut_out


MODELNAME: ltehdlDownlinkSyncDemod
PATH: toolbox/whdl/whdlexamples/ltehdlDownlinkSyncDemod.slx
BLOCKTYPE_FREQUENCY: 1;4;3;2;1;1;3;9;1;3;30;286;19;10;6;2;9;2;174;9;1;3;2;166;15;3;3;19;8;4;35;4;43;6;1;2;3;2
CHECKSUM: EDD7011F83BD5C860D842A20A79BEE66
PRODUCT: DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
Note that this subsystem has an overflow warning suppressed programmatically in its InitFcn callback.  Note that this subsystem has some warnings suppressed programmatically in its InitFcn callback. The CIC filter relies on overflow to function correctly.  Extra delay, to make overall filter chain delay up to a multiple of 16. reinterpret as 14 bit signed int This subsystem corrects the frequency offset using an Numerically Controller Oscillator (NCO) and a conjugate multiplication. reinterpret as 14 bit signed int This subsystem corrects the frequency offset using an Numerically Controller Oscillator (NCO) and a conjugate multiplication. This subsystem records the maximum CP correlation level, and the corresponding phase angle of the result, across windows of time equivalent to 1 slot (960 samples). A counter is used to reset the running max and record the final phase value, which is then passed to the output and qualified by the validOut signal. Store current mag & angle if mag is greater than previous max mag. This register stores the current running max magnitude in the current time window Use a comb filter followed by an integrator to implement an efficient 8-tap moving average.  This subsystem averages 7 of the CP correlation results, equivalant to 1 slot of averaging. This is done by delaying the signal by integer multiples of the OFDM symbol period, i.e. 137 samples. To optimize for HDL we scale the summation result by 1/8 rather than 1/7.  Correlate the signal with itself delayed by the FFT length (128 samples). Integrate across part of the CP length, which is 9 samples. However we use 8 samples here to optimize for HDL implementation. Finally average across 7 OFDM symbols, i.e. the number in each slot. Output toggles between zero and one  Reinterpret the result as fixdt(1,16,15), thereby scaling the signal by 2^-7.  Cast to 16 bits, making the 5th MSB the new MSB. Use rounding and saturation. Sum across a window of 128 samples using a comb filter followed by an integrator. A B explicitly model filter running at 61.44MHz (32 x 1.92MHz) to enable resource sharing A B explicitly model filter running at 61.44MHz (32 x 1.92MHz) to enable resource sharing A B explicitly model filter running at 61.44MHz (32 x 1.92MHz) to enable resource sharing  Measure the energy in the signal across a 128 sample window, which is equivalent to the PSS correlation window. This will be used later to generate a threshold.  Use a simple circular buffer to synchronize the streams, given that the correlators have greater latency than the signal power measurement.  Scale the signal by the square root of the threshold scaling factor before measuring the energy. This leads to a more efficient implementation than applying the scaling factor afterwards.  Apply a lower limit to the threshold to prevent small signals from triggering detection. Delay matching is not needed for the start and startTime signals, because the peak search uses a timing reference to schedule the start operation at some point in the future.  SSS Threshold Scaling Apply gain of sqrt(SSSThresholdScalingfactor) before squaring the signal to avoid the need for a wide multiplier.   SSS Normalization Factor  Magnitude squared Reduce the correlation result to 18 bits, keeping the MSBs. This facilitates efficient resource utilization on Xilinx and Intel FPGAs.  Multiply dataIn by seqIn: since seqIn is always either -1 or 1, use a gain of -1 and a switch to invert dataIn when seqIn = -1.  SSS correlation accumulator: The SSS consists of 62 complex values therefore 6 bits of headroom are required in the accumulator.  Only compute signal energy the first time, since the data is repeated 336 times. The TDD indicator does not need to be delay balanced, as it only gets updated once the Max Likelihood has completed the set of correlations for each mode. Introduce a 1 cycle delay to the data stream. This means that the PSS searcher outputs are advanced 1 cycle relative to the the data stream, and simplifies the SSS state machine by giving it one cycle to respond to PSSDetected and entering the WAITING_FOR_PSS_END state.  Signals at the bottom of the block diagram are sampled at 30.72 Msps, represented by a Simulink rate of 30.72 MHz.  Signals in this area are processed at a Simulink rate of 61.44 MHz. The sampling rate of the Decimation Filters subsystem output is 1.92 Msps, however the signals are oversampled at 61.44 MHz to allow resource sharing within filters and correlators, and accelerate SSS search operations. 

BLOCK:
 Demux ; SFunction ; Terminator ;Accumulator;Add;AngleAtMaximum;Bus Assignment;Bus Creator;Bus Selector;C;C+D;C-D;CIC Compensation Decimator;CIC Filter;CIC Gain Comp;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Constant;Correlators;CyclicPrefixCorrelator;DT Conversion;Data Type Conversion;Decimation Filters;Decimator;Delay;Detection Status;Determine Frame Timing;Diagnostics Bus Concatenator;Discrete FIR Filter;Downsample;Edge Detector;FFT HDL Optimized;FFT Shift;Find Max Correlation;Freq Est Reg;Frequency Correction 16x;Frequency Correction 1x;FrequencyEstimation;Gain;HDL Counter;Logical Operator;Magnitude Squared ;MagnitudeSquared;Max Element;Max Likelihood SSS;Max Likelihood SSS Bus Creator;Max Peak Searcher;MaxDiagnostics;MovingAverage;NCO HDL Optimized;NCellID;NCellIDIn;NCellIDOut;OFDM Demod Mask Generator;OFDM Demodulation;Output Interfacing;PSS Diagnostics Bus Creator;PSS Searcher;PSSAttempt;PSSCorrelation;PSSDetected;PSSDiagnostics;PSSDone;PSSEndTimingOffset;PSSIdxIn;PSSMaxCorrelation;PSSPeakTimingOffset;PSSSuccess;PSSThreshold;PSSTimingOffset;PSSValid;PSSXCorr;Peak Search;Product;Real-Imag to Complex;Rect2Polar;Reference;Relational Operator;Rx Sync Signal Buffer;SSS Correlation Controller;SSS Diagnostics Bus Creator;SSS Search Controller;SSS Searcher;SSS Sequence LUT;SSSAttempt;SSSCorrelation;SSSDiagnostics;SSSDone;SSSFound;SSSHalfFrameIndicator;SSSMaxCorrelation;SSSPSSPhaseAligned;SSSSuccess;SSSThreshold;SSSValid;SSSWinningSeqNum;SSS_Dot_Product;Signal Specification;Single Port RAM System;SlotAverage;Start Controller;State Control;Stream Syncronizer;StreamSyncronizer;SubSystem;Subframe Counter;Sum;Switch;Sync Signal Search;Synchronous Enabled 128 Sample Delay ;Synchronous Enabled Unit Delay;TDD;TDDMode;TDDModeIn;TDDModeOut;Terminator;ThresholdLimiter;ThresholdPrescaling;Timing Offset Mask Generator;Transfer Timing Offset;Transient Removal;Unit Delay Enabled Resettable Synchronous;Unit Delay Resettable Synchronous;Upsample;Vector Concatenate;accEnd;accStart;addr;angleIn;angleOut;attempt;cellDetected;cellDetectedStb;cellSearchDone;cellSearchDoneStb;cellsearchDone;complexConj;complexConjugate;corr;corrOut;correlation;correlationIn;correlationOut;counter;dataIn;dataOut;diagnostics;done;duplexMode;duplexModeDone;en;enable;freq;freqEst;freqEstRegEn;freqEstValid;gridData;gridValid;halfFrameIndicator;idx;inputValid;magIn;magOut;maxCorr;maxCorrelation;modeDone;pop;push;rdEn;real;reset;sampleIndex;sampleValidOut;searchStart;seqEnd;seqIn;seqNum;seqNumIn;seqNumOut;seqStart;slotValidOut;start;startBuffering;startIn;startTime;subframe;subframeNum;success;threshold;thresholdExceeded;thresholdIn;thresholdOut;timingOffset;timingOffsetIn;timingOffsetLong;timingOffsetOut;timingOffsetValid;tin;tout;validIn;validOut;winningSeqNum;wrEn;x;xmax;y;z

BLOCKTYPE:
BusAssignment;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle;ComplexFIRFilter;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Discrete FIR Filter;DownSample;FFT;Gain;HDL Counter;Inport;Logic;Lookup_n-D;Math;NCO;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Unit Delay Resettable Synchronous;Upsample;hdl.RAM


MODELNAME: ltehdlMIBRecovery
PATH: toolbox/whdl/whdlexamples/ltehdlMIBRecovery.slx
ANNOTATION: DECODING INDEXING GRID LTE Cell Search and MIB Recovery
BLOCKTYPE_FREQUENCY: 1;1;2;1;2;2;12;9;4;8;2;5;19;1;3;1;3
CHECKSUM: C5A4E925F362D48D6CC3F396E1259F53
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
Bus Creator;CellRefP;Channel Equalization;Compare To Constant;Constant;ControlSignals;Data Type Conversion;Delay;Detect Rise Positive;Display;Downlink Sync Demod;From;Goto;HDL LTE MIB Recovery;MIB Decoder;NCellID;NDLRB;NFrame;NcellID;Ng;Nsubframe;OFDMdata;OR;PBCH Decoder;PBCH Indexing;PHICH;Reference;Resource Grid Memory;Signal From Workspace ;Stop Simulation;SubSystem;TDDMode;Terminator;cellDetected;cellSearchDone;dataIn;freqEst;mibDetected;mibError;restart;startIn;validIn

BLOCKTYPE:
BusCreator;Compare To Constant;Constant;DataTypeConversion;Delay;Detect Rise Positive;Display;From;Goto;Inport;Logic;ModelReference;Outport;Scope;Signal From Workspace;Stop;Terminator

EXTERNALFILE_REFERENCE:
ltehdlChannelEqualizer___Model_Block___ltehdlDownlinkSyncDemod___Model_Block___ltehdlPBCHDecoder___Model_Block___ltehdlPBCHIndexing___Model_Block___ltehdlResourceGrid___Model_Block___


MODELNAME: ltehdlPBCHDecoder
PATH: toolbox/whdl/whdlexamples/ltehdlPBCHDecoder.slx
BLOCKTYPE_FREQUENCY: 1;1;2;2;2;1;48;11;10;1;53;1;1;1;9;61;1;3;1;11;1;1;1;2;2;12;1;5;1
CHECKSUM: CA2C125F3F337064607C376BC49133C2
PRODUCT: DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
dataInDT is used to convey type information only. Its signal values are not used.  coarse gain (left shift)  fine gain start reading data from RAM once the scaling terms are ready shiftAmount and fineGain are constant after scalingValid goes HIGH.

BLOCK:
 Demux ; SFunction ; Terminator ;AllZeroMIB;Apply Scaling;BCH Controller;BCH Decoder;BCHControllerCore;Bus Selector;CRC Decoder;CellRefP;Compare To Constant;Complex to Real-Imag;Convolutional Decoder;Data Type Conversion;Delay;Determine Scaling;Downsample;Gold Sequence Generator;HDL Counter;In;Logical Operator;MIB Data Buffer;MIB Interpretation;MIBDetect;MIBDetected;MIBDetectedPulseResync;MIBError;MIB_detected;Maximum Average Absolute Value;MemoryController ;NCellID;NDLRB;NFrame;Ng;Out;PBCH Controller;PBCH Descrambling;PBCH Rate Recovery;PHICH;PHICHDuration;Product;Reference;Repeat;Rounding Symmetric Saturation;Sample Control Bus Creator;Shift Arithmetic;Sign Extend by ;Signal Specification;Simple Dual Port RAM System;SubSystem;Sum;Switch;Symmetric Saturation;Terminator;Unary Minus;Upsample;addr;cellRefP;cellrefp;clearOutputReg;clearReg;controlbusGen;crcErr;crcmask;ctrl;ctrlIn;ctrlOut;data;dataIn;dataInDT;dataOut;dataScaled;deScrambled;enableDecoder;enb;enb_des;fineGain;goldSeq;load_des;maxIn;maxOut;maxValid;nfmod;p;q;qpsksymbol;raddr_qpsk;rateRecovered;rateRecovery;repeatQPSK;repeatQPSKPulseResync;repeat_QPSK;repeat_qpsk;restartMIB;restartMIBPulseResync;restart_MIB;scalingValid;shiftAmount;softBitScalingUnit;startReading;symbolBuffer;symbols;u;valid;validIn;validOut;valid_eq;valid_seq;waddr_qpsk;writeEn;x;y

BLOCKTYPE:
ArithShift;Autoscaling memory controller;BusSelector;Compare To Constant;ComplexToRealImag;DataTypeConversion;Delay;Demux;DownSample;HDL Counter;Inport;LTE CRC Decoder;LTE Convolutional Decoder;LTE Gold Sequence Generator;Logic;Outport;Product;Repeat;Rounding and Symetric Saturation;S-Function;Sample Control Bus Creator;SignalSpecification;Simple Dual-port RAM;Sum;Switch;Terminator;UnaryMinus;Upsample;hdl.RAM


MODELNAME: ltehdlPBCHIndexing
PATH: toolbox/whdl/whdlexamples/ltehdlPBCHIndexing.slx
BLOCKTYPE_FREQUENCY: 1;3;8;1;20;1;2;9;5;1;2;8;4;5;3
CHECKSUM: 0068BBFECEDD1E2309D7D48CE1DFED31
PRODUCT: MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
Add;Bus Creator;Compare To Constant;Constant;Data Type Conversion;Delay;Direct Lookup Table (n-D);Enabled Subsystem;Extract Bits;HDL Counter;Logical Operator;Multiport Switch;NCellID;NOT;PBCHIndGen;Product;Reference;SubSystem;Subtract;Switch;addr;addr_in;adjustIdx;cellID;enb;enbGen;idx_data;idx_data_valid;idxdata;mod(12*6);mod3HDL;quotient;reminder;resetNoneReg;seI;start

BLOCKTYPE:
BusCreator;Compare To Constant;Constant;DataTypeConversion;Delay;Extract Bits;HDL Counter;Inport;Logic;LookupNDDirect;MultiPortSwitch;Outport;Product;Sum;Switch


MODELNAME: ltehdlPCFICHDecoder
PATH: toolbox/whdl/whdlexamples/ltehdlPCFICHDecoder.slx
BLOCKTYPE_FREQUENCY: 1;2;2;5;1;34;1;2;2;3;2;26;1;1;1;14;3;1;4;7;9;2;2;5
CHECKSUM: D99F283A65BC76848765EE0071F1FC22
PRODUCT: DSP System Toolbox;Fixed-Point Designer;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
cell ID is effictively a constant, available well before cinit is used, so pipeline delay doesnt need balanced

BLOCK:
 Demux ; SFunction ; Terminator ;Add;Bus Selector;CFI;CFI Extraction;CFIGenerator;Compare To Constant;Complex to Real-Imag;Constant;Data Type Conversion;Delay;Detect Rise Positive;Downsample;Gain;Gold Sequence Generator;HDL Counter;Im;Logical Operator;Mux;Out;PCFICH Decoder;Re;Reference;Repeat;State Control;SubSystem;Sum;Switch;Terminator;Unary Minus;Upsample;a;b;bitsOut;c;cell ID;cellID;cfi_max;cinit;cinit calculation;clear;clearOutputReg;en;enable;reset;resigerValid;rst;ser;serialiseReIm;sym;symbols;val;valid;validOut;y

BLOCKTYPE:
BusSelector;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;DownSample;Gain;HDL Counter;Inport;LTE Gold Sequence Generator;Logic;Mux;Outport;Repeat;S-Function;StateControl;Sum;Switch;Terminator;UnaryMinus;Upsample


MODELNAME: ltehdlPCFICHIndexing
PATH: toolbox/whdl/whdlexamples/ltehdlPCFICHIndexing.slx
BLOCKTYPE_FREQUENCY: 1;6;1;5;7;8;39;7;1;3;36;10;6;1;2;3;29;5;6;1;5;4;8;6;1;2;4
CHECKSUM: 7B4048707884663654FF5B147296906A
PRODUCT: Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 Extract fractions  Drop fractions 4x4x10b RAM Improve state machine to save 2 Tck while reading  Extract fractions  Drop fractions  LTE params do not change during operation, so no need to match pipeline delays  &quot;param setup&quot; and &quot;count on start&quot; both have latency of 1  Sort PCFICH to prepare for next stage (PHICH)  k = k + NCellID;  k = mod(k, NDLRB*2); Wrapped adder Rotate the samples to reproduce the subcarrier indexing REG calculator 1 accumulator for each quadruplet RS Index Skip the RS and unusued cells 4x4 to 1x16 k0 is the lowest index of each quadruplet

BLOCK:
 Demux ; SFunction ; Terminator ;1/y;2-D Lookup Table;4Counters;AND;Add;Bit Shift;Bit Slice;Bus Creator;Compare To Constant;Constant;Count on Start;Data Type Conversion;Delay;Demux;Dual Port RAM System;Gain;HDL Counter;HDL mod;IdxOut;In;Index Vector;LUT_out;LUTs;Logical Operator;MATLAB Function;MATLAB System;Matrix2Vector;MemoryController;Multiport Switch;NDLRB;NOT;OR;Offset Subcarrier;Out;PCFICH;Param Setup;Prev;Product;Pulse Gen;Q;R;Reference;S;SR_latch;Samples Sorting;Selector;Signal Specification;SubSystem;Subsystem;Switch;Unit Delay;addr;cellID;count;count_en;data;done;dv_NDLRB;enShift;enable;enb;enbGen;idxRAM;idxRed;k;k reg;k_in;k_out;load_k;lst_pcfich;mod_out;rd_addr;sel;selector;sort k;start;sym Out;symb;u;valid;valid Out;wr_addr;wr_en;x;y

BLOCKTYPE:
Bit Shift;Bit Slice;BusCreator;Compare To Constant;Constant;DataTypeConversion;Delay;Demux;Gain;HDL Counter;Inport;Logic;Lookup_n-D;MATLABSystem;Mod for HDL;MultiPortSwitch;Outport;Product;S-Function;Selector;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay;hdl.RAM


MODELNAME: ltehdlPDCCHDecoder
PATH: toolbox/whdl/whdlexamples/ltehdlPDCCHDecoder.slx
BLOCKTYPE_FREQUENCY: 1;1;2;5;1;5;3;32;13;1;5;1;1;73;1;1;1;6;1;3;60;1;1;6;1;12;1;3;1;14;1;3;1
CHECKSUM: 64E15E500A84B6F1367887A4C338F582
PRODUCT: DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
dataInDT is used to convey type information only. Its signal values are not used.  coarse gain (left shift)  fine gain start reading data from RAM once the scaling terms are ready shiftAmount and fineGain are constant after scalingValid goes HIGH. Matching RAM delay? Ensuring start arrives one clock cycle before valid

BLOCK:
 Demux ; SFunction ; Terminator ;Add;Apply Scaling;BW;Bus Selector;CRC Decoder;Compare To Constant;Complex to Real-Imag;ConsCinit;Constant;Convolutional Decoder;Data Type Conversion;Delay;Demod/Descramble;Demux;Detect Rise Positive;Determine Scaling;Downsample;Gain;Gold Sequence Generator;HDL Counter;In;Logical Operator;MATLAB Function;Maximum Average Absolute Value;MemoryController ;Multiport Switch;NDLRB;OR;Out;PDCCH RAM;PDCCHSearch;Product;QPSKDemod;Reference;Relational Operator;Repeat;Rounding Symmetric Saturation;Sample Control Bus Creator;Shift Arithmetic;Sign Extend by ;Simple Dual Port RAM System;SubSystem;Sum;Switch;Symmetric Saturation;Terminator;Unary Minus;Upsample;addr;cand_size;candidateNumber;candidateSize;candidate_number;candidate_size;cellID;clear;clearOutputReg;controlbusGen;crc;crcEnd;crc_check;crc_end;crc_valid;ctrlIn;ctrlOut;dataIn;dataInDT;dataOut;dataScaled;dataStream;dataValid;dciBits;dciControl;dciDecode;dciFormat;dciSize;dciSizeSelect;deScrambled;demod/descramble;descramValid;descrambled;detected;din;duplexMode;enable;err;error;fineGain;format1A_sizes_FDD;format1A_sizes_TDD;format1C_sizes;goldSeq;gridData;index;inputLen;maxIn;maxOut;maxValid;msgLength;msgSize;nBits;nSymbols;ndlrb;noDCI;pdcchFormat;pdcchRateRecovery;pdcchSearchControl;pdcchram;pos edge detector;qpsksymbol;rd_addr;rd_dout;readAddress;restart;scalingValid;searchStart;shiftAmount;sirnti_detected;size;softBitScalingUnit;softBits;start;startReading;stateOut;subBlock_Size;subBlock_Size_out;symbols;valid;validIn;validOut;valid_seq;wr_addr;wr_en;writeEn;wrtAddr;x;y

BLOCKTYPE:
ArithShift;Autoscaling memory controller;BusSelector;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;DownSample;Gain;HDL Counter;Inport;LTE CRC Decoder;LTE Convolutional Decoder;LTE Gold Sequence Generator;Logic;MATLABSystem;MultiPortSwitch;Outport;Product;RelationalOperator;Repeat;Rounding and Symetric Saturation;S-Function;Sample Control Bus Creator;Sum;Switch;Terminator;UnaryMinus;Upsample;hdl.RAM


MODELNAME: ltehdlPDCCHIndexing
PATH: toolbox/whdl/whdlexamples/ltehdlPDCCHIndexing.slx
BLOCKTYPE_FREQUENCY: 4;2;3;4;3;1;5;5;7;117;15;1;3;8;164;25;1;2;2;9;2;118;5;7;14;1;5;7;4;14;1;6
CHECKSUM: B22F23246C09ED4F79763E16D1A9C4C7
PRODUCT: Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 &quot;done&quot; indicates RAM is ready to be read Re-generate signal using falling edge of valid instead of pipelining the counter output multiple times  For mi = 0, use PCFICH valid falling edge to start PDCCH Indices calculation  Extract fractions  Drop fractions  LTE params do not change during operation, so no need to match pipeline delays  &quot;param setup&quot; and &quot;count on start&quot; both have latency of 1  Sort PCFICH to prepare for next stage (PHICH)  k = k + NCellID;  k = mod(k, NDLRB*2); EXREG RAM w/ latency 1  Max count = 199*6 = 1194  symN_REG counts 3 for every 2 sym0_REG count. Max count = 299  - For sym0, count in both steps of 1 &amp; 6 saves having to multiply by 6 or 1/6 later. - For symN, one counter is sufficient as a factor of 4 is just a shift.  Max count = 199 when NDLRB = 100 Use 9-bit as s0_SubC_dv6 &amp; s0_SubC_dv4 are muxed together later as read address for EXREG RAM (which is 9-bit deep)  &quot;start_out&quot; only need to match the latency of the longest path (mod)  # of OFDM symbols (0-based): if NDLRB == 6 numbOFDMSymbols = CFI + 1; else numbOFDMSymbols = CFI; end  # of REG in symbol 0 (0-based)  cellRS_shift = mod(NCellID,3); switch cellRS_shift case 0 k_new = [1;2;4;5]; case 1 k_new = [0;2;3;5]; case 2 k_new = [0;1;3;4]; end  REG to RE Expansion, uses k_new, which is the REs with RS removed  Extract fractions  Drop fractions  count_m = 1:Ngroup count_i = 1:3   k_expanded(index_i, index_m) = k_base(index_i) + index_m  if index_i == 1 x = k_expanded(index_i,index_m) + NCellID; k_shift(index_i, index_m) = mod(x, N_available_REGs(1)); else x = k_expanded(index_i,index_m) + cellID_shift; k_shift(index_i, index_m) = mod(x, N_available_REGs(2)); end  All inputs in this subsystem are constant after &quot;start&quot;, so no need to match pipeline delays  No need to calculate PHICH indices when mi = 0, as there is no PHICH info in the grid  Drop fractions only, do not need to pipeline  &quot;start_out&quot; only need to match the latency of the longest path (CellID_shift)  CellID_shift = floor(NCellID * ext_PHICH_nl_n0)  Shift indexes to valid locations in the grid (skip over PCFICH locations) For example, if PCFICH (sorted) = 0,3,6,9: k_in = 2 which is &gt;= 0. k_stage1 = 2+1 = 3 k_stage1 = 3 which is &gt;= 3. k_stage2 = 3+1 = 4 k_stage3 = 4 &lt; 6 &amp; 9. k_out = k_stage3 = 4 Msymb and Mquad passed straight through  Balance RAM delay Go must arrive 1 early 

BLOCK:
 Demux ; SFunction ; Terminator ;1/y;AND;Add;Bias;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;CFI;Calc Index;Calc K Shift;CellID;CellID_shift;Compare To Constant;Constant;Count on Start;Count on falling edge of k_valid;Counters;D;Data Type Conversion;Delay;Demux;Detect Rise Positive;Direct Lookup Table (n-D);EXREG RAM;Excluded REGs;Falling;Gain;Generate_data_to_EXRAM;HDL Counter;HDL mod;In;Index Vector;Logical Operator;Minus;Minus1_;Mquad;Mquad ;Mquad_out;Msymb;Msymb_out;Multiport Switch;Mux;Mvalid;NCellID;NDLRB;NOT;N_REGs;Ngroup;Ngs;OR;Out;PCFICH;PCFICH_data;PCFICH_k;PCFICH_valid;PDCCH;PDCCH_Index_Gen;PHICH;PHICH_ext;PHICH_k;PHICH_l;PHICH_valid;Param Setup;Prev;Product;Q;R;RAM Write Signals;Reference;Relational Operator;S;SC LSB counter;SR_latch;Selector;Set Valid Flag;Shift_and_Add;Signal Specification;Start;SubC_LSB;SubSystem;Switch;Sym0 Shift;Symb Counter;addr;calcCellIDShift;calcPDCCHsize;cellID;cfi;count;count on start;countIn;count_i;count_m;count_valid;dataIn;dataOut;dataOutSize;deinterleaver;detect_falling_edge;din;done;done_in;done_out;dv_NDLRB;dv_N_REGs;dv_y;ePHICH;enb;exreg;exreg_addr;exreg_data;extended;get shift value;go;hit;idx_vld;indexDone;indexingDone;k;k reg;k_base;k_data;k_in;k_new;k_out;k_shift;k_valid;k_validIn;k_validOut;l;l_out;lkBufferRdWrtControl;lk_ram;mi;mod_out;nSymbols;ncellid;ndlrb;ng;numOFDMSym;numREG_s;numSym;param setup fcn;phich;phich_ext;ramAddrCalc;rdAddr;rdValid;rd_addr;rd_dout;read_addr;read_data;reset;rst;s0_SubC;s0_SubC_dv;sN_SubC_dv;scIsEqual;shiftVal;sort k;start;start_in;start_out;sym;sym0 REG counter;sym0 SC counter;sym0_enb;sym0_flag;symN REG counter;symN_enb;symb;u;valid;validIn;validOut;valid_in;valid_out;wr_addr;wr_data;wr_en;wrtAddr;wrtEn;x;xmod;y

BLOCKTYPE:
Bias;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;BusCreator;Compare To Constant;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;Gain;HDL Counter;Inport;Logic;LookupNDDirect;MATLABSystem;Mod for HDL;MultiPortSwitch;Mux;Outport;Product;RelationalOperator;S-Function;Selector;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: ltehdlPDSCHDecoder
PATH: toolbox/whdl/whdlexamples/ltehdlPDSCHDecoder.slx
BLOCKTYPE_FREQUENCY: 1;1;3;4;3;10;1;1;10;10;71;7;1;2;12;4;4;5;90;1;1;1;15;2;1;70;1;6;5;1;7;1;7;1;1;1;17;5;7;2;2;4
CHECKSUM: 2046272F6567C4CC829D33F4E9FF1CB4
PRODUCT: DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
increment wr_addr on valid input if current write address has reached framesize-1, then reset wr_addr to account for repititions of input increment wr_addr on valid input feedback value at address in order to accumulate reset accumulator to ZERO based on input command keep rd_addr one cycle ahead of wr_addr and wr_diin input so there is time to feedback data from read to be accumulated need to set the adder output data type due to #of folding  state determines which stream is being processed, which corresponds to which blockram to write to. The write address has been computed by the previous subsystems. The write occurs if the valid_in is true. This occurs for 3*Framesize samples where Framesize=32*Rtotal. The read address is valid if it is positive which only occursfor the last Framesize samples address=mod(tx_column,32)+32*mod(effective_row+(tx_column==32),Rtotal);   effective_col=mod(col+Koffset(RV+1),32*2); increment column when row wraps around and valid  % for stream 0, the rows will increment by 2 but then divided back by 2 % to increment 1 at a time. Since streams1/2 are interleaved this will % facilitate going back/forth between them offset=mod(row,2); % determines stream1 or stream2 effective_row=floor(row/2);  if effective_col<32 row=row+2; else row=row+1; end if row==Rtotal*2 row=0; col=col+1; end  if effective_col<32 row=row+2; else row=row+1; end if row==Rtotal*2 row=0; col=col+1; end  effective_row=floor(row/2); % >32 identifies if in bottom 2/3 which is stream1/stream2 otherwise in % stream0 % the offset identifies from interleaving whether in stream1/stream2 state=(effective_col>=32)+offset; % use invP to compute column index tx_column=invP(mod(effective_col,32)+1)+(state==2); %% setup P and invP table(s) % enter in P table from standard P_table = [0 16 8 24 4 20 12 28 2 18 10 26 6 22 14 30 ... 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 ] ; % produce inverse of this table for Rx (rateRecovery) [~,B]=sort(P_table); invP=B-1; if ((tx_column<Nd) && (effective_row==0)) || ((tx_column==32) && (Nd>0) && (effective_row==Rtotal-1)) Koffset=[2 26 41 53]; dataInDT is used to convey type information only. Its signal values are not used.  coarse gain (left shift)  fine gain start reading data from RAM once the scaling terms are ready shiftAmount and fineGain are constant after scalingValid goes HIGH.

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Add;Apply Scaling;Bit Shift;Bit Slice;Bus Selector;CRC Decoder;CellID;Clear;Compare To Constant;Compare To Zero;Complex to Real-Imag;ComputeWriteAddress;Compute_Column_and_Row;Compute_Effective_Column;Compute_Row;Compute_State_Column_Row;Compute_Wr_Addr_Frame_Number;Constant;Data Type Conversion;Decrement Stored Integer;Delay;Detect Rise Positive;DetectNull;Determine Scaling;Done;Downsample;EffectiveColumn;EffectiveColumn_In;Effective_Column_Out;Error;Foldlen;FrameCounter;FrameNumber;FrameStart_Out;Framestart_in;From;Gain;Gold Sequence Generator;Goto;HDL Counter;IncrementColumn;InputFolding;KOffset;Logical Operator;MatchAddrDelay;MatchRAMDelay;MaxAddr;Maximum Average Absolute Value;MemoryController ;Mux;Nd;OutputAccumulatorBlockRAM;OutputMemory;PDSCHPRBS;Product;QPSKDemod;RAMDelay;RV;Reference;Relational Operator;Repeat;Reset;Rounding Symmetric Saturation;Rtotal;Rtotal_In;Rtotal_Out;Sample Control Bus Creator;SampleControlBusGeneration;Shift Arithmetic;Sign Extend by ;Signal Specification;Simple Dual Port RAM;Simple Dual Port RAM System;State Control;SubSystem;Sum;Switch;Symmetric Saturation;TBS;TRREnb;Turbo Decoder;TurboBlkSize;TurboRateRecovery;TurboRateRecoveryController;TurboblkSize;Unary Minus;Upsample;Valid;Valid ;Valid_In;Valid_Out;WriteAddress;addr;address;bitsValid;bufferLen;clearOutputReg;ctrl;ctrlIn;ctrlOut;d;data;dataIn;dataInDT;dataOut;dataScaled;data_in;data_out;data_valid;decision;doneOut;dout;effective_row;effectivecolumn;enable;enb;errorOut;fineGain;foldLen;generate_ram_address;gridData;invP;maxAddr;maxIn;maxOut;maxValid;paramCalc;rd_addr;readAddr;readRdy;registerOutputs;reset;reset_data;row;scalingValid;shiftAmount;sib1Error;sib1_bits;softBitScalingUnit;softBits;startReading;state;stream;symbols;tbBlkSize;trBlkLen;trbBlkSize;tx_column;validIn;validOut;valid_in;valid_out;wr_addr_counter;wr_din;wr_en;writeEn;x;y

BLOCKTYPE:
ArithShift;Autoscaling memory controller;Bit Shift;Bit Slice;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;DownSample;From;Gain;Goto;HDL Counter;Inport;LTE CRC Decoder;LTE Gold Sequence Generator;LTE Turbo Decoder;Logic;LookupNDDirect;Mux;Outport;Product;RelationalOperator;Repeat;Rounding and Symetric Saturation;S-Function;Sample Control Bus Creator;SignalSpecification;Simple Dual-port RAM;StateControl;Stored Integer Value Decrement;Sum;Switch;Terminator;UnaryMinus;Upsample;hdl.RAM


MODELNAME: ltehdlPDSCHIndexing
PATH: toolbox/whdl/whdlexamples/ltehdlPDSCHIndexing.slx
BLOCKTYPE_FREQUENCY: 1;19;43;3;1;1;39;2;22;6;3;8;14;3
CHECKSUM: 2A2BF2849E68BA788D18C230CE10A5FB
PRODUCT: Fixed-Point Designer;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
 Demux ; SFunction ; Terminator ;Add;Bus Creator;CFI;Constant;Delay;From;Goto;Mux;NDLRB;NDLRBOut;PDSCHIdxController;Product;SubSystem;Subtract;Switch;addr;addr_in;cellID;cellRSInfo;cellRefP;col;duplexMode;enable;end_found;end_i;end_j;indk;indl;k;mod3HDL;mod6HDL;pdschStart;prbCol;prbRow;prbSet;prbSetBuffer;prbSetSize;prbset;preprocessing;reminder;row;searchIdx;setSize;start;startOut;start_found;start_i;start_j;startendIdx;valid;validIn;validOut;y

BLOCKTYPE:
BusCreator;Constant;Delay;Demux;From;Goto;Inport;Mux;Outport;Product;S-Function;Sum;Switch;Terminator


MODELNAME: ltehdlResourceGrid
PATH: toolbox/whdl/whdlexamples/ltehdlResourceGrid.slx
BLOCKTYPE_FREQUENCY: 1;1;2;3;10;22;22;1;1;20;1;3;42;7;2;4;28;2;5;1;1;3;4;4;1;1
CHECKSUM: 64C8511FB9C98B8901380310F863C096
PRODUCT: Fixed-Point Designer;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
make the signal into vector of 14 exclude anything outside of central 110 RBs subcarriers, and DC subcarrier (RS are generated based on 110 RBs)

BLOCK:
; Demux ; SFunction ; Terminator ;AND;Add;Bit Shift;Bus Creator;Bus Selector;Compare To Constant;Constant;Data Type Conversion;Delay;Detect Rise Positive;Dual Port RAM System;Enabled Delay;Equal;Extract Bits;Gain;Grid Memory Bank;HDL Counter;LTE Memory Bank Write Controller;Logical Operator;MATLAB Function;Memory Bank;MemoryBank Write Controller;Multiport Switch;Mux;NDLRB;NcellID;OFDMdata;OR;Product;Reference;Relational Operator;Signal Specification;State Control;SubSystem;SubcarrierCounter;Subtract;Switch;addr_in;bank_num;cellID;data;dataIn;dataValid;data_in;data_in_mem;data_out;data_sel;data_valid;en_flag;enb;eq_index;gridBankSelect;gridData;gridWriteDone;hestReadAddr;hw_index;lst2hw;lst_index;mod3cellID;nBank;nbank;ofdmData;ofdmSymbolCounter;rd_addr;rd_bank;rd_bus;reminder;repeat;rsData;rsOutputGen;rsValid;rst;shift;valid;valid_in;valid_out;wrAddr;wrData;wr_addr;wr_done;wr_en;wr_en calculator;wr_en_flag;writeDone;writeSubframe

BLOCKTYPE:
Bit Shift;BusCreator;BusSelector;Compare To Constant;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;Extract Bits;Gain;HDL Counter;Inport;Logic;MultiPortSwitch;Mux;Outport;Product;RelationalOperator;S-Function;SignalSpecification;StateControl;Sum;Switch;Terminator;hdl.RAM


MODELNAME: ltehdlSIB1Recovery
PATH: toolbox/whdl/whdlexamples/ltehdlSIB1Recovery.slx
BLOCKTYPE_FREQUENCY: 3;2;1;1;4;24;4;7;7;1;66;36;62;3;12;1;45;4;3;1;7;1
CHECKSUM: 0BBC86F540BB24ABD98462C435E10B3F
PRODUCT: DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
allow PDCCH decode to finish before moving on allow for nFrame calc output after MIB detected Assume smallest BW until MIB is recovered GRID DECODING INDEXING CONTROL  LTE HDL SIB1 Recovery Example

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Bus Creator;Bus Selector;CFI;CFIDecoder;CONTROL;CellID;CellRefP;Channel Equalization;Compare To Zero;Constant;Data Type Conversion;Delay;Detect Rise Positive;Display;Downlink Sync Demod;Enable;FROM_SW_DCIALLOC;From;Goto;HDL LTE SIB;HDL MIB + SIB1 Decoder;In;MATLAB Function;MIBDecoder;Multiport Switch;NDLRB;NFrame;NOT;NcellID;Ng;Nsubframe;OFDMdata;PBCH Indexing;PCFICH Indexing;PDCCH Indexing;PDCCHDecodeSearch;PDSCH Indexing;PDSCHDecode;PHICH;Reference;Resource Grid Memory;SIB1 Bits Buffer;SW DCI Resource Allocation;Signal From Workspace ;SignalsFromSW;SignalsToSW;Stop Simulation;SubSystem;TDDMode;TO_SW_DCIALLOC;Terminator;To Workspace;cellDetected;cellRefP;cellRefP_valid;cellSearchDone;cellSearchFail;cfiValid;cfi_valid;clearOutput;dataIn;dciDetected;dciError;dciResourceAllocation;decoderState;decoderStateControl;duplexMode;enablePBCH;enablePCFICH;enablePDCCH;enablePDSCH;frameCount;gridWrDone;gridWriteDone;hestRdy;hestReady;mi;mibDetected;mibError;mib_detected;mib_error;nFrame;nFrameMIB;nFrameOut;nFrame_mib;nSubFrame;nSubframe;pbch_addr;pcfich_addr;pdcch_addr;pdsch_addr;prbCalcDone;rd_addr_bus;read_selector;reset;restart;sib1Bits;sib1BitsValid;sib1Done;sib1Error;sib1_done;sib1_error;startIn;state;stateViewer;state_in;stopSimulation;validIn;writeSubframe

BLOCKTYPE:
BusCreator;BusSelector;Compare To Zero;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;Display;EnablePort;From;Goto;Inport;Logic;ModelReference;MultiPortSwitch;Outport;S-Function;Signal From Workspace;Stop;Terminator;ToWorkspace

EXTERNALFILE_REFERENCE:
ltehdlChannelEqualizer___Model_Block___ltehdlDCIResourceAllocation___Model_Block___ltehdlDownlinkSyncDemod___Model_Block___ltehdlPBCHDecoder___Model_Block___ltehdlPBCHIndexing___Model_Block___ltehdlPCFICHDecoder___Model_Block___ltehdlPCFICHIndexing___Model_Block___ltehdlPDCCHDecoder___Model_Block___ltehdlPDCCHIndexing___Model_Block___ltehdlPDSCHDecoder___Model_Block___ltehdlPDSCHIndexing___Model_Block___ltehdlResourceGrid___Model_Block___


MODELNAME: dvbs2hdlBBFrameRecoveryCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlBBFrameRecoveryCore.slx
BLOCKTYPE_FREQUENCY: 1;1;16;9;1;1;1;8;8;207;3;4;1;6;97;19;3;2;81;2;3;1;5;6;8;12;1;10
CHECKSUM: C5125BDF974084432C1547AFADAED34A
PRODUCT: Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 Base Address Index: Remains constant till the end of the frame. changes by 1 after every short and by 4 after every normal frame  This subsystem is a copy of Wrap Address subsystem in the RAM subsystem  Offset Address : Each ramp signal in the time scope indicates a column pickup. 1,3,4,5 ramp signals in constant base address index indicates a frame demodulated from QPSK, 8 PSK, 16 APSK, 32 APSK symbols respectively. The height of the ramps indicates a normal or a short frame  For Deinterleaver : Connect these line to Time scope to visualize signals Write Ports Read Ports  The FEC frame type of the input sequence must match the FEC Frame type set on the Demod Deinterleave and FECDecode subsystem.

BLOCK:
 Demux ; SFunction ; Terminator ;Add;BCHFrameIgnored;Bit Concat;Bus Selector;Compare To Constant;Compute Read Offset Address;Constant;DVB-S2 BCH Decoder;DVB-S2 LDPC Decoder;DVBS2 HDL Deinterleaver;DVBS2 Symbol Demodulator;Data Type Conversion;Data Type Duplicate;Delay;Demod Deinterleave and FECDecode;Discard Out of Frame samples;Discard Unsupported Frames;Extract Bits;FEC Decoding;FECFrame;FECFrameOut;Fec Frame FIFO;Gain;Generate Signal for End of Frame;Generate and Add Read Base Address;HDL Counter;Indicate End of Every ShortFrame Length Samples;LDPCFrameIgnored;Logical Operator;MODCOD;MaxC LUT;MaxR Normal LUT;MaxR Short LUT;Multiport Switch;No HDL Read Address Debug Scope;Parameter Store FIFO;Product;RAM;RAM Address Generator;Read Offset Address;Read Offset Address Signals Generator;ReadVal Address;Reference;Sample Control Bus Creator;Simple Dual Port RAM;Single RAM Using Two RAMs;SubSystem;Switch;Symbol Demodulaor;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Wrap Address;Write Base plus Offset Address;Write Offset Address;Write Offset Address Normal Frame;Write Offset Address Short Frame;WriteVal Address;addr;baseAddrIdx;basePlusOffsetAddr;bitsOut;captureBaseAddrIdx;captureIn;captureOut;chkwrAddrEnd;cod Idx FIFO;codIdx;codIdxIn;codIdxOut;codIdxReg;convertMODCOD;ctrl;curC;curCorROut;curR;curRorCOut;dataIn;dataOut;enb;endIn;endIndicate;endOfPLSC;endOut;fec;fecFrame;fecFrameOut;fecframe;fecframeIn;fecframeOut;fecframeReg;isMODOCD;maxC;maxR;maxR_switch;maxRorCOut;modIdx;modIdxIn;modIdxOut;modIdxReg;modcod;modcodIs;modcodIs12Out;modidx;nRows and nColumns;nVarIn;nVarOut;offsetAddr;paramCapture;paramCaptureOut;paramValid;rd_addr;rd_dout;rd_end;rd_endOut;rd_start;rd_startOut;rd_valid;rd_validOut;readAddr;readAddrIn;readAddrOut;readEnd;readEndOut;readStart;readStartOut;readVal;readValid;readValidIn;readValidOut;reset;softBitsOut;startIn;startOut;status;symbolIgnored;u;valid;validIn;validOut;var;wrAddr;wrEnb;wr_addr;wr_din;wr_en;writeAddr;writeEnable;writeVal;y

BLOCKTYPE:
Bit Concat;BusSelector;Compare To Constant;Constant;DVB-S2 BCH Decoder;DVB-S2 LDPC Decoder;DVB-S2 Symbol Demodulator;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Extract Bits;Gain;HDL Counter;Inport;Logic;Lookup_n-D;MultiPortSwitch;Outport;Product;S-Function;Sample Control Bus Creator;Simple Dual-port RAM;Sum;Switch;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous


MODELNAME: dvbs2hdlPLHeaderRecovery
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlPLHeaderRecovery.slx
BLOCKTYPE_FREQUENCY: 1;6;5;2;6;3;5;3;4;16;1;2;1;1;1;13;1;2;3;1;3;1;5;1
CHECKSUM: 5B43C761951F0500A3C0E0F40A534D40
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: dvbs2hdlSyncPLHeaderRecoveryCore.slx___Model_Block___
ANNOTATION:
Channel  Set the same symbol rate for the Input Configuration subsystem and the Synchronizer and PL Header Decoder subsystem in dvbs2hdlSyncPLHeaderRecoveryCore model reference.  DVB-S2 HDL PL Header Recovery  Copyright 2021 The MathWorks, Inc.

BLOCK:
AWGN Channel;Add;Bus Selector;CFD;Constant;Constellation;Constellation Plots;Control Scope;Correlation Time Scope;Data Type Conversion;Delay;Display;Enable;Gain;In;Information Decoder;Input Configuration;Logical Operator;Mod;Mod ;NCO HDL Optimized;Out;Over All Fading Scaling;Product;Reference;Rx In frequency offset time scope;Spectrum Analyzer;SubSystem;Synchronization and PL Header Recovery;Terminator;To Workspace;Variable Fractional Delay;coarseFreqEst;dataIn;dataOut;diagBus;dvbs2hdlSyncPLHeaderRecoveryCore;endOfPLSC;fecFrame;finalOut;fineFreqEst;headerInfo;modcod;rstCCFO;rstCoarseCFO;rstFCPO;rstFineCPO;rxIn;symbSyncOut;txDataOut;txOut;txValidOut;validIn;validOut;varOut

BLOCKTYPE:
AWGN Channel;BusSelector;Constant;ConstellationDiagram;DataTypeConversion;Delay;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;Math;ModelReference;NCO;Outport;Product;Scope;Signal From Workspace;SpectrumAnalyzer;Sum;Terminator;ToWorkspace;Variable Fractional Delay

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;Simulink;Wireless HDL Toolbox


MODELNAME: dvbs2hdlReceiver
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlReceiver.slx
BLOCKTYPE_FREQUENCY: 1;3;1;8;5;2;9;3;7;3;3;4;1;29;3;2;1;3;1;15;1;3;1;3;1;3;1;18;3;1
CHECKSUM: E55615D3C37C4425E350AEDD7242F85F
PRODUCT_BASECODE: LH
ANNOTATION:
Channel  DVB-S2 HDL Receiver  Copyright 2021-2023 The MathWorks, Inc. TSorGS = 3 indicates a TS stream packet = 0 indicates a GS stream packet = 1 indicates a GS continuous stream = 2 reserved for future use  Set the same symbol rate for the Input Configuration subsystem, the Synchronizer and PL Header Decoder subsystem of the dvbs2hdlSyncPLHeaderRecoveryCore and the Stream Recovery subsystem of the dvbs2hdlStreamRecoveryCore model references.  Set the same FEC frame type for the Input Configuration subsystem and the Demod Deinterleave and FECDecode subsystem of the dvbs2hdlDemodDeinterleaveFecdecodeCore model reference.

BLOCK:
AWGN Channel;Add;Assertion;BBHeaderCRCInfo;BBheaderParams;Bus Creator;Bus Selector;CFD;Capture Stream Bits;Constant;Constellation;Constellation Plots;Control Scope;DFL;DVB-S2 HDL Receiver;Data Type Conversion;Delay;Display;Enable;Estimated Frequency offset;Extract Bits;Gain;HDL Counter;In;Input Configuration;Logical Operator;MODCOD;Mod;Mod ;NCO HDL Optimized;No HDL;Out;Over All Fading Scaling;Product;Reference;Repeat;Rx In frequency offset time scope;SYNC;SYNCD;Spectrum Analyzer;SubSystem;Terminator;To Workspace;UPL;Upsample;Variable Fractional Delay;bitsIn;bitsOut;dataIn;dataOut;decoded MODCOD;diagbus;dvbs2hdDemodDeinterleaveFecdecodeCore;dvbs2hdlStreamRecoveryCore;dvbs2hdlSyncPLHeaderRecoveryCore;endIn;endOfPLSc;endOut;errorOut;frameEnd;frameStart;headerCRCInfo;headerinfo;invalid;invalidPkt;nCoarseFreq;nFineFreq;numSynced;number of frames synchronized;rstCCFO;rstCoarseCFO;rstFCPO;rstFineCPO;rxIn;startIn;startOut;symbDemodInValid;symbDemodIndata;symbSyncOut;txDataOut;txOut;txValidOut;u;validIn;validOut;varEst

BLOCKTYPE:
AWGN Channel;Assertion;BusCreator;BusSelector;Constant;ConstellationDiagram;DataTypeConversion;Delay;Display;EnablePort;Extract Bits;Gain;HDL Counter;Inport;Logic;ManualSwitch;Math;ModelReference;NCO;Outport;Product;Repeat;Scope;Signal From Workspace;SpectrumAnalyzer;Sum;Terminator;ToWorkspace;Upsample;Variable Fractional Delay

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;Simulink;Wireless HDL Toolbox

EXTERNALFILE_REFERENCE:
dvbs2hdlBBFrameRecoveryCore.slx___Model_Block___dvbs2hdlStreamRecoveryCore___Model_Block___dvbs2hdlSyncPLHeaderRecoveryCore.slx___Model_Block___


MODELNAME: dvbs2hdlStreamRecoveryCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlStreamRecoveryCore.slx
BLOCKTYPE_FREQUENCY: 3;26;8;14;1;165;4;1;8;5;2;5;96;37;1;138;1;3;3;8;11;4;7;24
CHECKSUM: 621B7BECF1704948760EACCCB92816F9
PRODUCT: Communications Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 if UPL &gt; DFL - 10 saturatedUPL = DFL - 10; else saturatedUPL = UPL end  The sample rate of the input sequence must be 32 times the symbol rate that is set on the Stream Recovery subsystem.  Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Add;BB Decoder;BB Demultiplexer;BB Descrambler;BB Header CRC Check;Bit Concat;Bit Index;CCMorACM;Compare To Constant;Constant;DFL;Data Type Conversion;Data Type Duplicate;Delay;Demux;Discard CRC failed Frame;Distance;Enable;Extract BBHeader;Extract Bits;Extract DFL;Extract Data Field;Extract MATYPE;Extract SYNC;Extract SYNCD;Extract Stream;Extract UPL;Extract User Packet ;Gain;General CRC Syndrome Detector HDL Optimized;HDL Counter;Hit;ISSYI;In;Indicate SYNCD bit;Insert SYNC;Logical Operator;MIS_ISI;Multiport Switch;NPD;Out;PN Sequence Generator;RO;Reference;Relational Operator;SISorMIS;SYNC;SYNCD;Sample Discard Control;Saturate UPL value;Stream Recovery;SubSystem;Subsystem;Subtract;Switch;TSorGS;Terminator;UPL;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;User Packet CRC Check;Variable Count Limited HDL Counter;bitsIn;bitsOut;countToValue;dValidIn;dValidOut;dataIn;dataOut;dbitsIn;dbitsOut;dstartIn;dstartOut;dvalidIn;enb;endIn;endOut;err;errIn;errOut;errorOut;errorValid;frameEnd;frameSrt;frameStart;hbitsIn;hbitsOut;headerCRCInfo;hendIn;hendOut;herrorIn;herrorOut;hstartIn;hstartOut;hvalidIn;hvalidOut;idx;invalidIn;invalidOut;invalidPkt;pktErr;reset;rst;saturatedUPL;startIn;startOut;trigger;validIn;validOut

BLOCKTYPE:
Bit Concat;Compare To Constant;Constant;DataTypeConversion;DataTypeDuplicate;Delay;Demux;EnablePort;Extract Bits;Gain;General CRC Syndrome Detector HDL Optimized;HDL Counter;Inport;Logic;MultiPortSwitch;Outport;PN Sequence Generator;RelationalOperator;S-Function;Sum;Switch;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous


MODELNAME: dvbs2hdlSyncPLHeaderRecoveryCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlSyncPLHeaderRecoveryCore.slx
CHECKSUM: B9D1DA0B44F06FB947ED42B63F80C6EE
PRODUCT_BASECODE: LH
ANNOTATION:
 force MODCOD to 0 until synchronization is done  Set this value to zero to disable correction  Let Z be the complex phase estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z))  Wrap on overflow with data type signed and 1 intergral bit will wrap the output to lie in between -1 to 1 Differential Detection Compute Energy Compute Energy Compute Energy  The initial output of these outports are set to 0 as this is an enabled subsystem Hold pilotEnable signal Hold pilotsEnable signal after endOfPLSC Proportional-Plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence  The sample rate of the input ports must be four times that of the symbol rate set on the Synchronizer and PL Header Decoder subsystem as the model works only for four samples per symbol.   Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;Add;AddADn;AddAUp;AddBCtr;AddBDn;AddBUp;Bias;Bit Concat;Bit Flipping and Averaging;Bus Creator;CWswitch;Coarse Frequency Estimator;Coarse Phase Corrector;Coarse Phase Estimator;Coarse Phase Synchronizer;Code Word LUT 1 to ;Code Word LUT 33 to ;Compare To Constant;Complex Multiplier;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Compute Euclidean Distance;Compute R(m) for 1 to ;Compute R(m) for 13 to ;Compute R(m) for 7 to ;Compute R(m)_;Constant;Corr Add;Corr Subtract;Correlator;CwEdMetric;Data Type Conversion;Data Type Duplicate;Delay;Delta;Demux;Direct Digital Synthesis;Discrete FIR Filter;Divide by ;Downsample;E;Ed;En;Enable;Enable MODCOD ;Euclidean Distance Sum Up;Extract Bits;FEC;FECFrame;FIFO;Fine Frequency Synchronizer;Fine Gain Control;Fine Phase Synchronizer;For Each;For Each Subsystem;Frame Synchronizer;Frequency Error Detector;From;Function Impl;GTED;Gain;Gardner TED;Get Min Index;Goto;HDL Counter;In;Input Sample Counter;Integer Delay;Integer to Bit Convertor;Integrator Gain;Interpolation Control;Interpolation Filter;K;L and R Algorithm 18 point;LS;LUT;LUTAddr;Logical Operator;Loop Filter;MATLAB Function;ML Decoder;MS;Math Function;Modified L and R Algorithm;Moving Average;Moving Average ;Moving Sum;Multiport Switch;Mux;NCO HDL Optimized;No HDL;No HDL Correlation Value;Out;PL Data Descrambler;PL Data Descrambler and Pilot Valid Indicator;PL Frame Demultiplexer;PL Header Decoder;PL Header Recovery;PL Scramble Sequence Mapper LUT;PL Scrambler Gold Sequence Generator;PLSC Correlator;PLSC Descrambler;PLSC Valid Counter;PLSCCorr;PLSCCorrOut;PLSCDiag;PLSCValid;PeakValueWithPilots;PeakValueWithoutPilots;Phase Error Detector;Pilot Blks Counter;Pilot Valid Indicator;Pilot and Sync Pulse Indicator;PilotIdx Counter;Power Q and Beta Offset Rotation;PrevEst;Product;ProductCtr;ProductDn;ProductUp;RRC Receive Matched Filter;Rate Handle;Real-Imag to Complex;Reciprocal;Reference;Relational Operator;Repeat;SOF Correlator;SOFCorrDelayed;SOFCorrOut;Simple Dual Port RAM;Source Encoding;SubSystem;Subsystem;Sum;Switch;Symbol Synchronizer;Synchronizer and PL Header Decoder;Terminator;Threshold Scaling;ThresholdLimiter;Time Frequency and Coarse Phase Synchronizer;Time and Coarse Frequency Synchronizer;To Workspace;Underflow;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Unwrapping algorithm;Upsample;ValueOut;Variance Estimator;VisualizeCorrelationSignals;X PN Generator M_n;X PN Generator M_nplus;Y PN Generator M_;avgOut;bits6Out;complexEst;complexEstimate;currentEst;dValid;data;dataIn;dataOut;diagBus;e;empty;enable;enb;enbMODCOD;endOfPLSC;endOfPLSCIn;endOfPLSc;endOfSOF;endOfSOFIn;estOut;estValid;estimate;finePhaseEn;forBit;full;functionValues;hValid;has Pilots;hasPilots;headerInfo;idxIn;idxOut;indexIndicater;indexIndicator;indexIndicatorIn;indexIndicatorOut;indices;inputCount;interpolant;isdummy;mod;modcod;modcodOut;monostable;mu;normCoaFreqEst;normFineFreqEst;normFreqEst;normalizedEst;out;outValid;pi/2 BPSK Soft Bit Generator;pilotBlkCount;pilotConstel;pilotEnable;pilotIdx;pilotIdxOut;pilotValid;pilotValidIn;pilotValidOut;pilotidx;pop;push;rd;reset;resetIn;resetOut;rst;rstCCFO;rstFCPO;rstOut;scaled;softBit;strobe;sum;switch;symbSyncDataOut;symbSyncValidOut;synbSyncDiag;threshold;thresholdExceeded;trigger;u;v;valid;validIn;validOut;valueIn;varOut;wr;x;xMn;xMnp;xph;y;yM;z;zvalid

BLOCKTYPE:
Bias;Bit Concat;BusCreator;Compare To Constant;Complex to Magnitude-Angle;ComplexToRealImag;Constant;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;DownSample;EnablePort;Extract Bits;ForEach;From;Gain;Goto;HDL Counter;Inport;Logic;LookupNDDirect;Lookup_n-D;Math;MultiPortSwitch;Mux;NCO;Outport;PN Sequence Generator;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample

BLOCKTYPE_FREQUENCY:
1;1;7;59;3;58;25;60;29;2044;17;3;6;3;25;14;127;42;54;29;293;69;6;2;30;7;11;4;230;4;91;25;8;2;5;1;178;26;16;2;26;34;4

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;Wireless HDL Toolbox


MODELNAME: dvbs2hdlTransmitter
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlTransmitter.slx
ANNOTATION: Copyright 2022-2023 The Mathworks, Inc. DVB-S2 HDL Transmitter
BLOCKTYPE_FREQUENCY: 6;8;12;4;3;3;2;2;37;10;2;1;37;2;3;1;3;6;1;1;3;6;3;1;6
CHECKSUM: 6A795A7F413A4852E77439481CC8D071
PRODUCT: DSP System Toolbox;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: dvbs2hdlTransmitterCore.slx___Model_Block___
BLOCK:
 Demux ; SFunction ; Terminator ;Capture Data;Compare To Constant;Constant;Control Scope;Controller;DFL;DFL Normal;DFL Short;DFL Store;DVB-S2 HDL Transmitter;Data Bits;Data Type Conversion;Delay;Divide;Enable;Extract Bits;FECFrame;Floor;Frame Control Signal Generator;GScontEnd;HDL Counter;In;Input Configuration;Logical Operator;MODCOD;Out;Outport;Packet Control Signal Generator;Parameters;Product;Reference;Relational Operator;SYNC;Signal From Workspace;Spectrum Analyzer;Stop Simulation;SubSystem;Subsystem;Subtract;Subtract One;Switch;TSorGS;To Workspace;UPL;Unit Delay Enabled Synchronous;bitsPerFrame;count;countToValue;dataOut;dvbs2hdlTransmitterCore;enb;endOut;fecframe;flag;frameEndIn;frameStartIn;modcod;nFrames;nextFrame;out;pDFL;pFECFrame;pFrameEndIn;pFrameStartIn;pMODCOD;pPktBitsIn;pPktEndIn;pPktStartIn;pPktValidIn;pSYNC;pTSorGS;pUPL;pktBitsIn;pktEndIn;pktStartIn;pktValidIn;rst;startOut;sync;takePktEnd;trigger;tsorgs;u;upl;valid;validOut

BLOCKTYPE:
Compare To Constant;Constant;DataTypeConversion;Delay;Demux;EnablePort;Extract Bits;HDL Counter;Inport;Logic;Lookup_n-D;ModelReference;Outport;Product;RelationalOperator;Rounding;S-Function;Signal From Workspace;SpectrumAnalyzer;Stop;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Synchronous


MODELNAME: dvbs2hdlTransmitterCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/dvbs2hdlTransmitterCore.slx
CHECKSUM: 7C7D6032CE5910A948380B277CA56461
PRODUCT_BASECODE: LH
ANNOTATION:
Input Sample Bus Controller  Compare input frame length with read Counter   Compare input frame length with write Counter  Sample Frame type and code rate and calculate framelength Write address generation for the input data bits Read address generation for the stored input bits Output data and control generation Next frame output port generation  Compare message plus parity length with output read Counter which reads the stored message and parity bits.   Compare input frame length with input bit Counter without delay Read address generation for the parity bits  Compare parity length with parity read Counter for resetting parity read counter   Compare parity length with parity read Counter to read the stored parity bits.  write and read input data using RAM  Compare input frame length with read Counter  Shift by 256 Shift by 128 Shift by 64 Shift by 32 Shift by 16 Shift by 8 Shift by 4 Shift by 2 Shift by 1 Selection signals  shiftLUT = (parity length - (Parity bit address - ramLUT))/qFactor)  ramLUT = remainder (Parity bit address spcified in standard, qFactor) columnLUT gives total number of columns in each row of a parity bit addresses Connect these line to Time scope to visualize signals  For Deinterleaver :  Offset Address : Each ramp signal in the time scope indicates a column pickup. 1,3,4,5 ramp signals in constant base address index indicates a frame demodulated from QPSK, 8 PSK, 16 APSK, 32 APSK symbols respectively. The height of the ramps indicates a normal or a short frame  This subsystem is a copy of Wrap Address subsystem in the RAM subsystem  Base Address Index: Remains constant till the end of the frame. changes by 1 after every short and by 4 after every normal frame Read Ports Write Ports  The initial output of these outports are set to 0 as this is an enabled subsystem  Copyright 2022 The Mathworks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;16x;8x;90x;AND;Add;Assertion;BB Frame Generator;BB Header CRC Generator;BB Header Generator;BB Header Packetizer;BB Header and Data CRC Generator;BB Scrambler;Bi Orthogonal Coding (32,6);Bit Concat;Bit Slice;Bitwise Operator;Bus Selector;Circular Shifter;Compare To Constant;Compare To Zero;Compute Read Offset Address;Constant;Continuous Streams;Control Logic;ConvertToMux;ConvertToWord;DFL;DFLOut;DVB-S2 BCH Encoder;DVB-S2 HDL Interleaver;DVB-S2 LDPC Encoder;DVB-S2 Symbol Modulator;DVB-S2 Tx;Data Field Generator;Data RAM;Data Store FIFO;Data Type Conversion;Data Type Duplicate;Delay;Discard Out of Frame samples;Discard SYNC;Discrete FIR Filter;Display;Downsample;Dual Port RAM System;Dummy Frame Generator;Dummy Frame Header LUT Address Generator;Dummy Frame Normal Header;Dummy Frame Short Header;EOF;Enable;Extract Bits;FEC Encoder;FECFrame;FECFrameIn;FECFrameOut;FIFO 3 Variables;Fec Frame FIFO;For Each;For Each Subsystem;Frame Length;Frame Length FIFO;From;Gain;Generate Signal for End of Frame;Generate and Add Read Base Address;Goto;HDL Counter;Header Bits Packer;In;In Frame Count;Indexing;Indicate End of Every ShortFrame Length Samples;Input RAM;Input bit Count;Input bit Count without delay ;Input controller;Integer to Bit Convertor;Interleaver;LUTAddr;Logical Operator;MATLAB Function;MODCOD;MODCOD Source Coder;MODCODIn;MODCODOut;MaxC LUT;MaxR Normal LUT;MaxR Short LUT;Multiplexer;Multiport Switch;Mux;NOT;No HDL;No HDL Read Address Debug Scope;Normal Frame xFECFrame Length;OR;Out;Out Frame Count;Output Controller;Output Counter;PL Data FIFO;PL Data Scrambler;PL Frame Generator;PL Header Bits Generator;PL Header FIFO;PL Header Generator;PL Scramble Sequence Mapper LUT;PL Scrambler Gold Sequence Generator;PLHeaderEnd;PLSC Generator;PLSC Scrambler;PLSC Valid Counter;PN Sequence Generator;Packetized Streams;Parameter Store FIFO;Parity Address Generator;Parity Generation;Parity RAM;ParityCalCompFlag;ParityController;Pilot Block Length Valid Generator;Pilot Generator;Pilot or Unmodulated Carrier;Priority Encoder;Product;RAM;RAM Address Generator;RAM FIFO;RAM status;RRC Transmit Filter;Read Offset Address;Read Offset Address Signals Generator;ReadVal Address;Reference;Relational Operator;Repeat;SOF Generator;SOF Sequence;SOF Sequence LUT Address Generator;SYNC;Sample Control Bus Creator;Sample Control Bus Selector;Sample Frame type and code rate;Selector;Serialize on trigger;Short Frame xFECFrame Length;Signal Specification;Simple Dual Port RAM;Single RAM Using Two RAMs;Store and Retreive Input;Store and Retrieve Parity;SubSystem;Subsystem;Subtract;Switch;Symbol Modulator;TSorGS;Terminator;To Workspace;UPL;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;User Packet CRC Generator;Wrap Address;Write Base plus Offset Address;Write Offset Address;Write Offset Address Normal Frame;Write Offset Address Short Frame;WriteVal Address;X PN Generator M_n;X PN Generator M_nplus;XOR;Y PN Generator M_;addr;addridx;baseAddrIdx;basePlusOffsetAddr;bit;bits1to;bitsEnd;bitsIn;bitsOut;bitsStart;bitsValid;bitsValidIn;captureBaseAddrIdx;captureIn;captureOut;chkwrAddrEnd;cnt;cntval;cod Idx FIFO;codIdx;codIdxIn;codIdxOut;codIdxReg;codOut;codeRateIdx;codeRateIdxIn;coderate;columnCounter;columnsLUT;convertMODCOD;countOut;countToValue;ctrlIn;ctrlOut;curC;curCorROut;curR;curRorCOut;data;data16SlotsEnd;dataBits;dataEnd;dataIn;dataOut;dataValid;datai;done;dummyData;dummyHeaderEnd;dummyHeaderSrt;dummyValid;dvalid;empty;enb;enbBCHEnc;encenable;encend;endAppend;endEnc;endIn;endIndicate;endOf16Slots;endOfPLHeader;endOfPLSC;endOfPilotBlk;endOfPlheader;endOut;endOut16Slots;endOutFrame;endOutFramem;endOutm;endi;endo;fec;fecFrame;fecFrameIn;fecFrameOut;fecOut;fecframe;fecframeIn;fecframeReg;flag;framLenDelay;framLenDelayed;frameEnd;frameEndIn;frameEndOut;frameLen;frameLength;frameStart;frameStartIn;frameStartOut;frameType;frameTypeIn;frametype;framevalid;full;headerBits;headerEnd;headerStart;headerValid;hvalid;i_index;in_data;indexLUT;inpFrameLength;inpLen;inpLenLUT;inpParityLength;input;input bit read counter;inputController;ird_addr;ird_data;ird_valid;isMODOCD;iwr_addr;iwr_data;iwr_enb;lutIdx;maxC;maxR;maxR_switch;maxRorCOut;modIdx;modIdxIn;modIdxOut;modIdxReg;modIn;modOut;modcod;modcodIs;modcodIs12Out;modcodis;modidx;nFramesInRAM;nRowLUT;nRows;nRows and nColumns;ncount;nextFrame;nextFrameReady;noofColumnsLUT;noofcol;nxtFrame;offsetAddr;outCtrl;outData;outRd_valid;outputMsg;outputParity;outrd_data;pFECFrame;pMODCOD;p_index;parLen;parLenLUT;par_data;par_ind;paraddr;paramValid;parity;parity Input Binary flag;parity RAM;parity bit read counter;parity indexing;parityAddr;parityBitsVector;parityIndex;parityLength;parityScalarOut;parityScalarValid;parityScalarValidOut;parityValid;parityValidVector;parityVectorInp;piby2 BPSK Modulator;pilotActive;pilotData;pilotEnd;pilotValid;pilotdata;pktBits;pktBitsIn;pktEndIn;pktStartIn;pktValid;pktValidIn;plheaderData;plheaderEnd;plheaderStart;plheaderValid;pop;prd_addr;prd_data;proper Input Binary flag;push;pwr_addr;pwr_data;pwr_enb;qFactorLUT;qfactor;ramLUT;rd;rdEnb;rd_addr;rd_dout;rd_end;rd_endOut;rd_start;rd_startOut;rd_valid;rd_validOut;rdenable;rdy;readAddr;readAddrIn;readAddrOut;readDataOut;readEnd;readEndOut;readInpData;readInpValid;readStart;readStartOut;readVal;readValid;readValidIn;readValidOut;ready;readyNxtFrame;reset;resetIn;resetOut;rowCounter;sample bus controller function;sampledEndIn;sampledStartIn;shift;shiftData;shiftLUT;shiftVal;slotsData;slotsValid;start;startIn;startOfPlheader;startOfSOF;startOut;startOutFrame;starti;starto;trigger;u;unitFrameLen;update parity bits;vMODCODis;vMaxC;vMaxR;vModCodIs;valid;validAppend;validCodeRate;validIn;validMsg;validOut;validParity;validateFrameFlag;validi;validm;valido;vld;wr;wrAddr;wrEnb;wr_addr;wr_din;wr_en;writeAddr;writeEnable;writeVal;x;xFECFrameLength;xMn;xMnp;y;yM

BLOCKTYPE:
Assertion;Bit Concat;Bit Slice;Bitwise Operator;BusSelector;Compare To Constant;Compare To Zero;Constant;DVB-S2 Symbol Modulator;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;DownSample;EnablePort;Extract Bits;ForEach;From;Gain;General CRC Generator HDL Optimized;Goto;HDL Counter;Inport;Logic;Lookup_n-D;MultiPortSwitch;Mux;Outport;PN Sequence Generator;Product;RelationalOperator;Repeat;S-Function;Sample Control Bus Creator;Selector;SignalSpecification;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;hdl.RAM

BLOCKTYPE_FREQUENCY:
17;2;9;1;2;25;1;27;1;33;9;519;35;1;8;7;3;15;6;22;2;2;15;32;502;113;20;5;15;395;5;3;14;4;35;3;22;2;15;10;40;56;1;4;38;3;4

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox


MODELNAME: nrhdlCORESET0Decoding
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlCORESET0Decoding.slx
BLOCKTYPE_FREQUENCY: 1;1;2;3;15;2;6;1;15;1;1;9
CHECKSUM: B106216C12D84A39095B66D05C683392
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: nrhdlCORESET0DecodingCore___Model_Block___nrhdlPolarDecodingChainCore___Model_Block___
ANNOTATION:
 NR HDL CORESET0 Decoding Copyright 2021-2022 The MathWorks, Inc.  Signals from workspace  Signals to workspace

BLOCK:
Bus Selector;CORESET0 Decoding;Delay;Diagnostics to workspace;Enable;NCellID;NSlot;NSym;Polar CoProcessing;Reference;Sample Control Bus Creator;Signal From Workspace;Signal Specification;Stop Simulation;SubSystem;To Workspace;Vector Concatenate;baseRBIdx;coreset0RBs;coreset0Syms;data;dciDataOut;dciValid;demodData;diagnostics;firstOrSecondSlot;gridCtrlIn;gridDataIn;nextFrame;numSlots;qpskSymb;rateRecData;restart;searchFailed;searchSpaces;status;sym

BLOCKTYPE:
BusSelector;Concatenate;Delay;EnablePort;Inport;ModelReference;Outport;Sample Control Bus Creator;Signal From Workspace;SignalSpecification;Stop;ToWorkspace


MODELNAME: nrhdlCORESET0DecodingCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlCORESET0DecodingCore.slx
ANNOTATION: Copyright 2021-2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 5;2;1;2;1;5;8;2;6;2;30;4;2;16;4;3;4;2;64;18;4;1;1;34;1;1;2;1;1;3;2;3;3;2;1;5;1
CHECKSUM: 061B982187A334C9D08012582D8CF100
PRODUCT: Communications Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Add;Bit Concat;Bit Reduce;Bit Shift;Bitwise Operator;Bus Creator;Bus Selector;Cast;Compare To Constant;Constant;D;Data Type Conversion;Decrement Real World;Delay;Demux;E;Enable;Equal;Extract Bits;From;Gain;Generation Control;Goto;HDL Counter;Increment Real World;Init;LFSR;Load;Logical Operator;MATLAB Function;Multiport Switch;NCellID;NR Gold Sequence Generator;NSlot;NSym;OR;Out;PDCCH DMRS Generation;Plus;Product;Q;Real-Imag to Complex;Reference;SetFF;Signal Specification;State Control;SubSystem;Switch;Symbol Generation;Tapped Delay;Terminator;Unit Delay Enabled Synchronous;Vector Concatenate;baseRBIdx;cInit;cInit calc;coreset0RBs;coreset0Syms;coresetDone;coresetErr;dciData;dciValid;decodeChainDiagnostics;decodeChainInput;decodeChainOutput;decodeChainStatus;decodeDone;decodeErr;demodDone;diagnostics;dmrsCInit;dmrsData;dmrsShiftIdx;dmrsValid;dmrsValidIn;enable;errIn;firstOrSecondSlot;getDimension;gridCtrl;gridData;isDMRS;load;loadDMRS;mask;mask1_const;mask2_const;n-D Lookup Table;nextFrame;numSlots;rateRecDone;rbSubcarrier;regBundleRBSizeInFreq;restart;searchFailed;searchSpaceControl;searchSpaces;shiftIdx;shiftMask;shiftMasks;shiftMasksConst;shiftMasksLookup;start;startDecode;status;status FSM;u;validIn;validOut;y

BLOCKTYPE:
Bit Concat;Bit Reduce;Bit Shift;Bitwise Operator;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;DataTypeConversion;Delay;Demux;EnablePort;Extract Bits;From;Gain;Goto;HDL Counter;Inport;Logic;Lookup_n-D;MultiPortSwitch;NR Gold Sequence Generator;Outport;Product;Real World Value Decrement;Real World Value Increment;RealImagToComplex;RelationalOperator;S-Function;SignalSpecification;StateControl;Sum;Switch;Tapped Delay Line;Terminator;Unit Delay Enabled Synchronous


MODELNAME: nrhdlDDCCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlDDCCore.slx
BLOCKTYPE_FREQUENCY: 5;29;4;1;6;3;52;2;48;2;4;4;1;5;5
CHECKSUM: AB331D6F893ED33128A71A43BFED3DC0
PRODUCT: DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
Cast to 16 bits for subsequent processing. Attenuate input signal by a small amount to prevent saturation due to small gains in passband (ripple) in filters further down the chain.  Multiply by 0.5 by simply reinterpreting the sfix16_En15 as an sfix16_En16. Match the latency of the HDL FIR used to implement polyphase filter 0. Input data type must be sfix16_En15 Copyright 2021-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Add;Centre Tap;DDCCore;Data Type Conversion;Delay;Enabled Delay;FIR ;FR;FR1 + FR;Filter and Downsample;Frequency Correction;Gain;Grid DDC;Input Scaling;NCO HDL Optimized;Polyphase Decimator;Product;Reference;SSB DDC;Stage ;State Control;SubSystem;Terminator;Transient Removal;Unit Delay Enabled Synchronous;dataIn;dataOut;frequencyOffset;gridData;gridFrequencyOffset;gridValid;phase;ssbData;ssbFrequencyOffset;ssbValid;validIn;validOut

BLOCKTYPE:
DataTypeConversion;Delay;Demux;Discrete FIR Filter;FIR Decimator;Gain;Inport;NCO;Outport;Product;S-Function;StateControl;Sum;Terminator;Unit Delay Enabled Synchronous


MODELNAME: nrhdlGridDemodulationCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlGridDemodulationCore.slx
BLOCKTYPE_FREQUENCY: 6;34;3;2;17;5;6;3;39;14;82;9;3;27;8;286;8;54;39;1;157;7;3;9;1;3;20;8;24;2;5;1
CHECKSUM: 55877DD8E32A7151BA63D49C58ECCA8E
PRODUCT: DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
adjust backwards from subsequent half subframe to slot half subframes are always 0.5ms convert slot @ scsCommon to half subframe for FR1 every slot is on a half subframe boundary Starting at the frame head means we are always on NSlot 0 Do not apply the CORESET0 offset if were doing a wideband grid demod. This sets the timing reference to the framehead containing the detected SSB. In wideband mode convert the timing reference from the 20ms SIB1 period to the 10ms period of system frames.  Adjust RB Offset by 1 if Kssb &gt; 0 for the following Tables and Indices: Table Index SCS {120,60} 13-7 8 SCS {120,60} 13-7 10 SCS {120,120} 13-8 4 SCS {120,120} 13-8 6 SCS {240,120} 13-10 4 SCS {240,120} 13-10 6 For FR2 Kssb is in units of scsCommon (60 or 120 KHz) first symbol in a demod needs to be initialized, subsequent symbols are incremented by FFTLen + cpLen Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;2-D Lookup Table;AND;Add;Align Latency;Align Symbol End;Apply Phase Post-Compensation;Bit Concat;Bit Slice;Bitwise AND;Bus Assignment;Bus Creator;Bus Selector;CORESET 0 Occasion;CORESET 0 Resources;CORESET 0 Sample Offset;CORESET0 MUX Pattern ;CPFraction;CPLen;CPLenIn;Cast;Cast To Boolean;Compare To Constant;Configuration;Constant;Data Type Conversion;Delay;Enabled Delay;Equal;FFT Scale;FFTLen;FFTLenIn;FFTScale;FIFO;FIR Decimator;FR;FR1 + FR;FR1+FR;FRSel;FSym LUT;FSym SCS 120 / 120 LUT;FSym SCS 120 / 60 LUT;FSym SCS 240 / 120 LUT;Frame Modulo;Frequency Offset Unit Conversion;Gain;GreaterThanOrEqual;Grid Frequency Offset;Grid Resource Blocks;Grid SCS;Grid Timing Offset;GridDemodulationCore;HDL Counter;Half Subframe Slot;In Bus Element;Initialization;Kssb;Kssb Adjust;KssbFrequency;Lmax;M LUT;MIB;Multiport Switch;NSlot;No FR;O LUT;OFDM Controller;OFDM Demod;OFDM Demodulator;OR;Offset Shift;Parameter Lookup;ParseMIB;Phase Post-Compensation;Product;Reference;SCS 120 Timing Reference;SCS 15 Halfband Decimator;SCS 15 Timing Reference;SCS 30 Halfband Decimator;SCS 30 Timing Reference;SCS 60 Halfband Decimator;SCS 60 Timing Reference;SCS Selection;SIB1 Config;SSB Sample Offset;Simple Dual Port RAM System;Stage ;State Control;SubSystem;Subcarrier Spacing Selection;Subtract;Switch;TRef;Terminator;Timing Reference Modulo;Transient Removal;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Vector Concatenate;Zero;busIn;busOut;clearStatus;coreset0Occasion;coreset0Resources;coreset0Sample;cpLen;data;dataIn;dataOut;dataValid;demodEn;exp HDL Optimized;frequencyOffset;frequencyOffsetIn;frequencyOffsetOut;gridData;gridStatus;gridTimingRef;gridValid;halfSubframe;halfSubframeSlot;halfSubframeSlotIn;idx;kSSBFrequency;kSSBNonZero;kssbRBOffset;longCPDelta;longCPFraction;longCPLen;longCPLenDelta;minChanBW;mode;muxPattern;nrbGrid;numGSc;numGScIn;numGsc;ofdmDemodController;ofdmStart;ofdmSymbols;ofdmValid;offset;params;parsedMIB;pbchPayload;pdcchConfigSIB;pdcchConfigSib;phaseComp;phaseTermInit;pop;push;rbOffsetGrid;resourceBlocks;rst;samplesPerSlot;scaleFactor;scs;scs120Data;scs120TRef;scs120Valid;scs15Data;scs15TRef;scs15Valid;scs30Data;scs30TRef;scs30Valid;scs60Data;scs60TRef;scs60Valid;scsCommon;scsGrid;scsIn;scsOut;scsPair = [120 120];scsPair = [120 60];scsPair = [15 15] minChanBW = 5 / 10 / ;scsPair = [15 30] minChanBW = 5 / 10 / ;scsPair = [240 120];scsPair = [240 60];scsPair = [30 15] minChanBW = ;scsPair = [30 15] minChanBW = 5 / ;scsPair = [30 30] minChanBW = ;scsPair = [30 30] minChanBW = 5 / 10 ;scsSSB;sib1Data;sib1Present;sib1Valid;slotOffset;slotOffset SCS 120 / ;slotOffset SCS 240 / ;ssbIdx;ssbIndex3Lsb;ssbPattern;ssbSample;ssbTimingOffset;start;startOFDM;status;stopDemod;symEnd;symStart;tRef;tRefAdjust;tRefIn;tRefModulo;targetOffset;timingRefIn;timingRefOut;timingUpdate;timingUpdateValid;valid;validIn;validOut

BLOCKTYPE:
Bit Concat;Bit Slice;Bitwise Operator;BusAssignment;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;DataTypeConversion;Delay;Demux;FIR Decimator;Gain;HDL Counter;Inport;Logic;Lookup_n-D;MultiPortSwitch;OFDM Demodulator;Outport;Product;RelationalOperator;S-Function;Sine and Cosine HDL optimized block;StateControl;Sum;Switch;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;hdl.RAM


MODELNAME: nrhdlLDPCDecodingChainCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlLDPCDecodingChainCore.slx
ANNOTATION: Copyright 2021-2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;2;1;4;2;2;8;1;1;10;3;47;3;2;5;112;20;1;1;7;1;1;56;1;1;11;3;2;1;1;13;7;5;5;1
CHECKSUM: D05BC1E3648A660580517094CFD361FC
PRODUCT: DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Abs;Add;Add Constant;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Compute Odd Idx Start;Config;Constant;Data Type Conversion;Decrement Real World;Deinterleave Indices;Deinterleave and Soft Combine;Delay;Enable Maximum Comparison;Equal;Even Transpose Indices;Filler Bits;G;Gain;GreaterThan;GreaterThanOrEqual;HDL Counter;In Bus Element;Input Control;K;Kd;L;LDPC Decoding Chain;LDPC Rate Recover;Less Than;Logical Operator;MSSB;Maximum;Multiport Switch;NOT;NR CRC Decoder;NR LDPC Decoder;NcbSub;NcbSubF;OR;Odd Transpose Indices;One;Out;Output Control;Product;Rate Recover;Reference;Running Maximum;Sample Control Bus Creator;Sample Control Bus Selector;Saturation;Shift Arithmetic;Signal Specification;Single Port RAM System;Soft Combining;Soft Scaling;SubSystem;Subtract;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Vector Concatenate;XOR;Zc;apply scaling;blkLen;cfg;clearStatus;coarseGain;compute scaling gains;crcDone;crcErr;crcStart;create diagnsotics bus;ctrlIn;ctrlOut;dataIn;dataOut;diagnostics;done;enable;endIn;endOut;feedbackEn;feedbackEnable;fineGain;gIn;indicesOut;infoBits;isFiller;k;k0In;kmssb;ldpcCtrl;ldpcData;ldpcStart;ldpcZc;liftingSize;maxEnable;maxIn;oddIdxStart;outputAddr;outputCtrl;outputEn;outputting;ramDataIn;ramDataOut;ramWriteAddress;ramWriteEnable;rateRecoverData;rateRecoverValid;remove padding bits;reset;restart;runningMax;scaledData;scalingData;scalingValid;sib1Bits;sib1BitsCtrl;sib1Err;start;startIn;startOut;status;status FSM;tbs;transposeEn;transposeInd;trblklen;trblklenIn;validIn;validMax;validOut;zcIn

BLOCKTYPE:
Abs;ArithShift;Bias;Bit Concat;Bit Shift;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;DataTypeConversion;Delay;Demux;Gain;HDL Counter;Inport;Logic;Lookup_n-D;Maximum;MultiPortSwitch;NR CRC Decoder;NR LDPC Decoder;Outport;Product;Real World Value Decrement;RelationalOperator;S-Function;Sample Control Bus Creator;Saturate;SignalSpecification;Sum;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;hdl.RAM


MODELNAME: nrhdlMIBRecovery
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlMIBRecovery.slx
BLOCKTYPE_FREQUENCY: 4;13;2;5;2;7;3;4;1;1;1;1;27;4;5;28;11;7;24;1
CHECKSUM: 1B360F88769E0562624A271AC5A64C68
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 Signals from workspace  Parse the PBCH Payload to obtain parameter values  NR HDL MIB Recovery  Signals to workspace Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;Cast To Boolean;Compare To Constant;Constant;DDC;Delay;Detect Decrease;Enable;From;Goto;Kssb;Lmax;MIB Recovery;Multiport Switch;NCellID;ParseMIB;Polar Decoding Chain;Reference;SSB Decoding;SSB Detection;Signal From Workspace;SubSystem;Subsystem;Terminator;To Workspace;Unit Delay Enabled Synchronous;Zero;bchStatus;cellBarred;convert bus;dataIn;detectionStatus;dmrsTypeAPos;dmrsTypeAPosition;enumToValue;frequencyOffset;frequencyRange;hrf;in;intraFreqResel;intraFreqReselect;mode;out;pbchPayload;pbchStatus;pssCorrelation;pssFrequencyOffset;pssNCellID;pssThreshold;pssTimingOffset;reportValid;scsCommon;scsCommonEnum;sfn;sib1Config;ssbDecodeValidOut;ssbGrid;ssbGridValid;ssbIndex;ssbIndex3LSb;ssbIndex3Lsb;sssCorrelation;sssThreshold;start;stopDemod;subcarrierSpacing;timeOut;timingOffset;validIn

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;Constant;DataTypeConversion;Delay;Detect Decrease;EnablePort;From;Goto;Inport;ModelReference;MultiPortSwitch;Outport;Signal From Workspace;Terminator;ToWorkspace;Unit Delay Enabled Synchronous

EXTERNALFILE_REFERENCE:
nrhdlDDCCore___Model_Block___nrhdlPolarDecodingChainCore___Model_Block___nrhdlSSBDecodingCore___Model_Block___nrhdlSSBDetectionCore___Model_Block___


MODELNAME: nrhdlPolarDecodingChainCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlPolarDecodingChainCore.slx
ANNOTATION: total input count input count mod N Copyright 2021-2022 The MathWorks, Inc.
CHECKSUM: 82D7FFF0B4615BE075E7BEF38761C04B
PRODUCT: Communications Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Abs;Add;Apply Scaling;Bit Concat;Bit Reduce;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;Cast;Channel Est + Equalize;Compare To Constant;Complex to Real-Imag;Compute Scaling;Configuration;Conj;Constant;Construct Sample Control;Controller;D;Data Type Conversion;Decode Status;Decrement Real World;Delay;Demod + Descramble;Demux;Detect Decrease;Detect Increase;E;ELtN;ESubN;EltN;Enable;Equal;Extract Bits;Framing;From;Gain;Goto;GreaterThan;HDL Counter;In Bus Element;Init;K;K/E<=7/;LFSR;Less Than;Load;Logical Operator;MATLAB Function;MSSB;Maximum;Min;Multiply;Multiport Switch;N;NOT;NR Gold Sequence Generator;NR Polar Decoder;NSub;NSubE;OFDM Channel Estimator;OR;Out;Polar Decoding Chain;Polar Rate Recover;Product;Q;Rate Recover;Reference;Relational Operator;Sample Control Bus Creator;Saturation;SetFF;Shift Arithmetic;Signal Specification;Single Port RAM System;Soft Scaling;State Control;SubSystem;Subtract;Switch;Terminator;Unary Minus;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Vector Concatenate;addr;addrIn;addrOut;bchStatus;cInit;ceilLog2E;ceilLog2K;cl2e;cntE;coarseGain;coarseScaling;create diagnsotics bus;ctrlIn;ctrlOut;cwSize;dataIn;dataOut;decodeChainIn;decodeChainOut;decodeDone;deitlvAddr;demodData;demodDone;demodValid;diagnostics;dmrsData;dmrsValid;enable;eqData;eqSym;eqSymValid;eqValid;fineGain;fineScaling;frameRd;frameWr;getDimension;hEstSym;itlvAddr;kmssb;load;mask;mask1_const;mask2_const;maxIn;n;order;phase equalization;punc;puncOffset;rateRecDone;rateRecoverData;rateRecoverValid;reset;rmPuncIdx;rmShortIdx;rxSym;scPerSym;scalingData;scalingValid;shiftIdx;shiftMask;shiftMasks;shiftMasksConst;shiftMasksLookup;shortPuncSel;shortenOrPunctureBits;softBits;softBitsValid;start;status;symValid;u;validIn;validOut;y

BLOCKTYPE:
Abs;ArithShift;Bit Concat;Bit Reduce;Bit Slice;Bitwise Operator;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Decrease;Detect Increase;EnablePort;Extract Bits;From;Gain;Goto;HDL Counter;Inport;Logic;Lookup_n-D;Math;Maximum;MinMax;MultiPortSwitch;NR Gold Sequence Generator;NR Polar Decoder;OFDM Channel Estimator;Outport;Product;Real World Value Decrement;RelationalOperator;S-Function;Sample Control Bus Creator;Saturate;SignalSpecification;StateControl;Sum;Switch;Terminator;UnaryMinus;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;hdl.RAM

BLOCKTYPE_FREQUENCY:
1;6;5;2;2;3;2;7;1;1;4;10;9;81;7;1;1;2;16;12;7;9;1;109;26;5;1;1;1;6;1;1;1;62;2;2;9;6;2;1;4;3;9;3;10;1;1;3;1


MODELNAME: nrhdlSIB1Demodulation
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSIB1Demodulation.slx
BLOCKTYPE_FREQUENCY: 1;2;1;1;18;2;6;18;1;2;6
CHECKSUM: 537BE32106E9E7D4DEF5275B50AEE953
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: nrhdlDDCCore___Model_Block___nrhdlGridDemodulationCore___Model_Block___
ANNOTATION:
 NR HDL SIB1 Demodulation  Signals from workspace  Signals to workspace Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
Bus Creator;Constant;DDC;From;Goto;Grid Demodulation;Lmax;Plus;Reference;SIB1 Demodulation;Signal From Workspace;SubSystem;Terminator;To Workspace;centerFreq;clearStatus;coreset0Occasion;coreset0Resources;dataIn;gridData;gridValid;minChanBW;mode;nrbGrid;parsedMIB;pbchPayload;rbOffsetGrid;scsGrid;scsSSB;ssbFrequencyOffset;ssbIndex3Lsb;ssbPattern;ssbTimingOffset;start;status;stopDemod;validIn

BLOCKTYPE:
BusCreator;Constant;From;Goto;Inport;ModelReference;Outport;Signal From Workspace;Sum;Terminator;ToWorkspace


MODELNAME: nrhdlSIB1LDPCDecoding
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSIB1LDPCDecoding.slx
BLOCKTYPE_FREQUENCY: 2;1;8;1;4;1;8;1;5
CHECKSUM: 14C7F9DFCCBDD81BC1A9FDB85C24935C
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: nrhdlLDPCDecodingChainCore___Model_Block___
ANNOTATION:
 NR HDL SIB1 LDPC Decoding  Signals from workspace Copyright 2021 The MathWorks, Inc.  Signals to workspace Copyright 2021-2022 The MathWorks, Inc.

BLOCK:
Bus Selector;Diagnostics to workspace;Enable;G;Reference;SIB1 Decoding;SIB1 LDPC Decoding;Sample Control Bus Creator;Signal From Workspace;Stop Simulation;SubSystem;To Workspace;clearStatus;data;diagnostics;ldpcCtrl;ldpcData;ldpcZc;rateRecData;sib1Bits;sib1BitsCtrl;sib1Err;status;tbs

BLOCKTYPE:
BusSelector;EnablePort;Inport;ModelReference;Outport;Sample Control Bus Creator;Signal From Workspace;Stop;ToWorkspace


MODELNAME: nrhdlSIB1Recovery
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSIB1Recovery.slx
BLOCKTYPE_FREQUENCY: 2;5;6;3;1;15;20;1;1;6;6;113;6;7;9;109;1;2;41;3;25;27;1;5
CHECKSUM: C09D3BC7895F53A1D07B67724B06DC74
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 NR HDL SIB1 Recovery  Signals from workspace  Signals to workspace Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Access Arbitration;Add;Bus Assignment;Bus Creator;Bus Selector;CORESET0 Decoding;Compare To Constant;Constant;DDC;Delay;Detect Decrease;From;Goto;Grid Demodulation;In Bus Element;Input Setup;LDPC Decoding;MIB Recovery;Multiport Switch;NOT;OR;Polar Decoding;Polar Decoding Chain;Reference;SIB1 Decoders;SIB1 Decoders Disabled;SIB1 Recovery;SSB Decoding;SSB Detection;SSB Frequency Tracking;Sample Control Bus Creator;Signal From Workspace;Start Generation;SubSystem;Subtract;Terminator;To Workspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Vector Concatenate;bchStatus;clearStatus;construct coreset0DecodingIn;construct recevier params;construct sib1LDPCDecodingIn;convert bus;coreset0DecodingIn;coreset0Occasion;coreset0Resources;coreset0Status;dataIn;dataOut;dciData;dciDiag;dciInput;dciNextFrame;dciOutput;dciSearchFailed;dciStatus;dciValid;decodeChainDiagnostics;decodeChainIn;decodeChainInput;decodeChainOut;decodeChainOutput;decodeChainStatus;detectionStatus;diagnostics;firstOrSecondSlot;gridData;gridDemodEn;gridDemodParams;gridDemodStatus;gridFrequencyOffset;gridMode;gridValid;in;mibDiag;mibInput;mibOutput;mibRecovered;mibStatus;nextFrame;nextSSB;out;params;parsedMIB;pbchPayload;pbchStatus;polarAccess;receiverParams;receiverStart;restart;rxDataIn;rxValidIn;searchFailed;selDCI;sib1Bits;sib1BitsCtrl;sib1Err;sib1LDPCDecodingIn;sib1Status;ssbData;ssbDecodeValid;ssbFrequencyOffset;ssbGrid;ssbGridValid;ssbIndex3Lsb;ssbReport;ssbReportValid;ssbValid;start;startDCI;startGridDemod;startIn;startMIB;startOut;status;stopDemod;timingUpdate;timingUpdateValid;trackedSSBFreqOffset;validIn;validOut

BLOCKTYPE:
BusAssignment;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Delay;Demux;Detect Decrease;From;Goto;Inport;Logic;ModelReference;MultiPortSwitch;Outport;S-Function;Sample Control Bus Creator;Signal From Workspace;Sum;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous

EXTERNALFILE_REFERENCE:
nrhdlCORESET0DecodingCore___Model_Block___nrhdlDDCCore___Model_Block___nrhdlGridDemodulationCore___Model_Block___nrhdlLDPCDecodingChainCore___Model_Block___nrhdlPolarDecodingChainCore___Model_Block___nrhdlSSBDecodingCore___Model_Block___nrhdlSSBDetectionCore___Model_Block___


MODELNAME: nrhdlSSBDecoding
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSSBDecoding.slx
BLOCKTYPE_FREQUENCY: 4;13;1;2;6;9;1;5;1;1;26;2;5;16;6;1;1;3;16
CHECKSUM: CEAE82D91239B77C55979B80E465C9D7
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: nrhdlPolarDecodingChainCore___Model_Block___nrhdlSSBDecodingCore___Model_Block___
ANNOTATION:
Copyright 2020-2021 The MathWorks, Inc.  Signals from workspace  Stop the simulation once decoding is complete  NR HDL SSB Decoding  Parse the PBCH Payload to obtain parameter values  Signals to workspace

BLOCK:
Bit Concat;Bit Slice;Bus Selector;Cast To Boolean;Compare To Constant;Constant;Data Type Conversion;Delay;Diagnostics to workspace;Enable;From;Goto;Kssb;Lmax;Multiport Switch;ParseMIB;Polar Decoding Chain;Reference;SSB Decoding;Signal From Workspace;Signal Specification;Stop Simulation;SubSystem;Subsystem;Terminator;To Workspace;Zero;bchStatus;cellBarred;cellID;data;dataValid;demodData;diagnostics;dmrsCorr;dmrsTypeAPos;dmrsTypeAPosition;enumToValue;frequencyRange;hrf;intraFreqResel;intraFreqReselect;nextSSB;pbchBits;pbchPayload;pbchStatus;qpskSymb;rateRecData;reset;scsCommon;scsCommonEnum;sfn;sib1Config;ssbIndex;ssbIndex3Lsb;startProcessing;sym;validOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusSelector;Compare To Constant;Constant;DataTypeConversion;Delay;EnablePort;From;Goto;Inport;ModelReference;MultiPortSwitch;Outport;Signal From Workspace;SignalSpecification;Stop;Terminator;ToWorkspace


MODELNAME: nrhdlSSBDecodingCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSSBDecodingCore.slx
BLOCKTYPE_FREQUENCY: 7;4;3;2;4;2;2;6;1;3;2;12;7;103;8;3;4;24;5;2;5;3;113;29;4;1;2;2;71;8;1;7;1;2;6;8;4;1;11;10;1
CHECKSUM: 003FC98CF3F7D53BA4C949FD34A67E46
PRODUCT: Communications Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
deinterleave The controller extracts v from the bch data. v is computed from bits [4 23] (zero-based) so delay by 24 as the valid will be continuously high buffer streaming data into a frame descramble get mod(cellID,4) delay balance for RAM read delay balance for RS generation Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Add;BCH status;Bit Concat;Bit Reduce;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;Cast;Compare To Constant;Compare To Zero;Complex to Real-Imag;Constant;Correlation Control;Create Bus;D;Data Type Conversion;Delay;Demux;Detect Increase;Diagnostics Bus Creation;Enable;Extract Bits;Extract Payload;From;Gain;Goto;HDL Counter;Init;LFSR;Lmax;Load;Logical Operator;MATLAB Function;Math Function;Multiport Switch;NCellID;NOT;NR Gold Sequence Generator;OR;Out;PBCH status;Product;Q;Real-Imag to Complex;Reference;SSB Buffer + DMRS Search;Selector;SetFF;Signal Specification;Simple Dual Port RAM System;State Control;SubSystem;Switch;Tapped Delay;Terminator;Unit Delay Enabled Synchronous;Vector Concatenate;XOR;bchController;bchStatus;bchValid;cellID;cellID_mod;cinit;cinit calc;coProcessorDiagostics;convert idx;corrResult;corrValid;correlationCalc;correlationDone;ctrlIn;data;dataIn;dataValid;decodeChainDiagnostics;decodeChainInput;decodeChainOutput;decodeChainStatus;descrambleShiftIdx;diagnostics;dmrsCorrResult;dmrsCorrValid;dmrsData;dmrsSearchControl;dmrsSearchDone;dmrsValid;enable;err;frequencyRange;getDimension;goldEn;goldLoad;goldValid;gridData;gridValid;ibarSSB;ibar_SSB;ibar_SSBValid;ibar_ssb;isScrambled;load;loadGold;mask;mask1_const;mask2_const;mibDetected;mibError;nCellID_mod;newWrtEn;nextFrame;nextSSB;numScPerSym;ofdmSymbolCount;payload;pbchDemodDone;pbchPayload;pbchStatus;ramAddr;rateRecoverDone;rdValid;refSymbolGen;reset;restart;resultValid;rs;rsGen;rsNumber;rsValid;rst;s1Out;s2Out;s3Out;scPerSym;searchDone;shiftIdx;shiftMask;shiftMasks;shiftMasksConst;shiftMasksLookup;skipFirstOFDMSymbol;ssbIndex3Lsb;start;startProcessing;subcarrierCount;sym;symValid;u;validOut;y

BLOCKTYPE:
Bit Concat;Bit Reduce;Bit Shift;Bit Slice;Bitwise Operator;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Increase;EnablePort;Extract Bits;From;Gain;Goto;HDL Counter;Inport;Logic;Lookup_n-D;Math;MultiPortSwitch;NR Gold Sequence Generator;Outport;Product;RealImagToComplex;S-Function;Selector;SignalSpecification;StateControl;Sum;Switch;Tapped Delay Line;Terminator;Unit Delay Enabled Synchronous;hdl.RAM


MODELNAME: nrhdlSSBDetection
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSSBDetection.slx
BLOCKTYPE_FREQUENCY: 1;3;1;3;1;11;2;12;10;2;21;1
CHECKSUM: FB6371F6590E9C73DD82E7288CE5F087
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: nrhdlDDCCore___Model_Block___nrhdlSSBDetectionCore___Model_Block___
ANNOTATION:
Copyright 2019-2022 The MathWorks, Inc.  Signals from workspace  NR HDL SSB Detection  Signals to workspace

BLOCK:
Bus Creator;Bus Selector;Constant;DDC;Delay;Detect Decrease;Diagnostics to workspace;NCellID;Reference;SSB Detection;Signal From Workspace;SubSystem;Terminator;To Workspace;Unit Delay Enabled Synchronous;dataIn;diagnostics;frequencyOffset;gridData;gridValid;mode;pssCorrelation;pssFrequencyOffset;pssNCellID;pssThreshold;pssTimingOffset;reportValid;sssCorrelation;sssThreshold;start;status;stopDemod;subcarrierSpacing;timeOut;timingOffset;validIn

BLOCKTYPE:
BusCreator;BusSelector;Constant;Delay;Detect Decrease;Inport;ModelReference;Outport;Signal From Workspace;Terminator;ToWorkspace;Unit Delay Enabled Synchronous


MODELNAME: nrhdlSSBDetectionCore
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSSBDetectionCore.slx
CHECKSUM: 2834465C2BDD70727C8482AA14E94C79
PRODUCT: Communications Toolbox;DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
Convert offset in samples to timingOffset for each scs Convert the input PSS timing offset from the first sample of the first SSB OFDM symbol to the first sample of the reacquire search window. Forward 273 samples to the PSS correlation peak and then back 2 samples to the start of the 5 sample reacquire window. subtract 273 samples to convert timing reference from end of pss to start of ssb  Normalize the FFT output by 1/sqrt(FFTLen) to maintain energy between time and frequency domains. FFTLen is 256 therefore sqrt(FFTLen) is 16. Convert to the final output data type used for both PSS and SSS correlation and threshold signals. Convert to the final output data type used for both PSS and SSS correlation and threshold signals. Matches the delay of the Magnitude Squared 1 subsystem. Matches the delay of the Magnitude Squared 0 subsystem.  Only compute signal energy the first time, since the data is repeated 336 times.  SSS correlation accumulator: In the worst case that each subcarrier has a magnitude of 1, the maximum value of the accumulator is (cellSearchConsts.sssNormFactor * 127) = 11.3 which requires 5 integer bits (signed).  Multiply dataIn by seqIn: since seqIn is always either -1 or 1, use a gain of -1 and a switch to invert dataIn when seqIn = -1.  SSS Normalization Factor  SSS Threshold Scaling Apply gain of sqrt(sssThresholdScaling) before squaring the signal to avoid the need for a wider multiplier further along the chain.  If all subcarriers have magnitude 1 and threshold is 0dBs, then the max accumulator value is 127, therefore 7 integer bits (unsigned) are required. In practice the threshold is less than 0dBs so this is plenty of headroom. Use a comb filter followed by an integrator to implement an efficient 18-tap sliding sum. 5 bits of headroom are required for this operation.  Implement frame sum across 4 of the CP correlation results. This is done by delaying the signal by integer multiples of the OFDM symbol period, i.e. 274 samples and summing the results. Correlate the signal with itself delayed by the FFT length (256). Integrate across the CP length, which is 18 samples. Sum across 4 OFDM symbols, since this is the length of the SS block. Each symbol is 274 samples long. Cast back to 32 bits, keeping the MSBs. The input signal is oversampled by 2 relative to the PSS bandwidth and has been prefiltered to remove noise outside the PSS bandwidth. Therefore, split the signal into 2 polyphase components and use a 128 tap FIR matched filter on each phase.  The input signal is oversampled by 2 relative to the PSS bandwidth and has been prefiltered to remove noise outside the PSS bandwidth. Therefore, split the signal into 2 polyphase components and use a 128 tap FIR matched filter on each phase.  The input signal is oversampled by 2 relative to the PSS bandwidth and has been prefiltered to remove noise outside the PSS bandwidth. Therefore, split the signal into 2 polyphase components and use a 128 tap FIR matched filter on each phase.  Multiply by 2 by shifting left 1 place. Convert to final output type. convert to unsigned Sum across a window of 128 samples using a comb filter followed by an integrator. Sum across a window of 128 samples using a comb filter followed by an integrator. Multiply by 2 with a reinterpret cast. Convert to final output type.  Measure the energy in the signal across a 128 sample window, which is equivalent to the PSS correlation window. This will be used later to generate a threshold.  Use a simple circular buffer to synchronize the streams, given that the correlators have greater latency than the signal power measurement.  Scale the signal by the square root of the threshold scaling factor before measuring the energy. This leads to a more efficient implementation than applying the scaling factor afterwards.  Apply a lower limit to the threshold to prevent small signals from triggering detection. ufix32_En24 is the data type used for both PSS and SSS correlation and threshold signals. Wait two valid samples to start. This aligns the start of the PSS reacquire window with the correct symbol in the OFDM demod data. subtract 2 samples to convert timing reference from PSS peak to start of detection window  Match the latency of the HDL FIR used to implement polyphase filter 0. Multiply by 0.5 by simply reinterpreting the sfix16_En15 as an sfix16_En16. Input data type must be sfix16_En15 Multiply by 0.5 by simply reinterpreting the sfix16_En15 as an sfix16_En16. Match the latency of the HDL FIR used to implement polyphase filter 0. Input data type must be sfix16_En15 Multiply by 0.5 by simply reinterpreting the sfix16_En15 as an sfix16_En16. Match the latency of the HDL FIR used to implement polyphase filter 0. Input data type must be sfix16_En15 Multiply by 0.5 by simply reinterpreting the sfix16_En15 as an sfix16_En16. Match the latency of the HDL FIR used to implement polyphase filter 0. Input data type must be sfix16_En15 Copyright 2019-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Accumulator;Add;Bit Concat;Bit Slice;Bitwise OR;Bus Assignment;Bus Creator;Bus Selector;CP Correlation to Frequency;Cast;Cast To Boolean;Centre Tap;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Constant;Convert Timing Offset;Correlate;Correlators;Correlators and threshold;Cyclic Prefix Correlation;Data Type Conversion;DataOut;Delay;Demux;Detect Increase;Detection Status;Diagnostics Bus Creation;Discrete FIR Filter HDL Optimized;Empty;Enabled Delay;Equal;FFT HDL Optimized;FIFO;FIR;FIR ;FIR Decimator;FR;FR1+FR;For Each;From;Gain;Goto;GreaterThan;HDL Counter;IFFT HDL Optimized;In;In Bus Element;Input Distributor;Logical Operator;MATLAB Function;Magnitude Squared;Magnitude Squared ;Magnitude Squared Thresh;MovingAverage;Multiphase Moving Average;Multiply;Multiply and IFFT;Multiport Switch;NCellID;NCellID2In;NCellIDIn;NOT;OFDM Data Synchronization;OFDM Demod Controller;OFDM Demod Sync;OFDM Demodulate;OFDM Demodulator;OR;Out;Output Combiner;Overlap-add;PSS Buffer;PSS Correlator ;PSS Detection;PSS Diagnostics;PSS Info Serialization;PSS Peak Detectors;PSS Prefilter;PSS and CP Alignment;PSS search status;Peak Search;Pick Timing Track Peak;Polyphase Decimator;Pop;Product;Push;Reacquire Track;Real-Imag to Complex;Recombine phases;Reference;Relational Operator;Report Creation;SCS;SCS 120 Halfband Decimator;SCS 120 Rate Synchronizer;SCS 15 Halfband Decimator;SCS 240 Rate Synchronizer;SCS 30 Halfband Decimators;SCS 30 Rate Synchronizer;SSB Demod;SSB Search;SSBDetectionCore;SSS Correlation Controller;SSS Detection;SSS Sequence LUT;SSS_Dot_Product;Search Controller;Select SCS;Selector;Shift Arithmetic;Signal Specification;Simple Dual Port RAM System;Sliding Sum;Split phases;Stage ;Start Controller;State Control;Stream Synchronizer;SubSystem;Subcarrier Spacing Selection;Subtract;Switch;Symbol Sum;Synchronous Enabled 128 Sample Delay ;Synchronous Enabled Unit Delay;Terminator;Threshold Limiter;Threshold Prescaling;ThresholdLimiter;Timing Ref Generator;Timing Reference Modulo;Transient Removal;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Vector Concatenate;Zero;accEnd;accStart;addrIn;bit reverse;clearStatus;coeff ROM;coeffs;complexConj;corrOut;correlation;cpCorr;cpCorrValid;cpCorrelation;cpCorrelationValid;cpFreqOffset;cpFreqOffsetIn;cpFreqOffsetValid;cpToPssOffset;dataIn;dataOut;demodSync;detectorValid;diagnostics;diagnosticsIn;diagnosticsOut;done;empty;en;globalCnt;globalCntIn;globalCntOut;gridData;gridValid;idleTimingSlip;maxCorrelation;mode;nonEmpty;ofdmDemodSync;ofdmDemodSyncStart;ofdmDemodSyncValid;ofdmDemodSyncValidIn;ofdmDemodSyncValidOut;overlap add;params;paramsIn;paramsOut;phase;phase ;pkDetCorrelation;pkDetCorrelationIn;pkDetCorrelationOut;pkDetThresholdExceeded;pkDetThresholdIn;pkDetThresholdOut;pkDetValid;pkDetValidIn;pkDetValidOut;pkLocation;pkReacquireFail;pop;pssCorrIn;pssCorrOut;pssCorrelation;pssCorrellationIn;pssDone;pssFound;pssFreqOffsetIn;pssFreqOffsetOut;pssFrequencyOffsetIn;pssReac;pssReacFail;pssSeq;pssSuccess;pssThreshold;pssThresholdIn;pssThresholdOut;pssTimingOffsetIn;pssTimingOffsetOut;pssTimingRef;pssTimingRefIn;pssTimingRefOut;pssValid;pssValidIn;pssValidOut;push;rdAddr;rdEn;reacTimingRef;reacTimingSlip;reacquire;reacquireFail;real;report;reportIn;reportValid;reset;restart;rst;scs120Data;scs120Valid;scs15Data;scs15Valid;scs240Data;scs240Valid;scs30Data;scs30Valid;scsIn;scsOut;scsValid;searchCount;searchEn;selData;selValid;seqEnd;seqIn;seqNum;seqNumIn;seqNumOut;seqStart;ssGridValid;sssAddr;sssCorrelation;sssCorrelationValid;sssDone;sssMaxCorrelation;sssMaxCorrelationIn;sssSuccess;sssThresholdIn;start;startIn;startOfSSB;startOut;startPkDet;startProcessing;startPss;startRead;startTime;startTimeOut;startWrite;status;stopDemod;stopReac;subcarrierSpacing;success;sync;syncOut;syncTime;targetPSS;targetTimingRef;threshold;thresholdExceeded;thresholdIn;thresholdOut;timeOut;timingOffset;timingOffsetOut;timingRef;timingRefIn;timingRefOut;timingReferenceIn;totalTimingSlip;trackPSSSeq;trackTRef;trackValid;trackedTimingRef;trackedTimingRefValid;validIn;validOut;winningSeqNum;wrAddr;wrEn;x;y

BLOCKTYPE:
ArithShift;Bit Concat;Bit Slice;Bitwise Operator;BusAssignment;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Increase;Discrete FIR Filter;FFT;FIR Decimator;ForEach;From;Gain;Goto;HDL Counter;IFFT;Inport;Logic;Lookup_n-D;Math;MultiPortSwitch;OFDM Demodulator;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Selector;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;hdl.RAM

BLOCKTYPE_FREQUENCY:
1;4;28;5;2;3;7;15;1;1;11;4;20;44;264;49;2;11;1;2;3;7;22;7;18;1;410;40;2;1;35;1;338;10;9;12;37;1;3;13;30;8;51;7;16;14


MODELNAME: nrhdlSignalDetection
PATH: toolbox/whdl/whdlexamples/whdlexamples/nrhdlSignalDetection.slx
BLOCKTYPE_FREQUENCY: 4;4;9;102;5;6;1;3;3;1;1;84;6;3;3;1;1;63;9;7;5;3;3;9;6;3;11;14;2;2
CHECKSUM: E22D3F9BEC2AC3A9F2742591AF2D3DD0
PRODUCT: DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 Delay data by Nfft + cyclic prefix of 18 to align detection peak with start of OFDM symbol containing selected PSS Enable OFDM Demod for 4 OFDM symbols Delay balance for pipelined MAX  DistributedPipelining =on to pipeline MAX tree  DistributedPipelining =on to pipeline MAX tree Delay balance for pipelined MAX Delay balance for pipelined MAX  DistributedPipelining =on to pipeline MAX tree Match delays in peak filtering subsystems  Apply thresholding to correlation peaks and select strongest peak within sl_in.windowLength sample window Convert to unsigned  Increase integer bits to allow for growth in averaging filter Sum across a window of Nfft samples using a comb filter followed by an integrator. Each PSS Correlator performs resource sharing. There are sl_in.cyclesPerSample clock cycles per input sample, allowing for serialization of the operations Synchronize signals between correlator and threshold paths 0 = 15kHz SCS 1 = 30kHz SCS Decimate to 15KHz SCS rate  convert to sfix16_15 to match filter input data type Synchronize signals across PSS Detector scsSSB is a boolean value 0 = 15kHz SCS 1 = 30kHz SCS

BLOCK:
 Demux ; SFunction ; Terminator ;A;AND;Add;B;C;Complex to Real-Imag;Constant;Data Type Conversion;Delay;Delay Enabled Synchronous;Demux;Detect Rise Positive;E;Enable;Equal;FIR Decimator;Find Peak;HDL Counter;MATLAB Function;Max;Multiport Switch;Mux;OFDM Demod Controller;OFDM Demodulator;OR;PSS Correlator ;PSS Detector;Product;Reference;SSB Detect and Demod;Selector;Signal From Workspace;Simple Dual Port RAM System;State Control;Stream Synchronizer;SubSystem;Synchronous Delay;Synchronous Enabled Nfft Sample Delay ;Synchronous Enabled Unit Delay;Tapped Delay;Terminator;To Workspace;Transient Removal;Unit Delay Enabled Synchronous;corrMag;dataIn;dataOut;detectionPeaks;detectionStrobe;done;en;enabledTapDelay;filter peaks ;max;peaks;pipelinedMax;pop;pssDetected;pssID;pssIndex;push;rdAddr;register PSS ID;scsSSB;scsSelection;selectedPSS;signalMag;signalMagAverage;start;startIn;strobeOut;strobeValid;threhold;thresholdIn;u;valid;validIn;validOut;wrAddr;wrEn;y

BLOCKTYPE:
ComplexToRealImag;Constant;DataTypeConversion;Delay;Delay Enabled;Demux;Detect Rise Positive;Discrete FIR Filter;EnablePort;FIR Decimator;HDL Counter;Inport;Logic;MinMax;MultiPortSwitch;Mux;OFDM Demodulator;Outport;Product;RelationalOperator;S-Function;Selector;Signal From Workspace;StateControl;Sum;Tapped Delay Line;Terminator;ToWorkspace;Unit Delay Enabled Synchronous;hdl.RAM


MODELNAME: whdlAWGNGenerator
PATH: toolbox/whdl/whdlexamples/whdlexamples/whdlAWGNGenerator.slx
BLOCKTYPE_FREQUENCY: 1;14;1;19;2;21;10;16;120;2;3;26;8;33;8;2;1;2;12;7;2;2
CHECKSUM: 5CA2F7A3C24ADC5A31F99F5B54420F48
PRODUCT: DSP System Toolbox;Fixed-Point Designer;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2)  Add Block is used to obtain integer index to Lookup Table  HDL AWGN Generator Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AWGNGenerator;Abs;Add;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;ConcatandExtract;Constant;Data Type Conversion;Delay;FunctionEvaluation;Gain;GaussianNoiseWithReqVar;GaussianNoiseWithUnitVar;Product;RangeReconstruction;RangeReduction;Reference;Shift Arithmetic;Signal From Workspace ;SinCos;Sine HDL Optimized;SqrtEval;SqrtImplementation;SubSystem;Subtract;Switch;TausURNG;TausUniformRandGen;To Workspace;a;awgn;b;dBtoLinearConverter;e;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;g;g1(16,15);leadingZeroDetector;log;logImplementation;noiseVar;pass;passIn;passOut;snrdB;sqrt(noisePow/2);u;u0(16,16);u0(48,48);u1(16,16);valid;validOut;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
Abs;ArithShift;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Constant;DataTypeConversion;Delay;Demux;Gain;Inport;Lookup_n-D;Outport;Product;S-Function;Signal From Workspace;Sine and Cosine HDL optimized block;Sum;Switch;Terminator;ToWorkspace


MODELNAME: whdlOFDMReceiver
PATH: toolbox/whdl/whdlexamples/whdlexamples/whdlOFDMReceiver.slx
BLOCKTYPE_FREQUENCY: 1;1;4;5;2;3;8;4;2;6;11;3;1;1;15;2;4;2
CHECKSUM: 8979B1E234BF477590EB2B4A7B9F7FBA
PRODUCT: Communications Toolbox;DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: whdlOFDMRx___Model_Block___
ANNOTATION:
 CFO must be in Hz OFDM Receiver  Copyright 2020-2023 The MathWorks, Inc.  To run the model, run the runOFDMReceiverModel script.

BLOCK:
<headerError>;<headerLatch>;Bias;Bus Creator;Bus Selector;CPE Correction;Capture Data Bits;Channel Equalization;Constant;Control Scope;Data Constellation Diagram;Data Type Conversion;Diagnostic Decoder;Display;Enable;External Frequency Offset;Frequency Correction Type;Gain;HDL Counter;Header Constellation Diagram;In;Logical Operator;MT;OFDM Receiver;Reference;Rx Data In;Rx Valid In;Store detected frame numbers to workspace;SubSystem;Subsystem;To Workspace;Unit Delay Enabled Synchronous;Visualize Data Constellation;Visualize Header Constellation;dataConstellationPoints;dataIn;dataOut;dataPoints;dataValid;decodedModType;decodedRate;diagBus;extRst;freqOffsetEstimate;headerConstellationPoints;headerPoints;headerValid;impairmentControl;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;validIn;validOut;whdlOFDMRx Model

BLOCKTYPE:
Bias;BusCreator;BusSelector;Constant;ConstellationDiagram;DataTypeConversion;Display;EnablePort;Gain;HDL Counter;Inport;Logic;Lookup_n-D;ModelReference;Outport;Signal From Workspace;ToWorkspace;Unit Delay Enabled Synchronous


MODELNAME: whdlOFDMRx
PATH: toolbox/whdl/whdlexamples/whdlexamples/whdlOFDMRx.slx
CHECKSUM: 7ABD87BCB40EF7459BE569F8B2E1BBFF
PRODUCT_BASECODE: LH
ANNOTATION:
 Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z))  conjugate pilot The pop signal asserts when 2 triggers occur  This block stores samples of length equal to 1 OFDM symbol.  When self pop trigger occurs, the symbol buffer pops out all the samples until it becomes empty.  Estimate CPE for each OFDM symbol using 12 pilot sub carriers and average the estimated data.  Pilot valid to false  OFDM Channel Estimator supports reference signal sub carriers only when magnitude is 1.  Reference signal sub carriers are stored in LUT.  Estimates the channel frequency response for each frame.  Stores the estimate from Channel Estimation subsystem for each frame and perform channel equalization.  Separate reference signal subcarriers from the frame  Separate header and data subcarriers in the frame Compute read address Give null output if valid is LOW  Puncture vectors are stored as integers in the LUT and converted into vectors. Deinterleave and generate inputs for depuncturer poly: 1 0 0 1 0 0 0  dataASc refers to Active subcarriers which are not pilot carriers  The input is a source coded header information  Port 1 return number of bit per modulated symbol.  Port 2 return a value = dataASc * modIndex * code rate * 32 - 7  (dataASc*log2(MaxModOrder)*MaxCodeRate*32) bits stream into this subsystem per frame. (dataASc*log2(MaxModOrder)*MaxCodeRate*32)-6 bits stream out as valid and the 6 bits gets discarded due to terminated mode. The end and valid signals will be generated appropriately.  Compute parameters required for successive subsystems.  Perform 1/2 or 2/3 or 3/4 or 5/6 rate viterbi decoding.   Perform 32-bit CRC Detection.  Perform BPSK or QPSK or 16-QAM or 64-QAM soft bit demodulation.  This function discards data sub carriers, if header CRC fails. Compute read address Give null output if valid is LOW  36 bits stream into this subsystem per frame. 30 bits are streamed out as valid. 6 bits gets discarded due to terminated mode. The end and valid signals are generated appropriately.  1/2 rate viterbi decoding  BPSK soft bit demodulation  Performs 16 - bit CRC Detection  Discard samples outside the boundaries Scaling factor does not affect the next stage as the angle does not depend on it and the relative magnitude of all the samples still remains the same. To optimize for HDL scale the summation result by 1/8 rather than 1/6.   This subsystem averages 6 of the CP correlation results. This is done by delaying the signal by integer multiples of the OFDM symbol period.  Use a comb filter followed by an integrator to implement an efficient CPCorrLen-tap moving average.   Average across 6 OFDM symbol duration.  Average across part of the CP length  Correlate the signal with itself delayed by the FFT length   This operation will convert 2*(f/ss) to f/ss  The angle returned by this block is normalized form of 2*pi*(f/ss) by pi i.e. 2*(f/ss) where f is fine frequency, ss is sub carrier spacing. Reinterpret as 14-bit signed integer  Sum across a window of 128 samples using a comb filter followed by an integrator.  This subsystem has commands in InitFcn callback to supress warnings B A  Use a simple circular buffer to synchronize the streams, given that the correlators have greater latency than the signal power measurement.  Measure the energy in the signal across a 128 sample window, which is equivalent to the SyncSignal correlation window. This will be used later to generate a threshold. peak picker  Perform SS correlation and generate dynamic threshold  SS detection  Performs CFO estimation for 4 frames  Disables max peak search until CFO is ready  CFO estimate becomes stable after 4 frames (12 ms duration) Reinterpret as 14 bit signed int  Perform CFO correction  The FIFO depth must be equal to the searchDuration samples in Max Peak Searcher subsystem  Count the input valid and synchronize the data with the timingOffset.  Generate start and end signals for the frame boundaries and discard samples outside the boundaries  Estimate and compensate CFO and perform SS detection and time synchronization  Create bus signal for status signals to monitor them outside FPGA  Recover header information and data bits using header information  Perform frequency and time synchronization and OFDM demodulation to get subcarriers  Copyright 2020-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;Accum Register;Active;Add;AngleAtMaximum;AngleFilter;Assertion;Average Estimate;Average6Symbols;Bias;Bit Clear;Bit Set;Bit Shift;Bit Slice;Buffer FIFO;Bus Creator;Bus Selector;C;C+D;C-D;CFO Estimation;CFO Estimation and Correction and SS Detection;CFO Estimation and SS Detection;CIC Decimator;CPAverage;CPCorr;CPE Correction;CPE Estimation and Correction;CPE Estimator;CPE Estimator and Symbol Buffer ;CPECorrectedData;CPECorrectedValid;CPECtrl;CPEestimate;ChanEquiCtrl;Channel Coding;Channel Equalization;Channel Estimates Store RAM;Channel Estimation;Channel Estimation and Equalization;Channel and CPE Estimation and Correction;Compare To Constant;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Constant;Constellation Bus;Correlator;CyclicPrefixCorrelator;DT Conversion;Data CRC;Data Recovery;Data Type Conversion;Data Type Duplicate;Decimation Filter Chain;Deinterleaver;Delay;Delay by ;Delay by Latency;Depuncturer;Descrambler;Diagnostic Bus Formation;Display;Divide;Enable;EstvalidIn;ExtFreq;Extract Bits;Extract System Parameters;FIFO;FIFO Rate Converter;FIR Decimator;Frame Controller;Frame boundaries Generator;Frequency Correction 1x;Frequency Correction Nx;Frequency and Time Synchronization;From;Function Impl;Gain;Generate Base Read Address;Generate Control Signals;Generate Current Frame Status;Generate Forced End;Generate Output Control Signals;Generate Read Address;Generate Ready;Generate Write Address;Goto;HDL Count and Stop;HDL Counter;Handle Input Control Signals;Header CRC;Header Recovery;Header and Data Parsing;Header and Data Recovery;In;Initial Seed;LTE Symbol Demodulator;LUT;LUTAddr;Logical Operator;MATLAB Function;MagnitudeSquared;Math Function;Max Peak Searcher;ModTypeReg;Modtype;MovingSum;Multiply-Add;Multiport Switch;NCO HDL Optimized;NO HDL;No HDL;OFDM Channel Estimator;OFDM Demodulator;OFDM Equalizer;OFDMDataOut;OFDMSymbolStart;OFDMValidOut;Out;Parameters;Pilot Dist Counter;Pilot Generator;Pilot Index Generator;Pilot Valid Generator;Pop Controller;Pop Counter;Product;Puncture Vector LUT;Push Counter;Read Logic;Real-Imag to Complex;Reciprocal;Rect2Polar;Reference;Reference Signal Parsing;Relational Operator;Rx Filter;Sample Control Bus Creator;Sample Control Bus Selector;Sample Discard Controller;Selfpop Trigger;Signal Specification;Simple Dual Port RAM System;Start Controller;State Control;State Register;StreamSyncronizer;SubSystem;Subsystem;Sum;Supress One Trigger;Switch;Symbol Boundaries Generator;Sync Signal Search;SyncPulse;SyncSignalXCorr;Synchronization and OFDM Demodulation;Synchronous Enabled 128 Sample Delay ;Synchronous Enabled Unit Delay;Terminator;ThresholdLimiter;ThresholdPrescaling;Timing Adjust;To Workspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Unit Delay Resettable Synchronous;Validate Input Push Pop;Vector Concatenate;Viterbi Decoder;Write Logic;advPop;angleIn;angleOut;angleValid;angleValidIn;angleValidOut;baseAddr;blockCount;blockDataCount;blockLen;blockValid;chanEst;chanEstIn;channelEqualizerControl;codeRate;codeRate Reg;coderateReg;colCounter;complexConj;complexConjugate;conjPilot;constellationBus;corr;corrOut;correlation;correlationIn;count;countEnb;countIn;currentAddr;cvalidIn;cvalidOut;data;data contellation points;data contellation valid;dataAScXCodeRateX;dataBits;dataBitsValid;dataCRCFail;dataCRCPass;dataCRCerror;dataCRCvalid;dataConstellationPoints;dataConstellationValid;dataIIn;dataIn;dataModTypeindex;dataOut;diagBus;dir;done;empty;en;enable;enb;end;endIn;endOut;endReady;error;errorIn;errorOut;estimate;estimateOut;estimateReady;extRst;extRstOut;externalFrequencyOffset;fifoCount;fifoData;forcedEnd;frameNumberBeforeSync;frameOn;freCorrect;freEstinternal;freq;freqCtrl;freqEst;freqEstRegEn;freqEstToNxCorrection;freqEstValid;frequencyCorrectedData;frequencyCorrectedValid;frequencyOffsetCorrectionType;full;functionValues;header latch;headerCaptured;headerConstellationData;headerConstellationPoints;headerConstellationValid;headerConstellationvalid;headerData;headerDataIn;headerError;headerLatch;headerValid;headerValidIn;headererror;hvalidOut;impairCtrl;in;ivalidOut;latchOut;magIn;magOut;modType;modType Reg;modtype;ncount;numEntries;out;packet discard controller;peakSearch;pilot LUT;pilotOut;pilotValid;pop;popEmpty;popEmptyDiag;popEmptyFIFO;push;pushFull;pushFullDiag;pushFullFIFO;rd;rdAddr;readStart;ready;readyCounter;reference symbols;reset;resetIn;resetOut;rowCounter;rst;rstOut;rxInputData;rxInputValid;sampleValidIn;sampleValidOut;searchHold;searchIHold;selfpopTrigger;start;startIn;startOut;success;switch;sync pulse;syncPulse;threshold;thresholdExceeded;thresholdIn;timing;timing Reference;timing Reference Long;timingOffset;timingOffsetLong;timingOffsetValid;timingValid;trigger;valid;valid Controller;valid pop;valid push;validCount;validIn;validOut;validin;whdlOFDMRx;wr;wrAddr;wrValid;x;y

BLOCKTYPE:
Assertion;Bias;Bit Clear;Bit Set;Bit Shift;Bit Slice;BusCreator;BusSelector;CIC Decimator;Compare To Constant;Complex to Magnitude-Angle;ComplexFIRFilter;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Depuncturer;Discrete FIR Filter;Display;EnablePort;Extract Bits;FIR Decimator;From;Gain;General CRC Syndrome Detector HDL Optimized;Goto;HDL Counter;Inport;LTE Symbol Demodulator;Logic;LookupNDDirect;Lookup_n-D;Math;MultiPortSwitch;NCO;OFDM Channel Estimator;OFDM Demodulator;OFDM Equalizer;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Sample Control Bus Creator;SignalSpecification;StateControl;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Unit Delay Resettable Synchronous;Viterbi Decoder;hdl.RAM

BLOCKTYPE_FREQUENCY:
8;2;1;1;1;10;4;3;1;40;2;1;3;1;48;41;3;454;22;1;4;3;12;4;2;8;6;2;8;45;426;2;145;2;6;5;3;2;1;1;1;301;15;1;21;22;2;5;2;32;15;39;13;18;16;2;2;8

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;Wireless HDL Toolbox


MODELNAME: whdlOFDMTransmitter
PATH: toolbox/whdl/whdlexamples/whdlexamples/whdlOFDMTransmitter.slx
BLOCKTYPE_FREQUENCY: 5;1;1;2;1;8;1;1;10;1;3;1;1;1;1
CHECKSUM: 48B107A91CFBF085A0C7B99D77134131
PRODUCT: DSP System Toolbox;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
EXTERNALFILE_REFERENCE: whdlOFDMTx___Model_Block___
ANNOTATION:
 This subsystem is active only when the input ready signal is active. The subsystem selects the Input Valid value and outputs the valid signal. The subsystem also selects the payload data from an LUT based on the Input Valid signal and outputs it as data signal.  This subsystem is active only when there is a rising edge on the input ready signal. The subsystem selects the Input modOrder and Input codeRateInd values for the current frame and outputs corresponding modTypeIndex and codeRateIndex values.  Copyright 2020-2023 The MathWorks, Inc.  OFDM Transmitter  To run the model, run the runOFDMTransmitterModel script.

BLOCK:
 Demux ; SFunction ; Terminator ;Capture Tx Waveform;Control Scope;Data Type Conversion;Data and Valid Selector;Delay;Enable;HDL Counter;Index Mapper;Index Selector;Input Valid;Input codeRateInd;Input modOrder;OFDM Transmitter;Payload Data;Payload Data Selector;Reference;Spectrum Analyzer;SubSystem;To Workspace;Trigger;codeRateInd;codeRateIndex;data;modOrder;modTypeIndex;ready;txData;txValid;valid;whdlOFDMTx Model

BLOCKTYPE:
DataTypeConversion;Delay;Demux;EnablePort;HDL Counter;Inport;Lookup_n-D;ModelReference;Outport;S-Function;Signal From Workspace;SpectrumAnalyzer;Terminator;ToWorkspace;TriggerPort


MODELNAME: whdlOFDMTx
PATH: toolbox/whdl/whdlexamples/whdlexamples/whdlOFDMTx.slx
CHECKSUM: C2AEA1D4AC3E5695145B3A9C946B3049
PRODUCT: Communications Toolbox;DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Simulink;Wireless HDL Toolbox
PRODUCT_BASECODE: LH
ANNOTATION:
 Select the transport block size of the current frame based on the modTypeIndex and codeRateIndex values.  The Dual Rate RAM block stores one frame of signals.  ofdmModIn, ofdmModInValid, ofdmData, and ofdmValid signals output few extra samples than expected. Discard the extra samples at the end and use the remaining samples for validation. polynomial: 1 0 0 1 0 0 0 Compute read address Give null output if valid is LOW  Ideally, the counter must reset when the count reaches (trBlkSize -1). But, as there are two delays in feedback loop, the counter resets when the count reaches (trBlkSize - 3).  This subsystem outputs payload data bits and the corresponding control signals that are processed through Data Chain.  This subsystem processes the payload data. Compute read address Give null output if valid is LOW  Header bits are formed based on input modTypeIndex, codeRateIndex, and fftLenIndex values. Header bits are then processed through header chain as shown below. Upsampling is done to compensate the rate change due to Convolutional Encoder in Header and Data subsystems. Access pilot signals from LUT. Access reference signal from LUT. Upsampling is done to compensate the rate change due to Convolutional Encoder in Header and Data subsystems. Access synchronization sequence from LUT.  Indicates that transmitter is ready to accept data.  Copyright 2020-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Add;Assertion;Bit Clear;Bit Set;Bit Shift;CIC Interpolator;Compare To Constant;Constant;Control OFDM Signal Generation;Convolutional Encoder;Counter for Read Address;Create Control Bus;Data;Data Chain;Data Type Conversion;Data Type Duplicate;Data and Control Signal Generation;Delay;Demux;Disable OFDM Generation;Discrete FIR Filter;Display;Enable;Enable Header and Preamble ;Extract Bits;FIFO;FIFO Rate Converter;FIR Interpolator;Falling Edge Detector;Frame Controller;Frame Controller and Input Sampler;Frame Formation and OFDM Modulation;Frame Generator;From;General CRC Generator HDL Optimized;Generate Base Read Address;Generate Current Frame Status;Generate Forced End;Generate OFDM Modulator Ready;Generate OFDM Modulator Valid;Generate Output Control Signals;Generate Preamble Control Signals;Generate RAM Inputs;Generate Read Address;Generate Ready;Generate Transmitter Ready;Generate Write Address;Goto;HDL Counter;Handle Input Control Signals;Header;Header Data Indices LUT;Header Formation;In;Input Sampler;Interleaver;Interpolation Filter Chain;LTE Symbol Modulator;Logical Operator;MATLAB Function;MonoStable;Multiplex Header and Data Signals;Multiplex Preamble Signals;Multiplexer;Multiport Switch;No HDL;OFDM Modulator;Pilot;Pilot Counter;Pilot LUT;Pop Counter;Preamble Indices LUT;Priority Encoder;Product;Pulse Generator;Puncturer;Push Counter;RAMAddress;RAMData;RAMValid;RS Counter;RS LUT;Random OFDM Symbol;Read Logic;Real-Imag to Complex;Reference;Reference Signals;Relational Operator;Rising Edge Detector;SS Counter;SS LUT;Sample Control Bus Creator;Sample Control Bus Selector;Scrambler;Select Puncture Vector;Serializer;Simple Dual Port RAM;Simple Dual Port RAM System;Split Data Into Symbols;Store Block Lengths;Store Input Payload Data;Store Number of Rows;SubSystem;Subsystem;Switch;Symbol Interleaver;Symbol LUT;Synchronization Sequence;Terminator;To Workspace;Transport Block Size LUT;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;ValidOut;Validate Input Push Pop;Write Logic;advPop;baseAddr;blockCount;blockDataCount;blockLen;blockLenOut;blockValid;cnt;codeInd;codeIndex;codeRate;codeRateIndex;colCounter;count;countEnb;ctrlIn;ctrlOut;currentAddr;data;dataIn;dataOut;dataSet;dataValid;dir;empty;enable;enableIn;enb;end;endIn;endOut;endReady;fftLen;fftLenIndex;fifoCount;forcedEnd;frameOn;full;generatedReady;header;headerBits;headerSet;headerValid;holdOFDMGen;in;loadMod;loadModulator;loadSymMod;modIdx;modInd;modIndex;modType;modTypeInd;modTypeIndex;ncount;numEntries;numRows;numRowsOut;ofdmData;ofdmModIn;ofdmModInValid;ofdmModReady;ofdmModValid;ofdmValid;out;parallelIn;pilot;pilot set;pilotValid;pop;popEmpty;popEmptyDiag;popEmptyFIFO;preambleData;preambleOut;preambleSet;preambleValid;pulse;puncVec;puncVector;push;pushFull;pushFullDiag;pushFullFIFO;rd;rdAddr;readStart;ready;readyCounter;readyLow;reset;resetRAM;rowCounter;rs;rs set;rsValid;rst;sampleInParam;selLine;serialOut;set;ss;ss set;ssValid;start;startIn;startOut;trBlkSizeM;trigger;txData;txValid;valid;valid pop;valid push;validIn;validOut;waitSignal;whdlOFDMTx;wr;wrAddr;wrEnable;wrValid

BLOCKTYPE:
Assertion;Bit Clear;Bit Set;Bit Shift;BusSelector;CIC Interpolator;Compare To Constant;Constant;Convolutional Encoder;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;EnablePort;Extract Bits;FIR Interpolator;From;General CRC Generator HDL Optimized;Goto;HDL Counter;Inport;LTE Symbol Modulator;Logic;Lookup_n-D;MultiPortSwitch;OFDM Modulator;Outport;Product;Puncturer;RealImagToComplex;RelationalOperator;S-Function;Sample Control Bus Creator;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;hdl.RAM

BLOCKTYPE_FREQUENCY:
17;1;1;1;2;1;43;61;2;10;2;246;34;1;6;1;7;2;13;2;12;52;363;2;170;7;2;1;273;2;1;2;21;32;2;4;16;24;48;5;2;20;11


MODELNAME: wtGettingStartedUSRPTargetingGainSL
PATH: toolbox/wt/examples/wtGettingStartedUSRPTargetingGainSL.slx
BLOCKTYPE_FREQUENCY: 2;4;4;12;7;1;1;2;2;10;15;2;1;2;2
CHECKSUM: FE4217305A2A7ABBF2420B8AC8A6D1CD
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: WB
ANNOTATION:
 Getting Started with NI USRP Targeting Workflow Hardware Generation Model WRITE GAIN REGISTER  Copyright 2024 The MathWorks, Inc.

BLOCK:
Bit Concat;Bit Slice;Data Type Conversion;DataOut;Data_In;Data_Out;Delay;Enable;Enabled Subsystem;From;Gain;Gain Multiplier;GainCtrl;Goto;In_ImData;In_ReData;Inputs;Last;Last_In;Last_Out;Out_ImData;Out_ReData;Outputs;Product;Read_Gain;ReadyIn;Ready_In;Ready_Out;Reference;SubSystem;Terminator;Valid;Valid_In;Valid_Out;Waveform Generator;Write_Gain

BLOCKTYPE:
Bit Concat;Bit Slice;Constant;DataTypeConversion;Delay;Display;EnablePort;From;Goto;Inport;Outport;Product;Scope;Terminator;WaveformGenerator


MODELNAME: wtMultiPortPacketBasedUSRPTargetingExampleSL
PATH: toolbox/wt/examples/wtMultiPortPacketBasedUSRPTargetingExampleSL.slx
BLOCKTYPE_FREQUENCY: 1;2;4;1;1;1;14;1;5;46;1;1;1;1;1;1;1;9;2;36;26;1;35;2;1;11;2;2;2;2;1;8;1
CHECKSUM: 8ED1EF15DDB5428643599C21E0A01A46
PRODUCT: DSP HDL Toolbox;DSP System Toolbox;MATLAB;Simulink
PRODUCT_BASECODE: WB
ANNOTATION:
When buffer full, de-asserts ready hDevice(BurstLength) Ensure output of previous FFT frame before reset Provide minimum tLast granularity Indicate start of FFT using highest bit Send Last after every SPP valid samples  Radio Source / Sink  MATLAB Host Interface  DUT  PL DDR Buffer / Registers  MultiPort Packet Based USRP Targeting Example Hardware Generation Model  Copyright 2024 The MathWorks, Inc.

BLOCK:
AND;Add;Array Plot;BinNumber2Frequency;Bit Concat;Bit Slice;BitCat;BitSlice;BufferOverflow;BufferReady;Burst Cnt;CORDIC_balance;Calculate NCO Increment;Calculated Max Bin Frequency;Cast;Compare To Zero;Complex to Magnitude-Angle;Complex to Real-Imag;Compute RX Spectrum Magnitudes;Constant;Count;D Latch;DUTData;DUTValid;DUT_Data_Out;DUT_EOB_Out;DUT_Last_Out;DUT_Ready_In;DUT_Valid_Out;Data;Data Type Conversion;Data_In;Data_Out;Delay;Detect Falling Edge;Detect Increase;Divide;EOB;EOB_In;EOB_Out;EndOfBurst;Equal;FFT;FFT Magnitude;FFT Start;FFTShift;From;GT;Gain;Generate TX Tone;Goto;HDL Counter;HDL FIFO;Hold Largest Magnitude Bin Index;In;Increment;Index;LT;Last;Last_In;Last_Out;Less Than;LessThanOrEqual;LookupMax;Magnitude;MaxBin;NCO;NOT;OR;Offset;Out;Overflow;PL DDR Buffer;Process Frame;ProcessFrames;Quadrature Phase;RFData_Loopback;RF_Data_In;RF_EOB_In;RF_Last_In;RF_Ready_Out;RF_Valid_In;Radio RF Sink;Radio RF Source;Ready;Ready_In;Ready_Out;Real-Imag to Complex;Reference;Reset;Rx Enable;SH_Idx;SH_Val;Sample Cnt;Sample Rate;SampleRateOut;Sampler;Selector;SubSystem;Subtract;Switch;TX_Data_Out;TX_EOB_Out;TX_Increment_In;TX_Last_Out;TX_Ready_In;TX_Valid_Out;Tapped Delay Enabled Synchronous;Terminator;Tone Freq;TransmitTone;Tx Enable;TxRx;Tx_Data;Tx_EOB;Tx_Last;Tx_Ready;Tx_Valid;Unary Minus;Valid;Valid_In;Valid_Out;i16c;readPort;u

BLOCKTYPE:
ArrayPlot;Bit Concat;Bit Slice;Compare To Zero;Complex to Magnitude-Angle;ComplexToRealImag;Constant;DLatch;DataTypeConversion;Delay;Detect Decrease;Detect Increase;Display;FFT;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;NCO;Outport;Product;RealImagToComplex;RelationalOperator;Sample and Hold;Selector;Sum;Switch;Tapped Delay Enabled Synchronous;Terminator;UnaryMinus


MODELNAME: energyDetectorModel
PATH: toolbox/wt/slwt/energydetector/energyDetectorModel.slx
ANNOTATION: Internal Signal for test Data Integration RFNoc Wrapper Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 3;2;5;2;1;2;7;10;53;1;1;4;8;22;17;93;5;1;75;2;2;2;1;2;10;4;5
CHECKSUM: 9D05D743E952BF49B4120022EB817AC5
PRODUCT: Fixed-Point Designer;MATLAB;Simulink
BLOCK:
 Demux ; SFunction ; Terminator ;Bit Concat;Bit Set;Bit Slice;Bitwise Operator;Compare To Constant;Complex to Real-Imag;Constant;CountNum;D;DIV;Data Output Converter;Data Packager;Data Type Conversion;DataEob;DataIn;DataInEOB;DataInStream;DataLast;DataLastInStream;DataLastOutStream;DataOut;DataOutEOB;DataOutStream;DataReadyInStream;DataReadyOutStream;DataStream;DataValid;DataValidInStream;DataValidOutStream;Delay;Detect Change;Divide;Dual Delayer;ED ACC;Enable;Enabled Subsystem;Energy Accumulator;Energy Detector Simulink Model;EnergyDetector;EnergyIncreaseScaler;EnergyIncreaseThreshold;EnergySum;EnergyThreshold;Finish;Float Typecast;FrameCountNum;FrameNum;From;Goto;Input Model;Input System;Logical Operator;N;Normalizer;OutputSel;OutputSelect;PacketSize;PacketSizeOut;Product;Q;RatioOut;Real-Imag to Complex;RecordNum;RecordNumber;RecorderState;Reference;Relational Operator;Reset;Rst;Scope;Signal Detection;SubSystem;System Controller;SystemRst;SystemState;SystemTimeHigh;SystemTimeLow;Terminator;Thresholding;TimeoutHigh;TimeoutLow;To Workspace;TriggerOffset;Unit Delay Resettable Synchronous;ValidOut;Variable Delayer;WindowLen;WindowLength;acc_init;acc_init_enb;adp_normalizer;adp_threshold_in;count_num;data_in;data_out;data_out_d;data_validin;delay_data_in;delay_len;energy_in;enregy_out;eob;eob_in;eob_out;fix_threshold_in;frame_num;last_in;last_out;n_init_assert;n_init_assert_out;n_input_valid;packager_enb;packet_size_in;packet_size_out;q0_in;ratio_in;ratio_out;ready_in;ready_out;rec_num;recorder_rst;rst;rst_out;sel;state_out;sys_rst;timeout_high;timeout_low;trigger_in;trigger_offset;trigger_out;u;valid_in;valid_out

BLOCKTYPE:
Bit Concat;Bit Set;Bit Slice;Bitwise Operator;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Change;EnablePort;FloatTypecast;From;Goto;Inport;Logic;MATLABSystem;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Scope;Terminator;ToWorkspace;Unit Delay Resettable Synchronous


MODELNAME: OFDMHWGenModel
PATH: toolbox/wt/slwt/ofdm/OFDMHWGenModel.slx
CHECKSUM: 4F6FCA172718DCB1D0A2A965BDD7F26F
PRODUCT: DSP HDL Toolbox;DSP System Toolbox;MATLAB;Simulink
EXTERNALFILE_REFERENCE: whdlOFDMRx___Model_Block___whdlOFDMTx.slx___Model_Block___
ANNOTATION:
 Add Block is used to obtain integer index to Lookup Table Range of x_f=[1,4) S1 S1 S0 S1 S1 S0 Range of x_e=[1,2) nFramesSynced Tap Points Status Signal Generator OFDM Receiver Status Signals Status Vector nFramesSynced If packetValid is true, OFDM Tx accepts input payload data and outputs proper waveform. If packetValid is false, OFDM Tx doesnt accept input data and outputs random signal. NO HDL Block Tx Data Ports Tap Points  Data tlast generation OFDM Transmiter  Wireless Testbench OFDM Hardware Model Copyright 2020-2021 The MathWorks, Inc.  OFDM Transmitter  AWGN Channel  OFDM Receiver  Copyright 2022 The MathWorks, Inc.  OFDM Receiver  Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ; dBtoLinearConverter;1-D Lookup Table;AWGNChannel;AWGNGenerator;Add;Apply CFO;BER;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;CFO;CIC Decimation HDL Optimized;CPECtrl;Capture Data Bits;ChData_In;ChData_Out;ChLast_In;ChLast_Out;ChReadyEn;ChReady_In;ChReady_Out;ChValid_In;ChValid_Out;Channel Control;Compare To Constant;Complex to Real-Imag;ConcatandExtract;Constant;CreateStateVector;Data Type Conversion;Delay;Detect Increase;Diagnostic Decoder;DiscreteFIRFilter HDLOptimized;Display;Downsample;Enable;EnableTapPoints;Falling Edge Detector;From;FunctionEvaluation;Gain;GaussianNoiseWithReqVar;GaussianNoiseWithUnitVar;Goto;HDL Counter;Logical Operator;MATLAB Function;MT;Multiport Switch;NCO HDL Optimized;Normalized by subcarrier space;OFDMReceiver;OFDMRx;OFDMTransmit;OFDMTransmitter;OFDMTx;OR;Prepare Inputs;PrepareOutputs;Product;RangeReconstruction;RangeReduction;Real-Imag to Complex;Reference;Relational Operator;Repeat;ResetOut;ResetTP;RxData_In;RxData_Out;RxLast_In;RxLast_Out;RxReadyEn;RxReady_In;RxReady_Out;RxTapData;RxValidEn;RxValid_In;RxValid_Out;SNRdB;SelectPayloadData;Send Payload Data;Shift Arithmetic;Signal Specification;SinCos;Sine HDL Optimized;SqrtEval;SqrtImplementation;SubSystem;Subsystem;Subtract;Switch;TapPoints;TapPointsEnable;TausURNG;TausUniformRandGen;Terminator;To Workspace;TriggerCapture;TriggerStateCapture;TriggerStatesCapture;TxData_In;TxData_Out;TxLast_In;TxLast_Out;TxReadyEn;TxReady_In;TxReady_Out;TxStop;TxTapData;TxTapData_Out;TxTapLast_Out;TxTapReady_In;TxTapValid_Out;TxValid_In;TxValid_Out;Unit Delay Enabled Synchronous;Upsample;White Gaussian Noise Generator;a;awgn;b;bitCount;bitErrors;chEqCtrl;codeRate;codeRateIndex;dataIn;dataOut;dataPoints;dataValid;decodedCodeRate;decodedModType;decodedRate;diagBus;displayReset;e;enableCPECorrec;enableChanEqui;eobout;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;freq;freqOffsetEstimate;g;g1(16,15);headerCaptred;headerPoints;headerValid;impairmentControl;in;initial reset;leadingZeroDetector;log;logImplementation;modType;modTypeIndex;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;noise;noiseVar;numBitErrors;numBitsReceived;nxtBit;out;packetValid;pass;passIn;passOut;ready;reset;resetcounter;rst;rxData;rxDataOut;rxValid;rxValidOut;snrdB;sqrt(noisePow/2);txData;txDataOut;txValid;txValidOut;txvalid;u;u0(16,16);u0(48,48);u1(16,16);userBits;userBitsValid;valid;validIn;validOut;whdlOFDMRx Model;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;BusCreator;BusSelector;CIC Decimator;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Increase;Discrete FIR Filter;Display;DownSample;EnablePort;From;Gain;Goto;HDL Counter;Inport;Logic;Lookup_n-D;ModelReference;MultiPortSwitch;NCO;Outport;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;SignalSpecification;Sine and Cosine HDL optimized block;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Synchronous;Upsample

BLOCKTYPE_FREQUENCY:
14;6;19;4;21;1;4;1;2;5;42;58;109;3;3;2;10;13;1;47;5;32;11;93;15;11;2;2;1;100;9;2;2;4;3;1;2;14;20;11;1;2;2


MODELNAME: OFDMProtectedGenModel
PATH: toolbox/wt/slwt/ofdm/OFDMProtectedGenModel.slx
CHECKSUM: BF1B3B5A6364362DF09E36D0E7D5CC01
PRODUCT: Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink
EXTERNALFILE_REFERENCE: whdlOFDMRx___Model_Block___whdlOFDMTx.slx___Model_Block___
ANNOTATION:
 Add Block is used to obtain integer index to Lookup Table Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2) Simulation Status Signals Vector OFDM Receiver Status Signal Generator Simulation Tap Points If packetValid is true, OFDM Tx accepts input payload data and outputs proper waveform. If packetValid is false, OFDM Tx doesnt accept input data and outputs random signal. Tx Data Ports Tap Points  Data tlast generation OFDM Transmiter  Wireless Testbench OFDM Model Copyright 2020-2021 The MathWorks, Inc.  OFDM Transmitter  AWGN Channel  OFDM Receiver  Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; Denormalization ; SFunction ; Terminator ; dBtoLinearConverter;1-D Lookup Table;AWGNChannel;AWGNGenerator;Add;Apply CFO;BER;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;CFO;CIC Decimation HDL Optimized;CPECtrl;Capture Tx Waveform;ChData_In;ChData_Out;ChLast_In;ChLast_Out;ChReadyEn;ChReady_In;ChReady_Out;ChValid_In;ChValid_Out;Channel Control;Compare To Constant;Complex to Real-Imag;ConcatandExtract;Constant;Data;Data Constellation Diagram;Data Type Conversion;DataMode;Delay;Diagnostic Decoder;DiscreteFIRFilter HDLOptimized;DisplayStatus;Downsample;Enable;EnableStatusGUI;EstimatedCFO;Falling Edge Detector;From;Function Evaluation;FunctionEvaluation;Gain;GaussianNoiseWithReqVar;GaussianNoiseWithUnitVar;Goto;HDL Counter;Header Constellation Diagram;In;Last;Logical Operator;MATLAB Function;MT;NCO HDL Optimized;Normalized by fs;OFDMReceiver;OFDMRx;OFDMTransmit;OFDMTransmitter;OFDMTx;PlotConstellation;PlotPowerSpectrum;Prepare Inputs;PrepareOutputs;Product;Range Reconstruction;RangeReconstruction;RangeReduction;Real-Imag to Complex;Reference;Relational Operator;Repeat;ResetOut;RxData_In;RxData_Out;RxLast_In;RxLast_Out;RxReadyEn;RxReady_In;RxReady_Out;RxValid_In;RxValid_Out;SNRdB;SelectPayloadData;Selector;Send Payload Data;Shift Arithmetic;Signal Specification;Sine HDL Optimized;SineCos;Spectrum Analyzer;Spectrum Analyzer_CCDF;Spectrum Analyzer_Convert;Spectrum Analyzer_PAPR;Spectrum Analyzer_RelPwr;SpectrumData_Out;SpectrumLast_Out;SpectrumReady_In;SpectrumValid_Out;SqrtEval;SqrtImplementation;Status Signals;StatusGUI;StatusInfo;StatusSignals;SubSystem;Submatrix;Subsystem;Subtract;Switch;TData;TLast;TValid;TapPointEn;TausURNG;TausUniformRandGen;Terminator;To Workspace;TxData_In;TxData_Out;TxLast_In;TxLast_Out;TxReadyEn;TxReady_In;TxReady_Out;TxTapPointEn;TxValid_In;TxValid_Out;Unit Delay Enabled Synchronous;Upsample;Valid;Vector Concatenate;White Gaussian Noise Generator;a;awgn;b;bitCount;bitErrors;chEqCtrl;codeRate;codeRateIndex;dataIn;dataOut;dataPoints;dataValid;decodedCodeRate;decodedModType;decodedRate;diagBus;displayReset;e;enableCPECorrection;enableChannelEqualization;enableStatusGUI;estimatedCFO;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;freq;freqOffsetEstimate;g;g1(16,15);headerCaptred;headerPoints;headerValid;impairmentControl;in;initial reset;log;logImplementation;modType;modTypeIndex;nBitErrors;nBitReceived;nDataCRCFail;nDataCRCPass;nFramesSynced;nFramessynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived;noise;noiseVar;nxtBit;out;packetValid;pass;passIn;passOut;ready;reset;resetStatus;resetcounter;rst;rxData;rxDataOut;rxValid;rxValidOut;snrdB;sqrt(noisePow/2);txData;txDataOut;txValid;txValidOut;txvalid;u;u0(16,16);u0(48,48);u1(16,16);userBits;userBitsValid;valid;validIn;validOut;whdlOFDMRx Model;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;BusCreator;BusSelector;CIC Decimator;Compare To Constant;ComplexToRealImag;Concatenate;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Discrete FIR Filter;Display;DownSample;EnablePort;From;Gain;Goto;HDL Counter;Inport;Logic;Lookup_n-D;ModelReference;NCO;Outport;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;Selector;SignalSpecification;Sine and Cosine HDL optimized block;SpectrumAnalyzer;Submatrix;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Synchronous;Upsample;dsp.simulink.PowerMeter

BLOCKTYPE_FREQUENCY:
13;6;19;10;21;1;4;1;1;5;3;38;2;58;80;4;2;2;13;4;41;6;36;10;122;16;11;2;1;100;9;5;5;4;4;10;1;2;1;4;14;12;14;3;2;2;1


MODELNAME: OFDMSimModel
PATH: toolbox/wt/slwt/ofdm/ofdm_protected/OFDMSimModel.slx
BLOCKTYPE_FREQUENCY: 6;18;2;18;11;1;2;4;19;2;14;34;2;3;11;3;3;1;10;1;4;5;3;3;1
CHECKSUM: A7DD1B444F78AF76A76C7F96655B1473
PRODUCT: Communications Toolbox;DSP System Toolbox;MATLAB;Simulink
EXTERNALFILE_REFERENCE: AWGNChannel___Model_Block___OFDMReceiver___Model_Block___OFDMTransmitter___Model_Block___
ANNOTATION:
 Wireless Testbench OFDM Model Copyright 2020-2021 The MathWorks, Inc.  OFDM Transmitter  AWGN Channel  OFDM Receiver  Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; Denormalization ; SFunction ; Terminator ;AWGNChannel;Bit Slice;Capture Tx Waveform;Constant;Data;Data Constellation Diagram;Data Type Conversion;DataMode;Delay;DisplayStatus;Enable;EnableStatusGUI;EstimatedCFO;From;Goto;Header Constellation Diagram;In;Last;Logical Operator;MATLAB Function;Normalized by fs;OFDMReceiver;OFDMTransmitter;PlotConstellation;PlotPowerSpectrum;Real-Imag to Complex;Reference;Relational Operator;Selector;Spectrum Analyzer;Spectrum Analyzer_CCDF;Spectrum Analyzer_Convert;Spectrum Analyzer_PAPR;Spectrum Analyzer_RelPwr;Status Signals;StatusGUI;StatusSignals;SubSystem;Submatrix;Subsystem;Switch;TData;TLast;TValid;Terminator;To Workspace;Valid;codeRate;decodedCodeRate;decodedModType;enableStatusGUI;estimatedCFO;modType;nBitErrors;nBitReceived;nDataCRCFail;nDataCRCPass;nFramesSynced;nFramessynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived;snrdB;txData

BLOCKTYPE:
Bit Slice;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Display;EnablePort;From;Gain;Goto;Inport;Logic;ModelReference;Outport;RealImagToComplex;RelationalOperator;S-Function;Selector;SpectrumAnalyzer;Submatrix;Switch;Terminator;ToWorkspace;dsp.simulink.PowerMeter


MODELNAME: preambleDetectorModel
PATH: toolbox/wt/slwt/preambledetector/preambleDetectorModel.slx
CHECKSUM: E983DE829679F571E1FA75C664FF0658
PRODUCT: DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Simulink
ANNOTATION:
+ 1 The reset here should be asserted at least for 15 clock cycles.  Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;12-bit LZC;4-Bit BZC_;4-bit BZC;A;AND;Abs;AccHigh;AccLow;AccOut;Accumulator HDL Optimized;Add;Adder;Assertion;Auto Scaler;Auto Scaler0 In;Auto Scaler0 Out;Auto Scaler1 In;Auto Scaler1 Out;B;Bin Logic;Bit Concat;Bit Set;Bit Shift;Bit Slice;Bitwise Operator;Bitwise XOR;Buffer Controller;Bus Creator;Bus Selector;C;CIn;Carry;CarryOut;CoeffEOB;CoeffIn;CoeffInStream;CoeffLastInStream;CoeffReadyOutStream;CoeffValidInStream;Coeffcients;Coefficients Controller;Coefficients Stream;Compare To Constant;Complex Multiply;Complex Power;Complex to Real-Imag;Constant;CorrOut;CorrValidIn;CorrValidOut;Correlation and Energy;CountNum;Count_Num;CustomEnergy;CustomThreshold;DIn;DOut;DValidIn;DValidOut;Data;Data Output Converter;Data Package;Data Packager;Data Selector;Data Stream;Data Type Conversion;Data Type Duplicate;Data Type Propagation;Data and Integrator;DataEOB;DataIn;DataInStream;DataLastInStream;DataLastOutStream;DataOut;DataOutStream;DataPush;DataReadyInStream;DataReadyOutStream;DataValidInStream;DataValidOut;DataValidOutStream;Delay;DelayLine;DelayRst;Delay_o;DetIn;Detect Decrease;Detect Increase;Differentiator;Direct Multiply;Divide;Dual Port RAM;Dual Rate Dual Port RAM;EOB;EOB Latch;EOBEnb;Enable;Enabled Subsystem;EnergyData;EnergyDataOut;EnergyOut;EnergyValidOut;FData;FDataValid;FFT;FFT Block;FFT Block Controller;FFT Clock;FFT Controller;FFT Finish;FFT Rst;FFT System;FFT0 Data;FFT0 End;FFT0 Start;FFT0 Valid;FFT1 Data;FFT1 End;FFT1 Valid;FIFO W Counter;FIR Scaler;FP Convert;FP Scaler;FTData;FTDataValid;FTValid;FilterData;FilterDataOut;FixedThreshold;Float Typecast;Floating Converter;ForceFFTRst;FrameCountNum;FrameNum;Frequency Domain Filter;From;Get State;Goto;HDL Counter;IFFT;IFFT FIFO;IFFT Set;IFFT0 Block;In;Input Model;Input System;Integrator;LC Length;LCNum;Last;Left Shifter;Load;Logical Operator;MaxOut;Min LZC;Multiport Switch;NOT;OR;Out;OutputSel;Overlapping Add;PD;PDRst;Package Reset;PacketOut;PacketSize;Pow;Power Optimized;Preamble Length;PreambleDetector;PreambleLen;PreambleScaler;Product;Program Start;ProgramStart;Q;R;RAM_state_out;RFData;RFDataOut;RFDataValid;Real Imag Abs Max;Real-Imag to Complex;Rec Num;Record Number;RecordNum;RecorderEnb;RecorderRst;Reference;Relational Operator;Rst;SSState;Scaler;Scope;Sel;Shift Arithmetic;ShifterIn;ShifterOut;Simple Dual Port RAM;Spectrum Sensing;SubSystem;Subsystem;Sum;Switch;Sys Rst;SysRst;SysState;System Controller;System Reset;System Timmer;SystemTimeHigh;SystemTimeLow;TData;TDataValid;Terminator;ThOffset;ThSel;Threshold Offset;Threshold Scaler;ThresholdOffset;ThresholdScaler;ThresholdSel;ThresholdSelect;Thresholding;TimeoutHigh;TimeoutLow;To Workspace;Trigger Offset;TriggerIn;TriggerOffset;TriggerOut;Unit Delay Enabled Resettable Synchronous;Unit Delay Resettable Synchronous;Valid;Valid Signal Assertion;ValidIn;ValidOut;WT FIFO;XOR;Z;ZeroNum;a;acc_init;acc_init_in;acc_init_out;addr0_out;addr1_out;addr_out;coeff_in;coeff_out;coeff_ready;coeff_valid_out;coeff_validin;coeffin;counter;counter_out;data;data0_in;data1_in;data_in;data_out;data_ready;data_valid;data_validin;data_validout;dataout;debug_enb;debug_valid;delay_len;delay_length;delay_line_ctrl;delay_rst;delayed_data_out;diff_out;dout_;empty;enb;eob_counter_enb;eob_counter_rst;eob_latch_rst;eob_wait_finish;fft0_finish;fft0_finish_in;fft0_finish_out;fft0_validin;fft1_finish;fft1_finish_in;fft1_finish_out;fft1_validin;fft_rst;fft_rst_in;fft_rst_out;fft_start;fft_state_out;force_fft_rst;full;init0_c;init_LZC;last;last_eob;latch_LZC;lc_num;lc_valid;lc_validout;n_coeff_enb;n_data_enb;overalpping;overlapping;overlapping_data_out;packetSize;padding_enb;padding_num;pop_c;popc_in;popc_out;preamble_len;prog_finish;prog_start;push_a;ready;reset;rst;start;start/rst;start_out;state_out;sys_rst;trigger_in;u;valid0_in;valid1_in;valid_in;valid_out;validin;validout;w_enb;we_out;y

BLOCKTYPE:
Abs;ArithShift;Assertion;Bit Concat;Bit Set;Bit Shift;Bit Slice;Bitwise Operator;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Constant;Data Type Propagation;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Detect Decrease;Detect Increase;Dual-port RAM;Dual-rate dual-port RAM;EnablePort;FFT;FloatTypecast;From;Goto;HDL Counter;IFFT;Inport;Logic;MATLABSystem;MultiPortSwitch;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Scope;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Resettable Synchronous

BLOCKTYPE_FREQUENCY:
6;4;1;32;2;2;69;6;2;2;2;20;33;6;58;7;334;16;2;2;1;1;4;2;15;121;79;8;2;366;21;1;2;297;16;13;5;16;3;6;22;10;58;4;10;26


MODELNAME: ramp64
PATH: toolbox/wt/slwt/ramp64/ramp64.slx
ANNOTATION: Copyright 2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;4;19;1;6;1;4;12;3;11;4;1;1;4;6;2
CHECKSUM: 8A849933A5EECCC2471A551797510B72
PRODUCT: DSP System Toolbox;MATLAB;Simulink
BLOCK:
Bit Concat;Bit Slice;Constant;Data;Data Type Conversion;Delay;Enable;HDL Counter;Last;Logical Operator;MinimumPacket;MinimumSpacing;PacketSize;RampGenerator;Ready;Reference;Relational Operator;SampleRate;Scope;Signal From Workspace;SubSystem;Subtract;Sum;Switch;TLast;Terminator;Valid;ValidCounter;gainct;i_tdata;i_tlast;i_tready;i_tvalid;o_data;o_last;o_ready;o_tdata;o_tlast;o_tready;o_tvalid;o_valid;r_enabledut;r_gain;r_rampmax;r_tlastsel;r_validrate;r_validsel;ramp

BLOCKTYPE:
Bit Concat;Bit Slice;Constant;DataTypeConversion;Delay;EnablePort;HDL Counter;Inport;Logic;Outport;RelationalOperator;Scope;Signal From Workspace;Sum;Switch;Terminator


MODELNAME: farrow
PATH: toolbox/wt/slwt/utils/blocks/farrow.slx
ANNOTATION: Control Copyright 2021 The MathWorks, Inc. Radio side DDC Host
BLOCKTYPE_FREQUENCY: 1;2;2;3;4;1;1;1;2;1;1;5;1;1;8
CHECKSUM: 3FF8A69C6CE364323CF2CF61388A9AA3
PRODUCT: DSP HDL Toolbox;DSP System Toolbox;MATLAB;Simulink
BLOCK:
Bit Concat;Bit Slice;Complex to Real-Imag;DDC;Data Type Conversion;Enable;In;Out;Real-Imag to Complex;Reference;SineWave;SpectrumAnalyzer;SubSystem;Terminator;eob;farrow;hastime;pktsize;rate;ready;reset;spectrum;timestamp;tlastin;u;uint2complex;valid

BLOCKTYPE:
Bit Concat;Bit Slice;ComplexToRealImag;Constant;DataTypeConversion;EnablePort;FIR Decimator;HDL Counter;Inport;Outport;RealImagToComplex;Signal From Workspace;Sine Wave;SpectrumAnalyzer;Terminator


MODELNAME: mviterbi_RAMTraceback_modelgen
PATH: toolbox/comm/commhdloptimized/commutilities/mviterbi_RAMTraceback_modelgen.mdl
ANNOTATION: Copyright 2010-2020 The MathWorks, Inc.
BLOCKTYPE: Demux;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;3;3;2;2
CHECKSUM: E672D21285C32ED95982F04AADBC7F72
PRODUCT: Communications Toolbox;Fixed-Point Designer;Simulink
PRODUCT_BASECODE: CM
BLOCK:
 Demux ; SFunction ; Terminator ;In;Out;SubSystem;decoded;in;viterbi_RAM;viterbi_RAM_Traceback_param


MODELNAME: rcosflt_tb
PATH: toolbox/edalink/foundation/hdllink/demo_src/tutorial/rcosflt_tb.mdl
ANNOTATION: Copyright 2010 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;2;3;2;1;2;2;2;2
CHECKSUM: F7105452D2959F57764949A71D9EDA9F
PRODUCT: HDL Verifier;Simulink
PRODUCT_BASECODE: ES
BLOCK:
Bus Creator;Constant;Data Type Conversion;Integer Delay;Product;Pulse Generator;Random Number;Reference;Scope;Sign

BLOCKTYPE:
BusCreator;Constant;DataTypeConversion;DiscretePulseGenerator;Integer Delay;Product;RandomNumber;Scope;Signum


MODELNAME: mrefrobotarm
PATH: toolbox/nnet/nncontrol/blocks/mrefrobotarm.mdl
BLOCKTYPE_FREQUENCY: 1;1;1;4;2;1;1;1;1;1;1;1
CHECKSUM: 30A00657BC34B64DBEDCCCCC28DAEED6
PRODUCT: Deep Learning Toolbox;MATLAB;Simulink
PRODUCT_BASECODE: NN
ANNOTATION:
This system simulates model reference control of a single-link robot arm. Double-click on the Model Reference Controller block to train the neural network controller and plant model. For more information on what the controller does, look under the mask of the Model Reference Controller block. Neural Network Model Reference Control of a Robot Arm (Double click on the ? for more info) To start and stop the simulation, use the Start/Stop selection in the Simulation pull-down menu

BLOCK:
Clock;Friction;Gravity;Level-2 MATLAB S-Function;Model Reference Controller;More Info;Mux;Plant (Robot Arm);Position;Random Reference;Reference;SubSystem;Sum;Velocity;X(2Y) Graph;u;x;y

BLOCKTYPE:
Clock;Fcn;Gain;Inport;Integrator;M-S-Function;Mux;NN Model Reference Control;Outport;Sum;UniformRandomNumber;X(2Y) scope.


MODELNAME: mrefrobotarm2
PATH: toolbox/nnet/nncontrol/blocks/mrefrobotarm2.mdl
BLOCKTYPE_FREQUENCY: 1;15;5;8;12;26;2;1;4;1;1;13;1;9;7;2;1;3;1;2
CHECKSUM: 35AE6BE110C1F2DA70F9599CDD7B3460
PRODUCT: Deep Learning Toolbox;MATLAB;Simulink
PRODUCT_BASECODE: NN
ANNOTATION:
This system simulates model reference control of a single-link robot arm. Double-click on the Model Reference Controller block to train the neural network controller and plant model. For more information on what the controller does, look under the mask of the Model Reference Controller block. Neural Network Model Reference Control of a Robot Arm (Double click on the ? for more info) To start and stop the simulation, use the Start/Stop selection in the Simulation pull-down menu

BLOCK:
Clock;Constant;Control Signal;Discrete State-Space;Exp;Fcn;Friction;Gain;Gravity;In;Level-2 MATLAB S-Function;Matrix Gain;Model Reference Controller;More Info;Mux;NN Controller;NN Plant;Out;Plant (Robot Arm);Plant Output;Position;Random Reference;Reciprocal;Reference;Saturation;SubSystem;Sum;Switch;Terminator;Unit Delay;Velocity;XY Graph;Zero-Order Hold;a;n;netsum;one;purelin;r;tansig;u;uhat;x;y;yhat

BLOCKTYPE:
Clock;Constant;DiscreteStateSpace;Fcn;Gain;Inport;Integrator;M-S-Function;Math;Mux;NN Model Reference Control;Outport;Saturate;Sum;Switch;Terminator;UniformRandomNumber;UnitDelay;XY scope.;ZeroOrderHold


