# MODELS

MODELNAME: SF_ChartFltrAllInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartFltrAllInstnc_Ex.slx
BLOCKTYPE_FREQUENCY: 3;8;3;3;1;16;2;2;4
CHECKSUM: 04A31FE84739F1D849415799F2F3769E
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model implements a coverage filter to exclude the coverage for all blocks with tye Stateflow in a model Copyright 2008-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;A;ArithLogic;Aux_Switch;Aux_Switch_State;B;C;Constant;D;Data Type Conversion;Demux;E;F;From Workspace;Pulse Generator;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch

BLOCKTYPE:
Constant;DataTypeConversion;Demux;DiscretePulseGenerator;FromWorkspace;Inport;Outport;S-Function;Terminator


MODELNAME: SF_ChartFltrAllInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartFltrAllInstnc_Jstfy.slx
BLOCKTYPE_FREQUENCY: 3;8;3;3;1;16;2;2;4
CHECKSUM: 4D7CA867999E3FB4E5B6AF033B2B8B14
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model implements a coverage filter to justify the coverage for all blocks with tye Stateflow in a model Copyright 2008-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;A;ArithLogic;Aux_Switch;Aux_Switch_State;B;C;Constant;D;Data Type Conversion;Demux;E;F;From Workspace;Pulse Generator;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch

BLOCKTYPE:
Constant;DataTypeConversion;Demux;DiscretePulseGenerator;FromWorkspace;Inport;Outport;S-Function;Terminator


MODELNAME: SF_ChartFltrByInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartFltrByInstnc_Ex.slx
BLOCKTYPE_FREQUENCY: 3;8;3;3;1;16;2;2;4
CHECKSUM: 8FA5788A7A43DDD588EF001291EE77C5
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model implements a coverage filter to exclude the coverage for a chart with all descendants in a State Chart in a model Copyright 2008-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;A;ArithLogic;Aux_Switch;Aux_Switch_State;B;C;Constant;D;Data Type Conversion;Demux;E;F;From Workspace;Pulse Generator;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch

BLOCKTYPE:
Constant;DataTypeConversion;Demux;DiscretePulseGenerator;FromWorkspace;Inport;Outport;S-Function;Terminator


MODELNAME: SF_ChartFltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartFltrByInstnc_Jstfy.slx
BLOCKTYPE_FREQUENCY: 3;8;3;3;1;16;2;2;4
CHECKSUM: DCDD35FFAF9536F06F5BBA163CFEDEB4
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2008-2022 The MathWorks, Inc.  This model implements a coverage filter to justify the coverage for a chart with all descendants in a State Chart in a model

BLOCK:
 Demux ; SFunction ; Terminator ;A;Aux_Switch;Aux_Switch_State;B;C;Chart;Constant;D;Data Type Conversion;Demux;E;F;From Workspace;Pulse Generator;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch


MODELNAME: SF_ChartState_Fltr_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartState_Fltr_Ex.slx
BLOCKTYPE: DataTypeConversion;Demux;FromWorkspace;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 5;1;5;10;2;1;2
CHECKSUM: 681A156EB5EA6755F8784A52DFBC4511
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model implements a coverage filter to exclude the coverage for a state with all descendants in a State Chart in a model Copyright 2008-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Aux_Switch;Aux_Switch_State;Data Type Conversion;From Workspace;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch


MODELNAME: SF_ChartTranstn_Fltr_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartTranstn_Fltr_Ex.slx
BLOCKTYPE: DataTypeConversion;Demux;FromWorkspace;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 5;1;5;10;2;1;2
CHECKSUM: E66484E1C5C8A2CD07F9E40CDDCE252B
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model implements a coverage filter to exclude the coverage for a transition in a State Chart in a model Copyright 2008-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Aux_Switch;Aux_Switch_State;Data Type Conversion;From Workspace;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch


MODELNAME: SF_ChartTranstn_Fltr_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_ChartTranstn_Fltr_Jstfy.slx
BLOCKTYPE: DataTypeConversion;Demux;FromWorkspace;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 5;1;5;10;2;1;2
CHECKSUM: 3A744DB4962BE71335B01639DB872627
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model implements a coverage filter to justify the coverage for a transition in a State Chart in a model Copyright 2008-2022 The MathWorks, Inc.


MODELNAME: SF_Ovrflw_ChartFltrAllInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_Ovrflw_ChartFltrAllInstnc_Ex.slx
BLOCK: Demux ; SFunction ; Terminator ;Constant;Out;Saturate;SubSystem;u;y
BLOCKTYPE: Constant;Demux;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;2;4;8;2;2
CHECKSUM: 77B65D2B5E5FF278804A08505F4394D9
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2022 The MathWorks, Inc.  This model implements a coverage filter to exclude the coverage for all blocks of type Stateflow in a model


MODELNAME: SF_Ovrflw_ChartFltrAllInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_Ovrflw_ChartFltrAllInstnc_Jstfy.slx
BLOCK: Demux ; SFunction ; Terminator ;Constant;Out;Saturate;SubSystem;u;y
BLOCKTYPE: Constant;Demux;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;2;4;8;2;2
CHECKSUM: 03652A184920E4DA8CD85BD1343BE80F
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2022 The MathWorks, Inc.  This model implements a coverage filter to justify the coverage for all blocks of type Stateflow in a model


MODELNAME: SF_Ovrflw_ChartFltrByInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_Ovrflw_ChartFltrByInstnc_Ex.slx
BLOCK: Demux ; SFunction ; Terminator ;Constant;Out;Saturate;SubSystem;u;y
BLOCKTYPE: Constant;Demux;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;2;4;8;2;2
CHECKSUM: 76F8180FC30C15ADF0C4ECAE14F6F521
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2022 The MathWorks, Inc.  This model implements a coverage filter to exclude the coverage for a chart with all descendants in a State Chart in a model


MODELNAME: SF_Ovrflw_ChartFltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SF_Ovrflw_ChartFltrByInstnc_Jstfy.slx
BLOCK: Demux ; SFunction ; Terminator ;Constant;Out;Saturate;SubSystem;u;y
BLOCKTYPE: Constant;Demux;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;2;4;8;2;2
CHECKSUM: 32AE3BA9A9C043607551A943B72FEBBC
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2022 The MathWorks, Inc.  This model implements a coverage filter to justify the coverage for a chart with all descendants in a State Chart in a model


MODELNAME: SLBscBlksOutcms_FltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlksOutcms_FltrByInstnc_Jstfy.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: C23E24614616678CDD0FC4D92593B283
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model justifies the coverage for unachieved outcomes of basic Simulink blocks by instance Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Abs_SubSystem;Chirp Signal;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Gain;In;In_RelOp_matrix;Logical_SubSystem;MATLABfun_Subsystem;MinMax;MinMax_DTC_SubSystem;Mux;Reference;Relational Operator;Relational_SubSystem;Repeating Sequence Stair;Saturation_SubSystem;Sine Wave;Sine Wave p=;SubSystem;Sum;Switch;Switch_Subsystem;Terminator;Whie_Subsystem;eml;no_ovf;onescallim;scalar_int;scalar_not;scalar_uncovered;system;u;while;y

BLOCKTYPE:
Abs;Compare To Constant;Compare To Zero;Constant;DataTypeConversion;Demux;Gain;Inport;Logic;MinMax;MultiPortSwitch;Mux;Outport;RelationalOperator;Repeating Sequence Stair;S-Function;Saturate;Sin;Sum;Switch;Terminator;WhileIterator;chirp


MODELNAME: SLBscBlks_FltrAllInstnc_Ex1
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrAllInstnc_Ex1.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: 1F50E586BD8014381D55A23E06B961C3
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model excludes all instances of basic Simulink blocks Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Abs_SubSystem;Chirp Signal;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Gain;In;In_RelOp_matrix;Logical_SubSystem;MATLABfun_Subsystem;MinMax;MinMax_DTC_SubSystem;Mux;Reference;Relational Operator;Relational_SubSystem;Repeating Sequence Stair;Saturation_SubSystem;Sine Wave;Sine Wave p=;SubSystem;Sum;Switch;Switch_Subsystem;Terminator;While_Subsystem;eml;no_ovf;onescallim;scalar_int;scalar_not;scalar_uncovered;system;u;while;y

BLOCKTYPE:
Abs;Compare To Constant;Compare To Zero;Constant;DataTypeConversion;Demux;Gain;Inport;Logic;MinMax;MultiPortSwitch;Mux;Outport;RelationalOperator;Repeating Sequence Stair;S-Function;Saturate;Sin;Sum;Switch;Terminator;WhileIterator;chirp


MODELNAME: SLBscBlks_FltrAllInstnc_Ex3
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrAllInstnc_Ex3.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: A97AEC389427F3014C5195E12E27FC89
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model excludes all instances of MATLAB Function blocks Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Abs_SubSystem;Chirp Signal;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Gain;In;In_RelOp_matrix;Logical_SubSystem;MATLABfun_Subsystem;MinMax;MinMax_DTC_SubSystem;Mux;Reference;Relational Operator;Relational_SubSystem;Repeating Sequence Stair;Saturation_SubSystem;Sine Wave;Sine Wave p=;SubSystem;Sum;Switch;Switch_Subsystem;Terminator;While_Subsystem;eml;no_ovf;onescallim;scalar_int;scalar_not;scalar_uncovered;system;u;while;y


MODELNAME: SLBscBlks_FltrAllInstnc_Jstfy1
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrAllInstnc_Jstfy1.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: E21FFD5C53187AF30249DEDF07AAD86A
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model justifies the unachieved coverage for all instances of basic Simulink blocks Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SLBscBlks_FltrAllInstnc_Jstfy3
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrAllInstnc_Jstfy3.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: 251AD6C5CAA0BD85959F3CACBCECF77F
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model justifies the unachieved coverage for all instances of MATLAB Function blocks Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SLBscBlks_FltrByInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrByInstnc_Ex.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: C0774E89923595A98E4FC542C91FA0C1
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model excludes the basic Simulink blocks with unachieved coverage by instance Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Abs_SubSystem;Chirp Signal;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Gain;In;In_RelOp_matrix;Logical_SubSystem;MATLABfun_Subsystem;MinMax;MinMax_DTC_SubSystem;Mux;Reference;Relational Operator;Relational_SubSystem;Repeating Sequence Stair;Saturation_SubSystem;Sine Wave;Sine Wave p=;SubSystem;Sum;Switch;Switch_Subsystem;Terminator;Whie_Subsystem;eml;no_ovf;onescallim;scalar_int;scalar_not;scalar_uncovered;system;u;while;y


MODELNAME: SLBscBlks_FltrByInstnc_Ex_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrByInstnc_Ex_Jstfy.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: 43449C094A99C2489BFECA27BE83AD9A
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model excludes and justifies the basic Simulink blocks with unachieved coverage by instance Copyright 2022 The MathWorks, Inc.


MODELNAME: SLBscBlks_FltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_FltrByInstnc_Jstfy.slx
BLOCKTYPE_FREQUENCY: 2;1;2;27;9;1;2;4;2;2;1;1;1;4;1;1;2;8;1;2;18;2;1
CHECKSUM: 03BFF498CCC3C1D509419F9025231788
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
3 Amplitudes, Phase shifted This model justifies the unachieved coverage for basic Simulink blocks by instance Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Abs_SubSystem;Chirp Signal;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Gain;In;In_RelOp_matrix;Logical_SubSystem;MATLABfun_Subsystem;MinMax;MinMax_DTC_SubSystem;Mux;Reference;Relational Operator;Relational_SubSystem;Repeating Sequence Stair;Saturation_SubSystem;Sine Wave;Sine Wave p=;SubSystem;Sum;Switch;Switch_Subsystem;Terminator;Whie_Subsystem;eml;no_ovf;onescallim;scalar_int;scalar_not;scalar_uncovered;system;u;while;y


MODELNAME: SLBscBlks_OvflwOutcms_FltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_OvflwOutcms_FltrByInstnc_Jstfy.slx
BLOCKTYPE: Constant;DataTypeConversion;DotProduct;Gain;Inport;Product;Saturate;Sin;Sum;Terminator;UnaryMinus
BLOCKTYPE_FREQUENCY: 8;18;4;5;17;4;2;2;5;20;2
CHECKSUM: E078E2297077BF2CA25D16441FB8A977
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
scalar vector matrix Coverage for Data Type Conversion blocks scalar scalar vector matrix This model has filter(justification rules) applied for uncovered outcomes of Simulink Basic Blocks having Saturate on Integer Overflow Coverage Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
Add;Constant;Data Type Conversion;DataType Conversion;Dot Product;Product;Saturation;Sine Wave;SubSystem;Sum;Terminator_;Unary Minus;cast;double;double_off;double_single;float;int;int32_int;int8_int;int8_uint;integer;make_matrix;make_vector;never;off;on;single;single_on;sometimes;uint;uint16_double


MODELNAME: SLBscBlks_Ovflw_FltrAllInstnc_Ex1
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_Ovflw_FltrAllInstnc_Ex1.slx
BLOCKTYPE: Constant;DataTypeConversion;DotProduct;Gain;Inport;Product;Saturate;Sin;Sum;Terminator;UnaryMinus
BLOCKTYPE_FREQUENCY: 8;18;4;5;17;4;2;2;5;20;2
CHECKSUM: 7791882451B56A1BE99C90C91F32CB75
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
scalar vector matrix Coverage for Data Type Conversion blocks scalar scalar vector matrix This model has filter(exclusion rules) applied for Simulink Basic Blocks having Saturate on Integer Overflow Coverage Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
Add;Constant;Data Type Conversion;DataType Conversion;Dot Product;Product;Saturation;Sine Wave;SubSystem;Sum;Terminator_;Unary Minus;cast;double;double_off;double_single;float;int;int32_int;int8_int;int8_uint;integer;make_matrix;make_vector;never;off;on;single;single_on;sometimes;uint;uint16_double


MODELNAME: SLBscBlks_Ovflw_FltrAllInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_Ovflw_FltrAllInstnc_Jstfy.slx
BLOCKTYPE: Constant;DataTypeConversion;DotProduct;Gain;Inport;Product;Saturate;Sin;Sum;Terminator;UnaryMinus
BLOCKTYPE_FREQUENCY: 8;18;4;5;17;4;2;2;5;20;2
CHECKSUM: 814126F37E990D5495BB107E1ADB4FA4
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
scalar vector matrix Coverage for Data Type Conversion blocks scalar scalar vector matrix This model has filter(justification rules) applied for all instances of Simulink Basic Blocks having Saturate on Integer Overflow Coverage Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SLBscBlks_Ovflw_FltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SLBscBlks_Ovflw_FltrByInstnc_Jstfy.slx
BLOCKTYPE: Constant;DataTypeConversion;DotProduct;Gain;Inport;Product;Saturate;Sin;Sum;Terminator;UnaryMinus
BLOCKTYPE_FREQUENCY: 8;18;4;5;17;4;2;2;5;20;2
CHECKSUM: 0B01B2AE686CD4BAD2554E75A0E8296A
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
scalar vector matrix Coverage for Data Type Conversion blocks scalar scalar vector matrix This model has filter(justification rules) applied for Simulink Basic Blocks having Saturate on Integer Overflow Coverage Copyright 2014-2024 The MathWorks, Inc.


MODELNAME: SL_LUT_FltrAllInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_LUT_FltrAllInstnc_Ex.slx
BLOCKTYPE_FREQUENCY: 3;2;1;3;3;1;1;3;3;1;6
CHECKSUM: 6960DD962AA5982DAFA9223922DCC5B0
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model provide a coverage filter to exclude the unachieved coverage for all instance of lookup table Vector input  Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
At Fast;Between Break values;Constant;LU;Mux;Prelookup;Reference;Repeating Sequence Stair;Scope;Table_;Terminator;VECT_CONT;VectorInput;size-type

BLOCKTYPE:
Constant;Gain;Interpolation_n-D;Lookup;Lookup_n-D;Mux;PreLookup;Repeating Sequence Stair;Repeating table;Scope;Terminator


MODELNAME: SL_LUT_FltrAllInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_LUT_FltrAllInstnc_Jstfy.slx
BLOCKTYPE_FREQUENCY: 3;2;1;3;3;1;1;3;3;1;6
CHECKSUM: E65467C94733D93543F931CDBDA4CF1A
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model provide a coverage filter to justify the unachieved coverage for all instance of lookup table Vector input  Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
At Fast;Between Break values;Constant;LU;Mux;Prelookup;Reference;Repeating Sequence Stair;Scope;Table_;Terminator;VECT_CONT;VectorInput;size-type

BLOCKTYPE:
Constant;Gain;Interpolation_n-D;Lookup;Lookup_n-D;Mux;PreLookup;Repeating Sequence Stair;Repeating table;Scope;Terminator


MODELNAME: SL_LUT_FltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_LUT_FltrByInstnc_Jstfy.slx
BLOCKTYPE_FREQUENCY: 3;2;1;3;3;1;1;3;3;1;6
CHECKSUM: 7393C5200C5F5079F19A22131DF3C5CA
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model provide a coverage filter to justify the unachieved coverage for an instance of lookup table Vector input  Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
At Fast;Between Break values;Constant;LU;Mux;Prelookup;Reference;Repeating Sequence Stair;Scope;Table_;Terminator;VECT_CONT;VectorInput;size-type

BLOCKTYPE:
Constant;Gain;Interpolation_n-D;Lookup;Lookup_n-D;Mux;PreLookup;Repeating Sequence Stair;Repeating table;Scope;Terminator


MODELNAME: SL_LUT_Fltr_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_LUT_Fltr_Ex.slx
BLOCKTYPE_FREQUENCY: 3;2;1;3;3;1;1;3;3;1;6
CHECKSUM: 3083D5C12CF90B9089C7733B243BDA86
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model provide a coverage filter to exclude the unachieved coverage for an instance of lookup table Vector input  Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_Lib_Fltr_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_Lib_Fltr_Ex.slx
BLOCKTYPE: Compare To Zero;Constant;DataTypeConversion;Display;Logic;Outport;Sum
BLOCKTYPE_FREQUENCY: 2;5;3;4;3;2;2
CHECKSUM: 47703835DADED34AFF40CC2A332C115F
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to exclude all instances of a block from the library Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
Compare To Zero;Constant;Counter;Data Type Conversion;Display;Enabled Subsystem;LogicOp;NOT;Out;Reference;SubSystem;any


MODELNAME: SL_Lib_Fltr_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_Lib_Fltr_Jstfy.slx
BLOCKTYPE: Compare To Zero;Constant;DataTypeConversion;Display;Logic;Outport;Sum
BLOCKTYPE_FREQUENCY: 2;5;3;4;3;2;2
CHECKSUM: 330C8ECAA47BFF70733C7B7813E7B62D
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to justify all instances of a block from the library Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
Compare To Zero;Constant;Counter;Data Type Conversion;Display;Enabled Subsystem;LogicOp;NOT;Out;Reference;SubSystem;any


MODELNAME: SL_RelOpOutcms_Fltr_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_RelOpOutcms_Fltr_Jstfy.slx
BLOCK: CheckCount;Constant;Data Type Conversion;Reference;Step;Terminator;tc
BLOCKTYPE: Constant;DataTypeConversion;RelationalOperator;Running Counter;Step;Terminator
BLOCKTYPE_FREQUENCY: 17;3;10;2;3;8
CHECKSUM: 11EA6D6498DBB137CD0375A3C1298555
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Implement a coverage filter to justify unachieved relational boundary coverage objectives for a block by its path in a model Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_RelOp_FltrAllInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_RelOp_FltrAllInstnc_Ex.slx
BLOCK: CheckCount;Constant;Data Type Conversion;Reference;Step;Terminator;tc
BLOCKTYPE: Constant;DataTypeConversion;RelationalOperator;Running Counter;Step;Terminator
BLOCKTYPE_FREQUENCY: 17;3;10;2;3;8
CHECKSUM: E154AD9968B79F68A913AA785E9F99AD
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Implement a coverage filter to exclude the relational boundary coverage for all instances of a block in the model Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_RelOp_FltrAllInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_RelOp_FltrAllInstnc_Jstfy.slx
BLOCK: CheckCount;Constant;Data Type Conversion;Reference;Step;Terminator;tc
BLOCKTYPE: Constant;DataTypeConversion;RelationalOperator;Running Counter;Step;Terminator
BLOCKTYPE_FREQUENCY: 17;3;10;2;3;8
CHECKSUM: 9BDBDD36C63C29196C8FA7990B8D2CF9
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Implement a coverage filter to justify the relational boundary coverage for all instances of a block in the model Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_RelOp_FltrByInstnc_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_RelOp_FltrByInstnc_Ex.slx
BLOCK: CheckCount;Constant;Data Type Conversion;Reference;Step;Terminator;tc
BLOCKTYPE: Constant;DataTypeConversion;RelationalOperator;Running Counter;Step;Terminator
BLOCKTYPE_FREQUENCY: 17;3;10;2;3;8
CHECKSUM: 6165ABE3652899B0D20928F4A1A93AC0
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Implement a coverage filter to exclude the relational boundary coverage for a block by its path  Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_RelOp_FltrByInstnc_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_RelOp_FltrByInstnc_Jstfy.slx
BLOCK: CheckCount;Constant;Data Type Conversion;Reference;Step;Terminator;tc
BLOCKTYPE: Constant;DataTypeConversion;RelationalOperator;Running Counter;Step;Terminator
BLOCKTYPE_FREQUENCY: 17;3;10;2;3;8
CHECKSUM: C856E00167C9AEA1FBF84579CBD2F720
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Implement a coverage filter to justify the relational boundary coverage for a block by its path  Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_masksubSys_Fltr_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_masksubSys_Fltr_Ex.slx
BLOCK: CheckCount;Compare To Constant;Compare To Zero;Constant;Out;Reference;tc
BLOCKTYPE: Compare To Constant;Compare To Zero;Constant;Outport;RelationalOperator;Running Counter
BLOCKTYPE_FREQUENCY: 2;2;8;4;2;2
CHECKSUM: 7D0669721CAD394B558670F1CF584566
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to exclude coverage for all instances of a masked Subsytem  Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_masksubSys_Fltr_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_masksubSys_Fltr_Jstfy.slx
BLOCK: CheckCount;Compare To Constant;Compare To Zero;Constant;Out;Reference;tc
BLOCKTYPE: Compare To Constant;Compare To Zero;Constant;Outport;RelationalOperator;Running Counter
BLOCKTYPE_FREQUENCY: 2;2;8;4;2;2
CHECKSUM: 8AF4132E7A84AAD67322D6084B1D87D8
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to justify coverage for all instances of a masked Subsytem  Copyright 2014-2022 The MathWorks, Inc.


MODELNAME: SL_subSys_FltrOutcms_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_subSys_FltrOutcms_Jstfy.slx
BLOCKTYPE_FREQUENCY: 6;13;2;3;2;3;1;1;13;1;1;9;10;1;9
CHECKSUM: E709CCFB3F17CE2777DF28002D324FA2
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to justify unachieved coverage for an outcome of a Subsytem  Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
ActionPort;Constant;Else Subsystem;Enable;Gain;If;If Subsystem;In;Logical Operator;Merge;Out;Ramp;Reference;Relational Operator;SubSystem;Sum;Terminator;Terminator_;Trigger;Unit Delay;count;scalar_enb;trig;vector_enb

BLOCKTYPE:
ActionPort;Constant;EnablePort;Gain;If;Inport;Logic;Merge;Outport;Ramp;RelationalOperator;Sum;Terminator;TriggerPort;UnitDelay


MODELNAME: SL_subSys_Fltr_Ex
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_subSys_Fltr_Ex.slx
BLOCKTYPE_FREQUENCY: 6;13;2;3;2;3;1;1;13;1;1;9;10;1;9
CHECKSUM: 532A7CA9CA2EA3865AA2B5285C754DC5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to exclude an instance of a Subsytem  Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
ActionPort;Constant;Else Subsystem;Enable;Gain;If;If Subsystem;In;Logical Operator;Merge;Out;Ramp;Reference;Relational Operator;SubSystem;Sum;Terminator;Terminator_;Trigger;Unit Delay;count;scalar_enb;trig;vector_enb

BLOCKTYPE:
ActionPort;Constant;EnablePort;Gain;If;Inport;Logic;Merge;Outport;Ramp;RelationalOperator;Sum;Terminator;TriggerPort;UnitDelay


MODELNAME: SL_subSys_Fltr_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/SL_subSys_Fltr_Jstfy.slx
BLOCKTYPE_FREQUENCY: 6;13;2;3;2;3;1;1;13;1;1;9;10;1;9
CHECKSUM: 6D0FE15CAD8DB99001210E0FC219B929
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 This model has coverage filter applied to justify an instance of a Subsytem  Copyright 2014-2022 The MathWorks, Inc.

BLOCK:
ActionPort;Constant;Else Subsystem;Enable;Gain;If;If Subsystem;In;Logical Operator;Merge;Out;Ramp;Reference;Relational Operator;SubSystem;Sum;Terminator;Terminator_;Trigger;Unit Delay;count;scalar_enb;trig;vector_enb

BLOCKTYPE:
ActionPort;Constant;EnablePort;Gain;If;Inport;Logic;Merge;Outport;Ramp;RelationalOperator;Sum;Terminator;TriggerPort;UnitDelay


MODELNAME: mCombineObjectives
PATH: toolbox/qualkits/common/slcov/tests/mcov/mCombineObjectives.slx
BLOCKTYPE_FREQUENCY: 1;2;2;11;15;13;1;2;1
CHECKSUM: 6D48C1260795365395CADFD23EC4E061
PRODUCT: IEC Certification Kit;MATLAB;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
The contents of this subsystem are excluded from the code Real-Time Workshop generates. To work correctly this system must continue to * Contain no output ports * Enable its Treat as Atomic Unit parameter * Specify its Mask type parameter as VerificationSubsystem Copyright 2008-2014 The MathWorks, Inc.


MODELNAME: mContinuous
PATH: toolbox/qualkits/common/slcov/tests/mcov/mContinuous.slx
DESCRIPTION: Model Coverage test model for Continuous Library blocks
BLOCKTYPE_FREQUENCY: 5;2;1;4;2;2;2;4;22;2;30;2;2;4;2
CHECKSUM: 196170AA31C51F7687A763EE9C9CE5E6
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Masked Subsystems, not directly instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Copyright 2020 The MathWorks, Inc.

BLOCK:
Constant;Derivative;Enable;Integrator;Integrator Limited;Integrator, Second-Order;Integrator, Second-Order Limited;Memory;NeagtiveCase;PID Controller;PID Controller (2DOF);PositiveCase;Reference;Sine Wave;State-Space;SubSystem;Terminator;Transfer Fcn;Transport Delay;Variable Time Delay;Variable Transport Delay;Zero-Pole

BLOCKTYPE:
Constant;Derivative;EnablePort;Integrator;Memory;PID 1dof;PID 2dof;SecondOrderIntegrator;Sin;StateSpace;Terminator;TransferFcn;TransportDelay;VariableTransportDelay;ZeroPole


MODELNAME: mCumulativeCoverage
PATH: toolbox/qualkits/common/slcov/tests/mcov/mCumulativeCoverage.slx
ANNOTATION: Copyright 2008-2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 6;1;1;1;1;2;1;1;1;6;2;2;6
CHECKSUM: 74892A41351EBE64E9241A895C6E99A6
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
And;C_and_MCDC_Coverage;Constant;D_Coverage;Data Type Conversion;FC_Operator_AND;Gain;Lookup Table;Rate Transition;Reference;SLDV_Coverage;SatOnIntOvflw;Scope;SignalEditor;SignalRange_and_Lookup_Coverage;SignalSize_Coverage;SubSystem;Sum;Switch;Terminator;Terminator_;Test Condition;Test Objective;all_input

BLOCKTYPE:
Constant;DataTypeConversion;Design Verifier Test Condition;Design Verifier Test Objective;Gain;Logic;Lookup;RateTransition;Scope;SignalEditor;Sum;Switch;Terminator


MODELNAME: mDiscontinuities
PATH: toolbox/qualkits/common/slcov/tests/mcov/mDiscontinuities.slx
DESCRIPTION: Model Coverage test case model for Discontinuites blocks
BLOCKTYPE_FREQUENCY: 2;22;2;208;2;85;10;24;2;2;2;31;27;53;75;72;2;53;257;2
CHECKSUM: B3C9713102AB0C3B5A901487489C4DD4
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Basic Tests for DC Full DC Partial DC - missed hitting lower limit Partial DC - missed hitting upper limit Partial DC - missed hitting either limit  Test Objective: Verify Decision coverage for Dead Zone Block  Partial DC - missed falling slew rate limit on 3rd element Partial DC - missed rising slew rate limit on 3rd element Full DC  Test Objective: Verify Decision coverage for Rate Limiter Block  Partial DC - 2nd element of vector missed DC on both switch points Full DC - Vector with multiple switch points Basic Tests for DC Full DC Partial DC - switch on, never switch off Partial DC - never switch on, switch off  Test Objective: Verify Decision coverage for Relay Block  Basic Tests for DC Full DC Partial DC - missed hitting lower limit Partial DC - missed hitting upper limit Partial DC - missed hitting either limit  Test Objective: Verify Decision coverage for Saturation Block   Note: Blocks with Background color set to orange are present to support coverage of Simulink Library blocks from Discontinuities sub-library. They may receive coverage, however the objective of this test is to show execution coverage of the sub-library blocks. Masked Subsystems, not directly instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage  Note: Blocks with Background color set to orange are present to support coverage of Simulink Library blocks from Discontinuities sub-library. They may receive coverage, however the objective of this test is to show execution coverage of the sub-library blocks.  Test Objective: Verify Execution and Signal Range coverage for blocks under simulink/Discontinuities  Full Coverage Partial Coverage - Missing 1 LSB under Start of dead zone (lower limit) Partial Coverage - Missing equal to Start of dead zone (lower limit) Partial Coverage - Missing 1 LSB over Start of dead zone (lower limit) Partial Coverage - Missing 1 LSB under End of dead zone (upper limit) Partial Coverage - Missing equal to End of dead zone (upper limit) Partial Coverage - Missing 1 LSB over End of dead zone (upper limit)  Test Objective: Verify Relational Boundary coverage for Dead Zone Full Relational Boundary coverage Partial coverage - missing (slew rate - lower limit) = +1 Partial coverage - missing (slew rate - lower limit) = -1 Partial coverage - missing (slew rate - lower limit) = 0 Partial coverage - missing (slew rate - upper limit) = +1 Partial coverage - missing (slew rate - upper limit) = 0  Test Objective: Verify Relational Boundary coverage for Rate Limiter Block  Full Relational Boundary Coverage Partial Coverage - missing (input - on threshold) = -1 Partial Coverage - missing (input - on threshold) = 0 Partial Coverage - missing (input - on threshold) = +1 Partial Coverage - missing (input - off threshold) = -1 Partial Coverage - missing (input - off threshold) = 0 Partial Coverage - missing (input - off threshold) = +1  Test Objective: Verify Relational Boundary coverage for Relay Block  Full Relational Boundary Coverage Partial Coverage - missing (input - lower limit) = -1 Partial Coverage - missing (input - lower limit) = 0 Partial Coverage - missing (input - lower limit) = +1 Partial Coverage - missing (input - upper limit) = -1 Partial Coverage - missing (input - upper limit) = 0 Partial Coverage - missing (input - upper limit) = +1  Test Objective: Verify Relational Boundary coverage for Saturation Block  Overflows upper limit (output = Input - UL) Overflows lower limit (output = Input - LL) Does not overflow (output = Input - UL) Does not overflow (output = Input - LL)  Test Objective: Verify Saturate on Integer Overflow coverage for Dead Zone Copyright 2020 The MathWorks, Inc.

BLOCK:
Backlash;Constant;Coulomb & Viscous Friction;Data Type Conversion;DataTypes;DataTypes_matrix;DataTypes_scalar;DataTypes_vector;Dead Zone;Dead Zone Dynamic;DeadZone_i;DeadZone_single;DeadZone_u;Decision;Enable;Execution and Signal Range;Gain;Hit Crossing;NegativeCase;PositiveCase;PostiveCase;Quantizer;Rate Limiter;Rate Limiter Dynamic;Rate Transition;Reference;Relational Boundary;Relay;Relay_double;Relay_double_vector;Relay_i;Relay_i16_vector;Relay_i32_vector;Relay_i64_vector;Relay_i8_vector;Relay_single;Relay_single_vector;Relay_u;Relay_u16_vector;Relay_u32_vector;Relay_u64_vector;Relay_u8_vector;Repeating Sequence Stair;Saturate on Integer Overflow;Saturation;Saturation Dynamic;Saturation_double;Saturation_i;Saturation_single;Saturation_u;Sine Wave;SubSystem;Terminator;Wrap To Zero

BLOCKTYPE:
Backlash;Constant;Coulombic and Viscous Friction;DataTypeConversion;Dead Zone Dynamic;DeadZone;EnablePort;Gain;HitCross;Quantizer;Rate Limiter Dynamic;RateLimiter;RateTransition;Relay;Repeating Sequence Stair;Saturate;Saturation Dynamic;Sin;Terminator;Wrap To Zero


MODELNAME: mDiscontinuitiesFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mDiscontinuitiesFxp.slx
DESCRIPTION: Model Coverage test case model for Discontinuites blocks
BLOCKTYPE_FREQUENCY: 5;33;13;5;4;4;8;33;8;33
CHECKSUM: A7ED9AB64CB619AEA0F83A1F1AFD4D3F
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Full Coverage Partial Coverage - Missing 1 LSB under Start of dead zone (lower limit) Partial Coverage - Missing equal to Start of dead zone (lower limit) Partial Coverage - Missing 1 LSB over Start of dead zone (lower limit) Partial Coverage - Missing 1 LSB under End of dead zone (upper limit) Partial Coverage - Missing equal to End of dead zone (upper limit) Partial Coverage - Missing 1 LSB over End of dead zone (upper limit)  Test Objective: Verify Relational Boundary coverage for Dead Zone Full Relational Boundary coverage Partial coverage - missing (slew rate - lower limit) = +LSB Partial coverage - missing (slew rate - lower limit) = -LSB  Test Objective: Verify Relational Boundary coverage for Rate Limiter Block  Full Relational Boundary Coverage Partial Coverage - missing (input - on threshold) = -LSB Partial Coverage - missing (input - on threshold) = 0 Partial Coverage - missing (input - on threshold) = +LSB Partial Coverage - missing (input - off threshold) = -LSB Partial Coverage - missing (input - off threshold) = 0 Partial Coverage - missing (input - off threshold) = +LSB  Test Objective: Verify Relational Boundary coverage for Relay Block  Full Relational Boundary Coverage Partial Coverage - missing (input - lower limit) = -LSB Partial Coverage - missing (input - lower limit) = 0 Partial Coverage - missing (input - lower limit) = +LSB Partial Coverage - missing (input - upper limit) = -LSB Partial Coverage - missing (input - upper limit) = 0 Partial Coverage - missing (input - upper limit) = +LSB  Test Objective: Verify Relational Boundary coverage for Saturation Block  Overflows upper limit (output = Input - UL) Overflows lower limit (output = Input - LL) Does not overflow (output = Input - UL) Does not overflow (output = Input - LL)  Test Objective: Verify Saturate on Integer Overflow coverage for Dead Zone Copyright 2020 The MathWorks, Inc.

BLOCK:
Constant;Data Type Conversion;Dead Zone;Enable;NegativeCase;PositiveCase;PostiveCase;Rate Limiter;Rate Transition;Reference;Relational Boundary;Relay;Repeating Sequence Stair;Saturate on Integer Overflow;Saturation;SubSystem;Terminator

BLOCKTYPE:
Constant;DataTypeConversion;DeadZone;EnablePort;RateLimiter;RateTransition;Relay;Repeating Sequence Stair;Saturate;Terminator


MODELNAME: mDiscrete
PATH: toolbox/qualkits/common/slcov/tests/mcov/mDiscrete.slx
DESCRIPTION: Model Coverage test case model for Discrete Library blocks
BLOCKTYPE_FREQUENCY: 35;44;62;2;2;31;29;11;2;15;2;13;2;2;8;2;2;4;4;71;136;14;2;182;4;6;2
CHECKSUM: 4E026F36AC1DBCE974E8067CC9C7E1A3
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Partial DC Note: Discrete FIR Filter blocks get Decision coverage when external reset option is enabled. Full DC Full DC Note: Discrete Filter blocks get Decision coverage when external reset option is enabled. Partial DC Partial DC Note: Discrete Transfer Fcn blocks get Decision coverage when external reset option is enabled. Full DC Full DC Partial DC, missing lower limit Partial DC, missing upper limit Note: Discrete-Time Integrator blocks get Decision coverage when saturation limits are enabled or reset. Partial DC, missing upper limit Partial DC, missing lower limit Full DC Note: Discrete-Time Integrator blocks get Decision coverage when saturation limits are enabled or reset. Basic Tests for DC Full DC Partial DC - always enabled Partial DC - never enabled  Test Objective: Verify Decision coverage for Enabled Delay Block  Full DC Note: Resetable Delay blocks get Decision coverage when either the enable or external reset option is enabled. Partial DC Full DC Note: Variable Integer Delay blocks get Decision coverage when either the enable or external reset option is enabled. Partial DC  Test Objective: Verify Decision coverage for blocks under simulink/Discrete   Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Not instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage Not instrumented for Execution coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution coverage for all blocks under simulink/Discrete  Output determined by internal rule/same as accumulator -- will never overflow Does overflow (internal data) Does not overflow Does overflow Does not overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete FIR Filter Output determined by internal rule -- will never overflow Does not overflow Does not overflow Does overflow Internal Rules  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete Filter Not directly instrumented for Saturation on Integer Overflow Not directly instrumented for Saturation on Integer Overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete PID Controller Not directly instrumented for Saturation on Integer Overflow Not directly instrumented for Saturation on Integer Overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete Transfer Fcn Output does not exceed int16 limits Output exceeds int8 limits  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete-Time Integrator Copyright 2020-2021 The MathWorks, Inc.

BLOCK:
Constant;Data Type Conversion;DataTypes_scalar;DataTypes_vector;Decision;Delay;Difference;Discrete Derivative;Discrete FIR Filter;Discrete Filter;Discrete Filter_cast_narrow;Discrete Filter_cast_wide;Discrete Filter_den_acc;Discrete Filter_den_prod;Discrete Filter_int16_matrix;Discrete Filter_int16_scalar;Discrete Filter_int16_vector;Discrete Filter_int8_matrix;Discrete Filter_int8_scalar;Discrete Filter_int8_vector;Discrete Filter_internalrule;Discrete Filter_num_acc;Discrete Filter_num_prod;Discrete Filter_single_scalar;Discrete PID Controller;Discrete PID Controller (2DOF);Discrete State-Space;Discrete Transfer Fcn;Discrete Zero-Pole;Discrete-Time Integrator;Discrete_FIR_Filter_double;Discrete_FIR_Filter_int16_matrix;Discrete_FIR_Filter_int16_scalar;Discrete_FIR_Filter_int16_vector;Discrete_FIR_Filter_int8_accumulator;Discrete_FIR_Filter_int8_cast_narrow;Discrete_FIR_Filter_int8_cast_wide;Discrete_FIR_Filter_int8_internalrule;Discrete_FIR_Filter_int8_matrix;Discrete_FIR_Filter_int8_productOutput;Discrete_FIR_Filter_int8_scalar;Discrete_FIR_Filter_int8_vector;Discrete_FIR_Filter_single;Enable;Enabled Delay;EnabledDelay_i16_scalar;EnabledDelay_i16_vector;EnabledDelay_i32_scalar;EnabledDelay_i32_vector;EnabledDelay_i64_scalar;EnabledDelay_i64_vector;EnabledDelay_i8_scalar;EnabledDelay_i8_vector;EnabledDelay_single_scalar;EnabledDelay_single_vector;EnabledDelay_u16_scalar;EnabledDelay_u16_vector;EnabledDelay_u32_scalar;EnabledDelay_u32_vector;EnabledDelay_u64_scalar;EnabledDelay_u64_vector;EnabledDelay_u8_scalar;EnabledDelay_u8_vector;Execution and Signal Range;First-Order Hold;Gain;Memory;NegativeCase;PositiveCase;PostiveCase;Reference;Repeating Sequence Stair;Resettable Delay;Saturate on Integer Overflow;Sine Wave;Step;SubSystem;Tapped Delay;Terminator;Transfer Fcn First Order;Transfer Fcn Lead or Lag;Transfer Fcn Real Zero;Unit Delay;Variable Integer Delay;Zero-Order Hold

BLOCKTYPE:
Constant;DataTypeConversion;Delay;Difference;Discrete Derivative;DiscreteFilter;DiscreteFir;DiscreteIntegrator;DiscreteStateSpace;DiscreteTransferFcn;DiscreteZeroPole;EnablePort;First Order Transfer Fcn;First-Order Hold;Gain;Lead or Lag Compensator;Memory;PID 1dof;PID 2dof;Repeating Sequence Stair;Sin;Step;Tapped Delay Line;Terminator;Transfer Fcn Real Zero;UnitDelay;ZeroOrderHold


MODELNAME: mDiscreteFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mDiscreteFxp.slx
DESCRIPTION: Model Coverage test case model for Discrete Library blocks
BLOCKTYPE_FREQUENCY: 3;22;14;12;3;3;8;2;4;29
CHECKSUM: 2AF2FE35E1A6D15349C0D8CBC4D9BBC1
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Output determined by internal rule/same as accumulator -- will never overflow Does overflow (internal data) Does not overflow Does overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete FIR Filter Output determined by internal rule -- will never overflow Does not overflow Does overflow Internal Rules  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete Filter Output does not exceed int16 limits Output exceeds 8-bit fixed-point limits  Test Objective: Verify Saturate on Integer Overflow coverage for Discrete-Time Integrator Copyright 2020 The MathWorks, Inc.

BLOCK:
Constant;Data Type Conversion;Discrete FIR Filter;Discrete Filter;Discrete Filter_cast_narrow;Discrete Filter_cast_wide;Discrete Filter_den_acc;Discrete Filter_den_prod;Discrete Filter_internalrule;Discrete Filter_num_acc;Discrete Filter_num_prod;Discrete Filter_sfix16_matrix;Discrete Filter_sfix16_scalar;Discrete Filter_sfix16_vector;Discrete Filter_sfix8_matrix;Discrete Filter_sfix8_scalar;Discrete Filter_sfix8_vector;Discrete-Time Integrator;Discrete_FIR_Filter_cast_narrow;Discrete_FIR_Filter_cast_wide;Discrete_FIR_Filter_int8_accumulator;Discrete_FIR_Filter_internalrule;Discrete_FIR_Filter_scalar;Discrete_FIR_Filter_sfix16_matrix;Discrete_FIR_Filter_sfix16_scalar;Discrete_FIR_Filter_sfix16_vector;Discrete_FIR_Filter_sfix8_matrix;Discrete_FIR_Filter_sfix8_productOutput;Discrete_FIR_Filter_sfix8_vector;Discrete_FIR_Filter_sfix_scalar;Enable;Gain;NegativeCase;PositiveCase;Saturate on Integer Overflow;Sine Wave;Step;SubSystem;Terminator

BLOCKTYPE:
Constant;DataTypeConversion;DiscreteFilter;DiscreteFir;DiscreteIntegrator;EnablePort;Gain;Sin;Step;Terminator


MODELNAME: mDiscreteSignalSize
PATH: toolbox/qualkits/common/slcov/tests/mcov/mDiscreteSignalSize.slx
BLOCKTYPE: Constant;DataTypeConversion;Delay;EnablePort;From;Goto;Inport;Sin;Step;Switch;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 16;50;43;5;20;2;5;2;3;2;54;11
CHECKSUM: EF6AEFEEBB2C9904F961C154B022ECB5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Note: Signal Size coverage is only captured when variable-sized signals are used.  Test Objective: Verify Signal Size coverage for Delay, Enabled Delay, Resettable Delay, and Variable Integer Delay blocks  Note: Signal Size coverage is only captured when variable-sized signals are used.  Test Objective: Verify Signal Size coverage for Discrete FIR Filter Copyright 2020-2021 The MathWorks, Inc.  Test Objective: Verify Signal Size coverage for blocks under simulink/Discrete that support variable-size signals. 

BLOCK:
Constant;Data Type Conversion;Delay;DelayBlock;Delay_double;Delay_i;Delay_single;Delay_u;Enable;Enabled Delay;EnabledDelay;EnabledDelay_double;EnabledDelay_i;EnabledDelay_single;EnabledDelay_u;From;Goto;In;NegativeCase;PositiveCase;Resettable Delay;ResettableDelay;ResettableDelay_double;ResettableDelay_i;ResettableDelay_single;ResettableDelay_u;Signal Size;Sine Wave;Step;SubSystem;Switch;Terminator;Unit Delay;UnitDelay_double;UnitDelay_i;UnitDelay_single;UnitDelay_u;Variable Integer Delay;VariableIntegerDelay;VariableIntegerDelay_double;VariableIntegerDelay_i;VariableIntegerDelay_single;VariableIntegerDelay_u;datatypes


MODELNAME: mDiscreteSignalSizeDsp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mDiscreteSignalSizeDsp.slx
BLOCKTYPE: Constant;DataTypeConversion;DiscreteFir;Step;Switch;Terminator
BLOCKTYPE_FREQUENCY: 2;11;11;2;1;11
CHECKSUM: C381E1FE5B390A362B11907AB69F70E5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Note: Signal Size coverage is only captured when variable-sized signals are used.  Note: To support variable-size signals, block parameter Input Processing must be set to Columns as channels (frame based). Frame-based processing requires a DSP System Toolbox license.  Test Objective: Verify Signal Size coverage for Discrete FIR Filter Copyright 2020-2021 The MathWorks, Inc.  Test Objective: Verify Signal Size coverage for blocks under simulink/Discrete that support variable-size signals. DSP System Toolbox license required for this test case 

BLOCK:
Constant;Data Type Conversion;Discrete FIR Filter;Discrete_FIR_Filter_SS_double;Discrete_FIR_Filter_SS_int;Discrete_FIR_Filter_SS_single;Discrete_FIR_Filter_SS_uint;NegativeCase;PositiveCase;Signal Size;Step;SubSystem;Switch;Terminator


MODELNAME: mEML_RelCov
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_RelCov.slx
DESCRIPTION: Model Coverage test case model for Relational Boundary coverage in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 3;3;3;3;6
CHECKSUM: DF3BA70B8C29C8EA60EE037C10D19E38
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Relational Boundary coverage in MATLAB code (floating-point) Copyright 2020 The MathWorks, Inc. Verify Relational Boundary coverage in MATLAB code (integer) Verify Relational Boundary coverage in MATLAB code (no coverage)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_float;MATLABFunction_int;MATLABFunction_never;SubSystem;Terminator;out


MODELNAME: mEML_RelCovFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_RelCovFxp.slx
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: F0DF1E517D62B5DFCE93959CA7E65BBC
PRODUCT: Fixed-Point Designer;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
DESCRIPTION:
Model Coverage test case model for Relational Boundary coverage in MATLAB Function code (Fixed-point data)

ANNOTATION:
Copyright 2020 The MathWorks, Inc. Verify Relational Boundary coverage in MATLAB code (fixed-point) Verify Relational Boundary coverage in MATLAB code (mixed data types)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_fixpt;MATLABFunction_mix;SubSystem;Terminator;out


MODELNAME: mEML_RelCovFxp_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_RelCovFxp_Jstfy.slx
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;4;4;4;8
CHECKSUM: B79B129DA2D508AEB97E36A59B1268B5
PRODUCT: Fixed-Point Designer;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
DESCRIPTION:
Model Coverage test case model for Relational Boundary coverage in MATLAB Function code (Fixed-point data)

ANNOTATION:
Copyright 2023 The MathWorks, Inc. Verify Relational Boundary coverage in MATLAB code (fixed-point) Verify Relational Boundary coverage in MATLAB code (mixed data types) Verify Relational Boundary coverage in MATLAB code (fixed-point) Verify Relational Boundary coverage in MATLAB code (mixed data types)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_fixpt;MATLABFunction_fixpt_external;MATLABFunction_mix;MATLABFunction_mix_external;SubSystem;Terminator;out


MODELNAME: mEML_RelCov_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_RelCov_Jstfy.slx
DESCRIPTION: Model Coverage test case model for Relational Boundary coverage in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;4;4;4;8
CHECKSUM: 7FD367B271CBC02A1165650ECA5B4AF9
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Relational Boundary coverage in MATLAB code (floating-point) Copyright 2023 The MathWorks, Inc. Verify Relational Boundary coverage in MATLAB code (integer) Verify Relational Boundary coverage in MATLAB code (floating-point) Verify Relational Boundary coverage in MATLAB code (integer)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_float;MATLABFunction_float_external;MATLABFunction_int;MATLABFunction_int_external;SubSystem;Terminator;out


MODELNAME: mEML_RelCov_SF_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_RelCov_SF_Jstfy.slx
DESCRIPTION: Model Coverage test case model for Relational Boundary coverage in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: E8C4DB16DCE436B27A07604C72539F7C
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2023 The MathWorks, Inc. Verify Relational Boundary coverage in MATLAB code (floating-point) Verify Relational Boundary coverage in MATLAB code (floating-point)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_float;MATLABFunction_float_external;SubSystem;Terminator;out_data


MODELNAME: mEML_TooComplexMcdc
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_TooComplexMcdc.slx
BLOCK: Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_TooComplex;SubSystem;Terminator;out
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;1;1;1;2
CHECKSUM: 47AAB95A84759888EA076484A84F6932
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify warning message thrown when expression is too complex to instrument for MCDC. Copyright 2020 The MathWorks, Inc.


MODELNAME: mEML_assignment
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_assignment.slx
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: 32C864DBBC4FE778EB907C5BBCCEFBD6
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
DESCRIPTION:
Model Coverage test case model for coverage on MATLAB Function logical expressions in assignment statements

ANNOTATION:
Verify Condition coverage and MCDC on assignments in MATLAB Function code (internal)  NOTE: Logical expressions in assignment statements in the MATLAB Function Block that contain &amp;&amp; and || have model coverage conditions. Full condition coverage requires that each condition evaluate to true at least once and evaluate to false at least once. Full MCDC coverage requires that each condition independently changes the expressions value. Logical expressions in assignment statements are only instrumented for condition coverage and MCDC.  Verify Condition coverage and MCDC on assignments in MATLAB Function code (external) Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;Assignment coverage;Assignment coverage (External);SubSystem;Terminator;out


MODELNAME: mEML_assignment_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_assignment_Jstfy.slx
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: EFFA47B573F3907959548D670509FB08
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
DESCRIPTION:
Model Coverage test case model for coverage on MATLAB Function logical expressions in assignment statements

ANNOTATION:
Verify Condition coverage and MCDC on assignments in MATLAB code (external) Copyright 2023 The MathWorks, Inc. Verify Condition coverage and MCDC on assignments in MATLAB code (internal)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;Assignment coverage;Assignment coverage (External);SubSystem;Terminator;out


MODELNAME: mEML_assignment_SF_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_assignment_SF_Jstfy.slx
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: EBE6AC46E18B6993A6DCFBB24E10BFF6
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
DESCRIPTION:
Model Coverage test case model for coverage on MATLAB Function logical expressions in assignment statements

ANNOTATION:
Verify Condition coverage and MCDC on assignments in MATLAB code (external) Copyright 2023 The MathWorks, Inc. Verify Condition coverage and MCDC on assignments in MATLAB code (internal)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;Assignment coverage;Assignment coverage (External);SubSystem;Terminator;out_data


MODELNAME: mEML_for
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_for.slx
DESCRIPTION: Model Coverage test case model for coverage on for loops in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: 59B8025EC694E06D2F020D62308DD0D8
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Note: for — Decision coverage is 100% if the equivalent loop condition evaluates to true at least once, and false at least once. The for statement is only instrumented for decision coverage. Verify Decision coverage on for loop in MATLAB Function code (internal) Verify Decision coverage on for loop in MATLAB Function code (external) Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;For coverage;For coverage (External);SubSystem;Terminator;out


MODELNAME: mEML_for_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_for_Jstfy.slx
DESCRIPTION: Model Coverage test case model for coverage on for loops in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: 3C9F5BEA0B62B7AA75390B3C4D1BA5D2
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Decision coverage on for loop in MATLAB Function code (external) Copyright 2023 The MathWorks, Inc. Verify Decision coverage on for loop in MATLAB Function code (internal)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;For coverage;For coverage (External);SubSystem;Terminator;out


MODELNAME: mEML_function
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_function.slx
DESCRIPTION: Model Coverage test case model for function call coverage in MATLAB Function code
BLOCKTYPE: Constant;Demux;EnablePort;Ground;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;1;1;2;3;2;4
CHECKSUM: 0D080AB0512C961DEE43ED30786654E0
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify decision coverage on MATLAB Function (main and local)  Note: Functions in the MATLAB Function Block have model coverage decisions that indicate if the function was called.  Verify no decision coverage on Function when never called Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;Constant;Enable;Function coverage;In;MATLABFunction_DC;NeverCalled;Out;SubSystem;Terminator;out;u;y


MODELNAME: mEML_function_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_function_Jstfy.slx
DESCRIPTION: Model Coverage test case model for function call coverage in MATLAB Function code
BLOCKTYPE: Constant;Demux;EnablePort;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 8;4;4;8;8;4;8
CHECKSUM: 068C3E8A0CC22C37C558BAFC573B352E
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify no decision coverage on Function Header when function is never called Verify no decision coverage on Function Header when local function is never called Copyright 2023 The MathWorks, Inc. Verify no decision coverage on Function Header when function is never called Verify no decision coverage on Function Header when local function is never called

BLOCK:
 Demux ; SFunction ; Terminator ;Constant;Enable;FuncNotExecuted;FuncNotExecutedExternal;In;LocalFuncNotExecuted;LocalFuncNotExecutedExternal;MATLABFunction_DC;Out;SubSystem;Terminator;out;u;y


MODELNAME: mEML_if
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_if.slx
DESCRIPTION: Model Coverage test case model for coverage on if statements in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 6;6;6;6;12
CHECKSUM: 15F7D30355314E11960360BF8994A9C8
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Note: if — Decision coverage is 100% if the if expression evaluates to true at least once, and false at least once. Verify MCDC for if statement in MATLAB Function code (internal) Verify Decision coverage for if statement in MATLAB Function code (internal) Verify Decision coverage for if statement in MATLAB Function code (external) Verify Condition coverage for if statement in MATLAB Function code (internal) Verify Condition coverage for if statement in MATLAB Function code (external) Verify MCDC for if statement in MATLAB Function code (external) Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_CC;MATLABFunction_CC_Ext;MATLABFunction_DC;MATLABFunction_DC_Ext;MATLABFunction_MCDC;MATLABFunction_MCDC_Ext;SubSystem;Terminator;out;y


MODELNAME: mEML_if_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_if_Jstfy.slx
DESCRIPTION: Model Coverage test case model for coverage on if statements in MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 6;6;6;6;12
CHECKSUM: 390CB3C93FDC50FE31EFEF697B073022
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Decision coverage for if statement in MATLAB Function code (external) Verify Condition coverage for if statement in MATLAB Function code (external) Verify MCDC for if statement in MATLAB Function code (external) Copyright 2023 The MathWorks, Inc. Verify MCDC for if statement in MATLAB Function code (internal) Verify Condition coverage for if statement in MATLAB Function code (internal) Verify Decision coverage for if statement in MATLAB Function code (internal)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_CC;MATLABFunction_CC_Ext;MATLABFunction_DC;MATLABFunction_DC_Ext;MATLABFunction_MCDC;MATLABFunction_MCDC_Ext;SubSystem;Terminator;out;y


MODELNAME: mEML_saturate
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_saturate.slx
DESCRIPTION: Model Coverage test case model for Saturate on Integer Overflow for MATLAB Function code
BLOCK: Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_tc;SubSystem;Terminator;i;u
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 4;4;24;4;28
CHECKSUM: 6DF91A5D15CE8065298909F23C74BA3D
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Saturate on Integer Overflow Coverage metric for MATLAB Function code Copyright 2022 The MathWorks, Inc.


MODELNAME: mEML_saturate_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_saturate_Jstfy.slx
DESCRIPTION: Model Coverage test case model for Saturate on Integer Overflow for MATLAB Function code
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;16;2;18
CHECKSUM: 457B766EB95791946B38E4A94313BC33
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;For Coverage;For coverage (external);SubSystem;Terminator;i;u


MODELNAME: mEML_saturate_SF_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_saturate_SF_Jstfy.slx
DESCRIPTION: Model Coverage test case model for Saturate on Integer Overflow for MATLAB Function code
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;16;2;18
CHECKSUM: 430A5AC8077BACFA39FF7CCABE3EEF61
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;For coverage ;For coverage (external);SubSystem;Terminator;out_data


MODELNAME: mEML_sldv
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_sldv.slx
DESCRIPTION: Model Coverage test case model for Simulink Design Verifier coverage for MATLAB Function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: 191B80DBE790903725DE9578CD6D85D9
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify missing Simulink Design Verifier coverage for MATLAB code  Note: Simulink Design Verifier coverage measures the number of time steps that the expression expr evaluates to true. If expr is true for at least one time step, Simulink Design Verifier coverage for that function is 100%. Otherwise, the Simulink Coverage software reports coverage for that function as 0%. Verify Simulink Design Verifier coverage for MATLAB Function code Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;MATLABFunction_SLDV_neg;MATLABFunction_SLDV_pos;SubSystem;Terminator;out


MODELNAME: mEML_switch
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_switch.slx
DESCRIPTION: Model Coverage test case model for switch-case statements in MATLAB function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: E11053A9870687556107A763B816D740
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Decision coverage for switch statement in MATLAB Function code (internal) Verify Decision coverage for switch statement in MATLAB Function code (external) Copyright 2020 The MathWorks, Inc.  Note: switch-case constructs in the MATLAB Function Block have model coverage decisions that indicate which case statements have executed. Full coverage requires that each case statement (and the otherwise case) be taken at least once. Even if the otherwise is not written there must still be an execution where no case statement is taken to achieve full coverage.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;SubSystem;Switch-case coverage;Switch-case coverage (external);Terminator;out


MODELNAME: mEML_switch_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_switch_Jstfy.slx
DESCRIPTION: Model Coverage test case model for switch-case statements in MATLAB function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: 940E26FAB06A1D69AF4CDCE917E0131A
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Decision coverage for switch statement in MATLAB function code Copyright 2023 The MathWorks, Inc. Verify Decision coverage for switch statement in MATLAB function code

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;SubSystem;Switch-case coverage;Switch-case coverage (external);Terminator;out


MODELNAME: mEML_switch_SF_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_switch_SF_Jstfy.slx
DESCRIPTION: Model Coverage test case model for switch-case statements in MATLAB function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: E7EC4A8E116081E66C8A37A344D3ABA9
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2023 The MathWorks, Inc. Verify Decision coverage for switch statement in MATLAB Function in Stateflow Verify Decision coverage for switch statement in MATLAB Function in Stateflow

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;SubSystem;Switch-case EML coverage;Switch-case EML coverage (external);Terminator;out_data


MODELNAME: mEML_while
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_while.slx
DESCRIPTION: Model Coverage test case model for while loops in MATLAB function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: D7801AB9CDEFDED266147EA95EFA3C06
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Note: while — Decision coverage is 100% if the equivalent loop condition evaluates to true at least once, and evaluates to false at least once. The while statement is only instrumented for decision coverage. Verify Decision Coverage (DC) for a while statement in a MATLAB Function block (Internal) Verify Decision Coverage (DC) for a while statement in a MATLAB Function block (external) Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;SubSystem;Terminator;While coverage (external);While coverage (internal);out


MODELNAME: mEML_while_Jstfy
PATH: toolbox/qualkits/common/slcov/tests/mcov/mEML_while_Jstfy.slx
DESCRIPTION: Model Coverage test case model for while loops in MATLAB function code
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;2;2;2;4
CHECKSUM: 875A322A45265068C909366A61BE02C5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Verify Decision Coverage (DC) for a while statement in a MATLAB Function block (external) Copyright 2023 The MathWorks, Inc. Verify Decision Coverage (DC) for a while statement in a MATLAB Function block (Internal)

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;SubSystem;Terminator;While coverage (external);While coverage (internal);out


MODELNAME: mFcnCallerCov
PATH: toolbox/qualkits/common/slcov/tests/mcov/mFcnCallerCov.slx
ANNOTATION: Copyright 2022-2024 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;3;3;3;3;1;1;2;3;1;3;1;3
CHECKSUM: 5DC67D88739A2DA85734805FB4D11DFC
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
Action Port;Add;Constant;Ground;If;If Action Subsystem;In;Out;Output;Product;SubSystem;To Workspace;callWhenFalse;callWhenTrue;doubleMe;doubleMeFnc;groundCall;squareMe;squareMeFcn;u;x;zeroMe;zeroMeFnc

BLOCKTYPE:
ActionPort;ArgIn;ArgOut;Constant;FunctionCaller;Ground;If;Inport;Outport;Product;Sum;ToWorkspace;TriggerPort


MODELNAME: mLogicBitOperations
PATH: toolbox/qualkits/common/slcov/tests/mcov/mLogicBitOperations.slx
DESCRIPTION: Model Coverage test case model for Logic and Bit Operations
BLOCKTYPE_FREQUENCY: 2;2;2;2;3;18;11;2;2;19;116;179;2;2;2;2;2;2;2;5;9;1;2;16;2;2;23;2;2;92;36;287;135;16;24;8;4;394
CHECKSUM: 9E77B3C5F4ED9BC2E70E01ACDF7CAB7B
PRODUCT: IEC Certification Kit;MATLAB;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Full Condition Coverage Partial Condition Coverage - 2nd input always zero Full Condition Coverage (double input) Partial Condition Coverage - 3rd input always one (double input)  Test Objective: Verify Condition coverage for Combinatorial Logic Block   Test Objective: Verify Condition coverage for Logical Operator Block  Mix double and uint32 Mix scalar and vector Full Condition Coverage (One-Input Mode) Full Condition Coverage (Two-Input Mode) Partial Condition Coverage (Two-Input Mode) Partial Condition Coverage (One-Input Mode)  Test Objective: Verify Condition coverage for Relational Operator Block  Always true Always false Full DC Basic Tests for DC  Test Objective: Verify Decision coverage for Combinatorial Logic Block   Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Masked Subsystems, not directly instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution and Signal Range coverage for all blocks under simulink/Logic and Bit Operations  Partial MCDC with 10 inputs Full MCDC with 10 inputs  Test Objective: Verify MCDC for Logical Operator Block  Partial Relational Boundary Coverage (missing input1 - input2 = 0..tol) Partial Relational Boundary Coverage (missing input1 - input2 = -tol..0) Full Relational Boundary Coverage Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = -1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = -1) Full Relational Boundary Coverage Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = -1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = -tol..0) Partial Relational Boundary Coverage (missing input1 - input2 = 0..tol) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = -1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = -1) Full Relational Boundary Coverage Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = -1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Partial Relational Boundary Coverage (missing input1 - input2 = +1) Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = -1) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = -1) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = +1)  Test Objective: Verify Relational Boundary coverage for Relational Operator Block   Test Objective: Verify Signal Size coverage for Logical Operator Block   Test Objective: Verify Signal Size coverage for Relational Operator Block  Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
! A || B;!( !A && !B && !C );!( A && !B);A && !B;A && B && C;A || B || C;AND;AND_;B && !C;Bit Clear;Bit Set;Bitwise Operator;Bus Creator;Bus Selector;Cascaded;Combinatorial Logic;Compare To Constant;Compare To Zero;Condition;Constant;Data Type Conversion;DataTypes_matrix;DataTypes_scalar;DataTypes_vector;Decision;Detect Change;Detect Decrease;Detect Fall Negative;Detect Fall Nonpositive;Detect Increase;Detect Rise Nonnegative;Detect Rise Positive;Enable;Enumerated Constant;Execution and Signal Range;Extract Bits;FC_Operator_AND;FC_Operator_NAND;FC_Operator_NOR;FC_Operator_NXOR;FC_Operator_OR;FC_Operator_XOR;From;Full MCDC;Full MCDC treating as short-circuited;FullCoverage_AND;FullCoverage_NAND;FullCoverage_NOR;FullCoverage_NOT;FullCoverage_NXOR;FullCoverage_OR;FullCoverage_XOR;Gain;Goto;In;Input;Interval Test;Interval Test Dynamic;Logical Operator;MCDC;ManyInputs;Mix;NAND;NAND( A, !B);NOR;NOR( !B, C);NOT;NOT_;NegativeCase;OR;OR_;Out;PC_Operator_AND;PC_Operator_NAND;PC_Operator_NOR;PC_Operator_NXOR;PC_Operator_OR;PC_Operator_XOR;Partial MCDC;PartialCoverage_AND;PartialCoverage_NAND;PartialCoverage_NOR;PartialCoverage_NOT;PartialCoverage_NXOR;PartialCoverage_OR;PartialCoverage_XOR;PositiveCase;PostiveCase;Pulse Generator;Reference;RelOpEQ;RelOpGE;RelOpGT;RelOpLE;RelOpLT;RelOpNE;Relational Boundary;Relational Operator;Repeating Sequence Stair;SE_G;Scalar;Shift Arithmetic;Signal Editor;Signal Size;Sine Wave;Step;SubSystem;Switch;Terminator;Vector;Vector Concatenate;double;int;single;uint

BLOCKTYPE:
ArithShift;Bit Clear;Bit Set;Bitwise Operator;BusCreator;BusSelector;CombinatorialLogic;Compare To Constant;Compare To Zero;Concatenate;Constant;DataTypeConversion;Detect Change;Detect Decrease;Detect Fall Negative;Detect Fall Nonpositive;Detect Increase;Detect Rise Nonnegative;Detect Rise Positive;DiscretePulseGenerator;EnablePort;Enumerated Constant;Extract Bits;From;Gain;Goto;Inport;Interval Test;Interval Test Dynamic;Logic;Outport;RelationalOperator;Repeating Sequence Stair;SignalEditor;Sin;Step;Switch;Terminator


MODELNAME: mLogicBitOperationsFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mLogicBitOperationsFxp.slx
DESCRIPTION: Model Coverage test case model for Logic and Bit Operations
BLOCKTYPE: Constant;DataTypeConversion;EnablePort;RelationalOperator;Repeating Sequence Stair;Terminator
BLOCKTYPE_FREQUENCY: 6;10;1;25;5;25
CHECKSUM: 9F4F90F41F767F4BA838AC2582106FBB
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Partial Relational Boundary Coverage (missing input1 - input2 = -LSB) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing input1 - input2 = 0) Partial Relational Boundary Coverage (missing input1 - input2 = +LSB)  Test Objective: Verify Relational Boundary coverage for Relational Operator Block  Copyright 2020 The MathWorks, Inc.

BLOCK:
Constant;Data Type Conversion;Enable;NegativeCase;PositiveCase;Reference;RelOpEQ;RelOpGE;RelOpGT;RelOpLE;RelOpLT;RelOpNE;Relational Boundary;Relational Operator;Repeating Sequence Stair;SubSystem;Terminator


MODELNAME: mLookupTables
PATH: toolbox/qualkits/common/slcov/tests/mcov/mLookupTables.slx
DESCRIPTION: Model Coverage test case model for Lookup Table blocks
BLOCKTYPE_FREQUENCY: 40;38;1;9;8;1;3;6;17;2;18;12;27;5;1;5;1;22;28;1;2;29;7;7;82
CHECKSUM: F5C54DF9B708BA08F814767FB17FE3A1
PRODUCT: IEC Certification Kit;MATLAB;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution and Signal Range coverage for all blocks under simulink/Lookup Tables  1D Table, scalar input 1D Table, Discontiguous Input 2D Tables 2D Table, Contiguous Input ND Tables Column Select  Test Objective: Verify Lookup Table coverage for Direct Lookup Tables  Scalar All < brk[0] Scalar All > brk[max] Scalar Full Coverage, No Equality Scalar All Equality Pts Vector Contiguous Vector Discontiguous  Test Objective: Verify Lookup Table coverage for legacy 1D Lookup Tables  Scalar Full Y Coverage Scalar Full Coverage, no break point equality Scalar 4 corners Scalar all break point equality Scalar Full X Coverage Vector Contiguous Vector Discontiguous  Test Objective: Verify Lookup Table coverage for legacy 2D Lookup Tables  Testcase 35 - datatypes: int - intsize: 8 - signbit: unsigned - datashapes: matrix - matrixshapes: 2-D - scenarios: untriggered - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: noreuse - search: binary - interps: nointerp - extraps: noextrap - noextrap_clip: uselast Testcase 18 - datatypes: int - intsize: 8 - signbit: unsigned - datashapes: scalar - scenarios: untriggered - inputs: one input scalar - oneinputopt: nooneinput - reuseopt: noreuse - search: even - interps: cubicint - extraps: noextrap - noextrap_clip: nouselast Testcase 29 - datatypes: float - floattypes: double - datashapes: scalar - scenarios: partial - partialset: only breakpts - inputs: normal inputs - oneinputopt: oneinput - reuseopt: reuseindex - search: lin - interps: cubicint - extraps: cubicex - noextrap_clip: nouselast Testcase 17 - datatypes: int - intsize: 16 - signbit: unsigned - datashapes: vector - scenarios: partial - partialset: only breakpts - inputs: table type mismatch - oneinputopt: nooneinput - reuseopt: noreuse - search: binary - interps: nointerp - extraps: noextrap - noextrap_clip: uselast Testcase 6 - datatypes: int - intsize: 32 - signbit: unsigned - datashapes: scalar - scenarios: partial - partialset: no breakpts - inputs: normal inputs - oneinputopt: oneinput - reuseopt: reuseindex - search: binary - interps: linint - extraps: noextrap - noextrap_clip: uselast Testcase 27 - datatypes: float - floattypes: single - datashapes: matrix - matrixshapes: 1-D - scenarios: partial - partialset: no breakpts - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: noreuse - search: even - interps: linint - extraps: linex - noextrap_clip: nouselast Testcase 9 - datatypes: int - intsize: 8 - signbit: signed - datashapes: scalar - scenarios: full - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: noreuse - search: even - interps: linint - extraps: noextrap - noextrap_clip: nouselast Testcase 36 - datatypes: int - intsize: 32 - signbit: signed - datashapes: matrix - matrixshapes: 1-D - scenarios: full - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: noreuse - search: lin - interps: nointerp - extraps: noextrap - noextrap_clip: nouselast Testcase 34 - datatypes: float - floattypes: double - datashapes: scalar - scenarios: partial - partialset: only breakpts - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: reuseindex - search: lin - interps: cubicing - extraps: cubicex - noextrap_clip: nouselast Testcase 14 - datatypes: int - intsize: 32 - signbit: signed - datashapes: matrix - matrixshapes: 2-D - scenarios: full - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: reuseindex - search: lin - interps: nointerp - extraps: noextrap - noextrap_clip: nouselast Testcase 28 - datatypes: int - intsize: 8 - signbit: signed - datashapes: matrix - matrixshapes: 1-D - scenarios: full - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: noreuse - search: even - interps: linint - extraps: noextrap - noextrap_clip: uselast Testcase 21 - datatypes: float - floattypes: single - datashapes: matrix - matrixshapes: 2-D - scenarios: partial - partialset: ints and breakpts - inputs: one input scalar - oneinputopt: nooneinput - reuseopt: noreuse - search: lin - interps: linint - extraps: linex - noextrap_clip: nouselast Testcase 1 - datatypes: int - intsize: 32 - signbit: unsigned - datashapes: scalar - scenarios: partial - partialset: only breakpts - inputs: normal inputs - oneinputopt: oneinput - reuseopt: reuseindex - search: binary - interps: linint - extraps: noextrap - noextrap_clip: nouselast Testcase 30 - datatypes: int - intsize: 16 - signbit: unsigned - datashapes: scalar - scenarios: partial - partialset: ints and breakpts - inputs: normal inputs - oneinputopt: nooneinput - reuseopt: noreuse - search: binary - interps: linint - extraps: noextrap - noextrap_clip: nouselast Testcase 37 - datatypes: int - intsize: 32 - signbit: signed - datashapes: scalar - scenarios: full - inputs: table type mismatch - oneinputopt: nooneinput - reuseopt: noreuse - search: lin - interps: nointerp - extraps: noextrap - noextrap_clip: nouselast Testcase 8 - datatypes: int - intsize: 16 - signbit: signed - datashapes: matrix - matrixshapes: 2-D - scenarios: partial - partialset: no breakpts - inputs: one input scalar - oneinputopt: nooneinput - reuseopt: reuseindex - search: lin - interps: nointerp - extraps: noextrap - noextrap_clip: uselast  Test Objective: Verify Lookup Table coverage for Lookup Table (n-D) cannot extrapolate on integer input, so cannot saturate. note: you cannot extrapolate non-floats, and floats dont overflow. so no overflowing.  Test Objective: Verify Saturate on Integer Overflow coverage for Interpolation Using Prelookup  Legacy 1D Lookup Table (Obsolete as of R2011a) cast narrower cast wider  Test Objective: Verify Saturate on Integer Overflow coverage for legacy 1D Lookup Tables  Legacy 2D Lookup Table (Obsolete as of R2011a) vector, scalar exp on first input scalar matrix, scalar exp on second input  Test Objective: Verify Saturate on Integer Overflow coverage for legacy 2D Lookup Tables  note: cannot extrapolate non-float, cannot saturate without extrapolating  Test Objective: Verify Saturate on Integer Overflow coverage ND Lookup Tables  Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;1-D Lookup Table;1D;2-D Lookup Table;2D;Add;At;At Break Values;At Fast;Between ;Between Break values;Between Fast;Constant;Data Type Conversion;Direct Lookup Table (n-D);Enable;Execution and Signal Range;Extremes;Extremes Fast;FullCoverage;FullCoverage_int;FullCoverage_uint;Gain;Interpolation Using Prelookup;LU;Legacy Lookup;Legacy Lookup2D ;LegacyLookup1D;LegacyLookup2D;Lookup;Lookup Table;Lookup Table Dynamic;Lookup2D;LookupND;MATLAB Function;Mux;ND;NegativeCase;NoCoverage_SIO_off;NoOverflow_CastWider;NoOverflow_boolean;NoOverflow_matrix;NoOverflow_single;Overflow_CastNarrower;PartialCoverage;PositiveCase;PostiveCase;Prelookup;Ramp;Reference;Repeating Sequence Stair;Saturation on Integer Overflow;Scalar;Scalars;Signal Builder;Signal Editor;Sine Wave;Step;SubSystem;Sum;Table;Table_;Table_1d;Table_2d;Table_col;Table_nd;Terminator;Terminator_;Testcase ;Vector;Vectors;double;float;int;integer;interp;make_matrix;make_vector;n-D Lookup Table;off;on;single;size-type;y

BLOCKTYPE:
Constant;DataTypeConversion;Demux;EnablePort;Gain;Ground;Inport;Interpolation_n-D;Lookup;Lookup Table Dynamic;Lookup2D;LookupNDDirect;Lookup_n-D;Mux;Outport;PreLookup;Ramp;Repeating Sequence Stair;Repeating table;S-Function;SignalEditor;Sin;Step;Sum;Terminator


MODELNAME: mLookupTablesFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mLookupTablesFxp.slx
DESCRIPTION: Model Coverage test case model for Lookup Table blocks
BLOCKTYPE_FREQUENCY: 7;16;4;1;5;5;2;8;4;4;16
CHECKSUM: 5BE92E23044A35C5F24FA02622AFA423
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Masked Subsystems, not directly instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage  Test Objective: Verify Execution and Signal Range coverage for all blocks under simulink/Lookup Tables  Legacy 1D Lookup Table (Obsolete as of R2011a) cast narrower cast wider  Test Objective: Verify Saturate on Integer Overflow coverage for legacy 1D Lookup Tables  Legacy 2D Lookup Table (Obsolete as of R2011a) vector, scalar exp on first input scalar  Test Objective: Verify Saturate on Integer Overflow coverage for legacy 2D Lookup Tables   Test Objective: Verify Saturate on Integer Overflow coverage ND Lookup Tables  Copyright 2020-2021 The MathWorks, Inc.

BLOCK:
2-D Lookup Table;Constant;Cosine;Data Type Conversion;Enable;Execution and Signal Range;FullCoverage_sfix;FullCoverage_ufix;LegacyLookup1D;LegacyLookup2D;Lookup;Lookup2D;LookupND;NegativeCase;NoOverflow_CastWider;Overflow_CastNarrower;PositiveCase;PostiveCase;Reference;Saturation on Integer Overflow;Sine;Sine Wave;Step;SubSystem;Terminator;Terminator_;make_vector

BLOCKTYPE:
Constant;DataTypeConversion;EnablePort;Gain;Lookup;Lookup2D;Lookup_n-D;Sin;Sine and Cosine;Step;Terminator


MODELNAME: mMathOperations
PATH: toolbox/qualkits/common/slcov/tests/mcov/mMathOperations.slx
DESCRIPTION: Model Coverage test case model for Math Operations
CHECKSUM: F34C1510234F369E1DA20918508B9561
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Vectors and Matrices Scalars Abs blocks with unsigned input data types are not instrumented Vectors and Matrices Scalars  Test Objective: Verify Decision coverage for Abs block   Test Objective: Verify Decision coverage for MinMax block  Vectors and Matrices Scalars Vectors and Matrices Scalars  Test Objective: Verify Decision coverage for Sign block  Verify only execution coverage when RemoveProtectionAgainstOutOfRangeInput is On  Scalars Vectors and Matrices Verify only execution coverage when RemoveProtectionAgainstOutOfRangeInput is On  Scalars Vectors and Matrices  Test Objective: Verify decision coverage for Trigonometric Function block Note: Only asin and acos functions get decision coverage  Concatenate block duplicated in Signal Routing and Math Operations  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. z2 z1 z1 z2 z2 z1 z2-z1-1 Sum1 Sum Not instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage Not instrumented for Execution coverage Sum Sum1 z2-z1-1 z1 z2 z2 z1 z1 z2  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Concatenate block duplicated in Signal Routing and Math Operations  Test Objective: Verify Execution Signal Range coverage for all blocks under simulink/Math Operations   Test Objective: Verify Relational Boundary coverage for Abs block   Test Objective: Verify Relational Boundary coverage for Sign block   Note: To see partial Relational Boundary coverage for Trignometric block, see mMathOperations/Decision/Trigonometric Function/PositiveCase  Test Objective: Verify Relational Boundary coverage for Trigonometric Function block  Scalars Vectors and Matrices Vectors and Matrices Scalars  Test Objective: Verify Saturate on Integer Overflow coverage for Abs block   Test Objective: Verify Saturate on Integer Overflow coverage for Bias block  Does not overflow  Cast narrow  Cast wider  Test Objective: Verify Saturate on Integer Overflow coverage for Dot Product block  Does not overflow  Cast narrow  Test Objective: Verify Saturate on Integer Overflow coverage for Gain block  Does not overflow  Note: Saturate on integer overflow parameter is enabled for the Math Function block when the Function is set to magnitude^2, square, conj, reciprocal, or hermitian.  Test Objective: Verify Saturate on Integer Overflow coverage for Math Function block   Test Objective: Verify Saturate on Integer Overflow coverage for MinMax block   Cast narrow Does not overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Product block   Cast narrow Internal Data  Cast narrow Internal rule  Cast wider  Test Objective: Verify Saturate on Integer Overflow coverage for Sqrt block  accumulator saturates  Test Objective: Verify Saturate on Integer Overflow coverage for Sum block   Test Objective: Verify Saturate on Integer Overflow coverage for Unary Minus block  Does not overflow Does not overflow Does not overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Weighted Sample Time Math block   Test Objective: Verify Signal Size coverage for Abs block   Test Objective: Verify Signal Size coverage for Assignment block   Test Objective: Verify Signal Size coverage for Bias block   Test Objective: Verify Signal Size coverage for Complex to Magnitude-Angle block   Test Objective: Verify Signal Size coverage for Complex to Real-Imag block   Test Objective: Verify Signal Size coverage for Vector Concatenate and Matrix Concatenate block   Test Objective: Verify Signal Size coverage for Find Nonzero Elements block   Test Objective: Verify Signal Size coverage for Gain block   Test Objective: Verify Signal Size coverage for Magnitude-Angle to Complex block   Test Objective: Verify Signal Size coverage for Math Function block   Test Objective: Verify Signal Size coverage for MinMax block   Test Objective: Verify Signal Size coverage for Permute Dimensions block   Test Objective: Verify Signal Size coverage for Real-Imag to Complex block   Test Objective: Verify Signal Size coverage for Reshape block   Test Objective: Verify Signal Size coverage for Rounding Function block   Test Objective: Verify Signal Size coverage for Reciprocal Sqrt, Signed Sqrt, and Sqrt block   Test Objective: Verify Signal Size coverage for Sum block   Test Objective: Verify Signal Size coverage for Trigonometric Function block  Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
Abs;Abs_double;Abs_double_mat;Abs_double_partial;Abs_double_vector;Abs_int;Abs_int16_mat;Abs_int16_partial;Abs_int16_vector;Abs_int32_mat;Abs_int32_partial;Abs_int32_vector;Abs_int64_mat;Abs_int64_partial;Abs_int64_vector;Abs_int8_mat;Abs_int8_partial;Abs_int8_vector;Abs_off_int;Abs_on_int;Abs_on_int16_mat;Abs_on_int16_vec;Abs_on_int32_mat;Abs_on_int32_vec;Abs_on_int64_mat;Abs_on_int64_vec;Abs_on_int8_mat;Abs_on_int8_vec;Abs_on_partial_int;Abs_single;Abs_single_mat;Abs_single_partial;Abs_single_vector;Add;Add_int;Add_u;Algebraic Constraint;Assignment;B;Bias;Complex to Magnitude-Angle;Complex to Real-Imag;Concatenate;Constant;Data Type Conversion;Decision;Display z;Divide;Dot Product;Enable;Execution and Signal Range;Find Nonzero Elements;From;Full Decision Coverage;Gain;Goto;Horizontal Matrix Concatenate;Magnitude-Angle to Complex;Math Function;Matrix Concatenate;Max;Max_FullDC_double;Max_FullDC_single;Max_FullDC_vec_double;Max_FullDC_vec_int;Max_FullDC_vec_single;Max_Partial1_double;Max_Partial1_single;Max_Partial1_vec_double;Max_Partial1_vec_int;Max_Partial1_vec_single;Max_Partial2_double;Max_Partial2_single;Max_Partial2_vec_double;Max_Partial2_vec_int;Max_Partial2_vec_single;Max_int;Max_u;Min;MinMax;MinMax Running Resettable;Min_FullDC_double;Min_FullDC_single;Min_FullDC_vec_double;Min_FullDC_vec_int;Min_FullDC_vec_single;Min_Partial1_double;Min_Partial1_single;Min_Partial1_vec_double;Min_Partial1_vec_int;Min_Partial1_vec_single;Min_Partial2_double;Min_Partial2_single;Min_Partial2_vec_double;Min_Partial2_vec_int;Min_Partial2_vec_single;Min_int;Min_u;Multidimensional Matrix Concatenate;NegativeCase;Partial Decision Coverage;Permute Dimensions;Polynomial;PositiveCase;Product;Product of Elements;Ramp;Rate Transition;Real-Imag to Complex;Reciprocal Sqrt;Reference;Relational Boundary;Repeating Sequence Stair;Reshape;Rounding Function;RoundingFunction_ceil;RoundingFunction_fix;RoundingFunction_floor;RoundingFunction_round;Saturation on Integer Overflow;Sign;Sign_double;Sign_double_mat;Sign_double_partial;Sign_double_vector;Sign_in32_vector;Sign_int;Sign_int16_mat;Sign_int16_partial;Sign_int16_vector;Sign_int32_mat;Sign_int32_partial;Sign_int64_mat;Sign_int64_partial;Sign_int64_vector;Sign_int8_mat;Sign_int8_partial;Sign_int8_vector;Sign_single;Sign_single_mat;Sign_single_partial;Sign_single_vector;Signal Size;Signed Sqrt;SignedIntegers;Sine Wave;Sine Wave Function;Slider Gain;Sqrt;Squeeze;Step;SubSystem;Subtract;Subtract_int;Subtract_u;Sum;Sum of Elements;Sum of Elements_int;Switch;Terminator;Terminator_;Trigonometric Function;TrigonometricFunction_acos;TrigonometricFunction_asin;TrigonometricFunction_cos;TrigonometricFunction_sin;TrigonometricFunction_tan;Unary Minus;UnsignedIntegers;Vector Concatenate;Vertical Matrix Concatenate;Weighted Sample Time Math;cast;double;internal data;make_matrix;never;off_int;off_u

BLOCKTYPE:
Abs;AlgebraicConstraint;Assignment;Bias;ComplexToMagnitudeAngle;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Display;DotProduct;EnablePort;Find;From;Gain;Goto;Inport;MagnitudeAngleToComplex;Math;MinMax;MinMax Running Resettable;PermuteDimensions;Polyval;Product;Ramp;RateTransition;RealImagToComplex;Repeating Sequence Stair;Reshape;Rounding;SampleTimeMath;Signum;Sin;Slider Gain;Sqrt;Squeeze;Step;Sum;Switch;Terminator;Trigonometry;UnaryMinus

BLOCKTYPE_FREQUENCY:
162;4;4;26;8;8;60;421;390;4;23;37;10;11;66;4;2;8;39;114;2;4;2;29;4;2;8;146;6;10;16;66;213;2;33;2;4;30;126;720;60;16


MODELNAME: mMathOperationsFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mMathOperationsFxp.slx
DESCRIPTION: Model Coverage test case model for Math Operations
BLOCKTYPE_FREQUENCY: 38;5;8;19;38;6;12;11;7;8;7;46;9;4;6;96;2
CHECKSUM: 46DC81C58D067E7C0D6A1EDD6E9EA2F5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
partial coverage - missing (input - 0 = -LSB) parital coverage - missing (input - 0 = 0) partial coverage - missing (input - 0 = +LSB) Full Relational Boundary coverage  Test Objective: Verify Relational Boundary coverage for Abs block  Vectors and Matrices Scalars Vectors and Matrices Scalars  Test Objective: Verify Saturate on Integer Overflow coverage for Abs block   Test Objective: Verify Saturate on Integer Overflow coverage for Bias block  Does overflow Does not overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Dot Product block  Does overflow Does not overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Gain block  Does not overflow  Note: Saturate on integer overflow parameter is enabled for the Math Function block when the Function is set to magnitude^2, square, conj, reciprocal, or hermitian.  Test Objective: Verify Saturate on Integer Overflow coverage for Math Function block   Test Objective: Verify Saturate on Integer Overflow coverage for MinMax block   Test Objective: Verify Saturate on Integer Overflow coverage for Product block   Cast narrow  Cast narrow  Test Objective: Verify Saturate on Integer Overflow coverage for Sqrt block   Test Objective: Verify Saturate on Integer Overflow coverage for Sum block   Test Objective: Verify Saturate on Integer Overflow coverage for Unary Minus block  Does not overflow  Test Objective: Verify Saturate on Integer Overflow coverage for Weighted Sample Time Math block  Copyright 2020 The MathWorks, Inc.

BLOCK:
Abs;Abs_double;Abs_double_mat;Abs_double_partial;Abs_double_vector;Abs_int;Abs_int16_mat;Abs_int16_partial;Abs_int16_vector;Abs_int32_mat;Abs_int32_partial;Abs_int32_vector;Abs_int64_mat;Abs_int64_partial;Abs_int64_vector;Abs_int8_mat;Abs_int8_partial;Abs_int8_vector;Abs_off_sfix;Abs_on_mat;Abs_on_partial_sfix;Abs_on_sfix;Abs_on_vec;Abs_partial;Abs_single;Abs_single_mat;Abs_single_partial;Abs_single_vector;Add;Bias;Constant;Data Type Conversion;Dot Product;Enable;Gain;LSB;Math Function;Matrix Concatenate;Max_sfix;Max_ufix;MinMax;Min_sfix;Min_ufix;NegativeCase;PositiveCase;Product;Product of Elements;Reference;Relational Boundary;Repeating Sequence Stair;Saturation on Integer Overflow;Sqrt;SubSystem;Subtract;Sum;Sum of Elements;Terminator;Unary Minus;Vector Concatenate;Weighted Sample Time Math;make_matrix;off

BLOCKTYPE:
Abs;Bias;Concatenate;Constant;DataTypeConversion;DotProduct;EnablePort;Gain;Math;MinMax;Product;Repeating Sequence Stair;SampleTimeMath;Sqrt;Sum;Terminator;UnaryMinus


MODELNAME: mMessagesEvents
PATH: toolbox/qualkits/common/slcov/tests/mcov/mMessagesEvents.slx
DESCRIPTION: Model Coverage test case model for Messages & Events
BLOCKTYPE_FREQUENCY: 2;2;2;2;2;2;3;2;5;5;5
CHECKSUM: DE475F3A6447F59304E4C32F85BFF769
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Full DC Note: Message Send blocks get Decision coverage when the enable port is shown Partial DC  Test Objective: Verify Decision coverage for all blocks under simulink/Messages &amp; Events  Message Flow 1 Not instrumented for coverage Message Flow 1  Test Objective: Verify Execution coverage for all blocks under simulink/Messages &amp; Events  Copyright 2020-2021 The MathWorks, Inc.

BLOCK:
Constant;Decision;Enable;Execution;Hit Crossing Probe;NegativeCase;PostiveCase;Queue1 LIFO;Receive1 0.;Reference;Repeating Sequence Stair;Scope;Send;Sequence Viewer;Sine Wave1 0.;SubSystem;Terminator

BLOCKTYPE:
Constant;EnablePort;HitCross;MessageViewer;Queue;Receive;Repeating Sequence Stair;Scope;Send;Sin;Terminator


MODELNAME: mModelVerification
PATH: toolbox/qualkits/common/slcov/tests/mcov/mModelVerification.slx
DESCRIPTION: Model Coverage test case model for Model Verification library blocks
BLOCKTYPE_FREQUENCY: 2;1;1;1;1;1;1;1;1;1;1;16;1;2
CHECKSUM: 8C6A28C714543532CA7BC625EA82EBD6
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Verify Execution coverage for all blocks under simulink/Model Verification  Not instrumented for coverage Copyright 2020 The MathWorks, Inc.

BLOCK:
Assertion;Check Discrete Gradient;Check Dynamic Gap;Check Dynamic Lower Bound;Check Dynamic Range;Check Dynamic Upper Bound;Check Input Resolution;Check Static Gap;Check Static Lower Bound;Check Static Range;Check Static Upper Bound;Constant;Enable;Never;Reference;Sine Wave;SubSystem

BLOCKTYPE:
Assertion;Checks_DGap;Checks_DMax;Checks_DMin;Checks_DRange;Checks_Gradient;Checks_Resolution;Checks_SGap;Checks_SMax;Checks_SMin;Checks_SRange;Constant;EnablePort;Sin


MODELNAME: mPortsAndSubsystems
PATH: toolbox/qualkits/common/slcov/tests/mcov/mPortsAndSubsystems.slx
DESCRIPTION: Model Coverage test case model for Ports and Subsystems
BLOCKTYPE_FREQUENCY: 28;16;122;99;2;27;2;16;2;2;2;6;198;134;14;3;117;24;35;2;5;25;24;12;2;14;10;469;22;2;14;24
CHECKSUM: 102297C28CDC61283650E667B309A9E5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Test Objective: Verify Enabled Subsystem gets full coverage (DC, CC, MCDC) Input Conditions: Enable Port: Scalar signal Test Objective: Verify Enabled Subsystem gets full coverage (DC) Input Conditions: Enable Port: Vector signal Test Objective: Verify Enabled Subsystem gets partial coverage (CC, MCDC) Input Conditions: Enable Port: Vector signal  Test Objective: Verify Decision, Condition and MCDC coverage for Enabled and Triggered Subsystems  Input Conditions: Enable Port: Scalar signal Trigger Port: Scalar signal Test Objective: Verify Enabled and Triggered Subsystem get partial coverage (CC, MCDC) and full DC Input Conditions: Enable Port: Scalar signal Trigger Port: Vector signal Input Conditions: Enable Port: Scalar signal Trigger Port: Vector signal Input Conditions: Enable Port: Vector signal Trigger Port: Scalar signal Input Conditions: Enable Port: Scalar signal Trigger Port: Scalar signal Test Objective: Verify Enabled and Triggered Subsystem get full coverage (DC, CC, MCDC) Input Conditions: Enable Port: Vector signal Trigger Port: Vector signal Input Conditions: Enable Port: Vector signal Trigger Port: Vector signal Test Objective: Verify Enabled and Triggered Subsystem get partial coverage (DC, CC) and no MCDC Input Conditions: Enable Port: Vector signal Trigger Port: Scalar signal  Test Objective: Verify Decision, Condition and MCDC coverage for Enabled and Triggered Subsystems  Full DC Partial DC - no looping  Test Objective: Verify Decision coverage for the For Iterator block  No coverage metrics expected Test Objective: Verify If block gets full coverage (EC, DC, CC, MCDC). (scalar input)  * CC is not shown 100% in the report due the limitaion: expession in the IF block is always treated as short-circuited  Test Objective: Verify If block gets full coverage (EC, DC, CC, MCDC). (vector input) Test Objective: Verify If block gets partial coverage (CC, MCDC). (scalar input)  * CC is not shown 100% in the report due the limitaion: expession in the IF block is always treated as short-circuited  Test Objective: Verify If block gets partial coverage (CC, MCDC). (vector input) No coverage metrics expected No coverage metrics expected No coverage metrics expected Note: If blocks supports inputs of type Boolean, double, integer, and single. Boolean input type is tested in the basic coverage tests in this model.  Test Objective: Verify If block gets coverage with input of type double. (scalar input) Test Objective: Verify If block gets coverage with input of type single. (scalar input) Test Objective: Verify If block gets coverage with input of type signed integer. (scalar input) Test Objective: Verify If block gets coverage with input of type signed integer. (scalar input) No coverage metrics expected No coverage metrics expected No coverage metrics expected No coverage metrics expected  Test Objective: Verify Decision, Condition and MCDC coverage for If block  Input Conditions: Reset Port: Scalar signal Test Objective: Verify Resettable Subsystem gets full coverage (DC) Input Conditions: Reset Port: Scalar signal Test Objective: Verify Resettable Subsystem get partial coverage (DC)  Test Objective: Verify Decision coverage for Resettable Subsystems  Partial DC - missing default case Partial DC - missing 2nd case Full DC Full DC - No default case Full DC - No default case, multiple match Partial DC - No default case, missing implicit-default Full DC - No default case, multiple match, missing 2nd case and implicit-default  Test Objective: Verify Decision coverage for Switch Case block  Test Objective: Verify Triggered Subsystem get partial coverage DC and no (CC, MCDC) Test Objective: Verify Triggered Subsystem get full coverage (DC, CC, MCDC) Input Conditions: Trigger Port: Scalar signal Input Conditions: Trigger Port: Vector signal Test Objective: Verify Triggered Subsystem get partial coverage (CC, MCDC) and full DC Input Conditions: Trigger Port: Vector signal Input Conditions: Trigger Port: Scalar signal Test Objective: Verify Triggered Subsystem gets full coverage (DC)  Test Objective: Verify Decision, Condition and MCDC coverage for Triggered Subsystems  DO-While Configured blocks While Configured blocks Without a maximum iteration test With an unsatisfied maximum iteration test Full coverage With a satisfied maximum iteration test With a satisfied maximum iteration test Without a maximum iteration test Full coverage With an unsatisfied maximum iteration test  Test Objective: Verify Decision coverage for While Iterator Subsystems   1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Not Instrumented for Execution coverage Not instrumented for Execution coverage Masked Subsystems, not directly instrumented for Execution coverage  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Masked Subsystems, not directly instrumented for Execution coverage Not instrumented for Execution coverage Not Instrumented for Execution coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution coverage for all blocks under simulink/Ports &amp; Subsystems  Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1 - u2 = -tol..0) Partial Relational Boundary Coverage (missing u1 - u2 = 0..tol) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1 - u2 = 0) Partial Relational Boundary Coverage (missing u1 - u2 = -1) Partial Relational Boundary Coverage (missing u1 - u2 = +1) Partial Relational Boundary Coverage (missing u1 - u2 = +1) Partial Relational Boundary Coverage (missing u1 - u2 = -1) Partial Relational Boundary Coverage (missing u1 - u2 = 0) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1 - u2 = 0..tol) Partial Relational Boundary Coverage (missing u1 - u2 = -tol..0) Full Relational Boundary Coverage Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1 - u2 = 0) Partial Relational Boundary Coverage (missing u1 - u2 = -1) Partial Relational Boundary Coverage (missing u1 - u2 = +1) Partial Relational Boundary Coverage (missing u1 - u2 = +1) Partial Relational Boundary Coverage (missing u1 - u2 = -1) Partial Relational Boundary Coverage (missing u1 - u2 = 0) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1 - u2 = +1) Partial Relational Boundary Coverage (missing u1 - u2 = -1) Partial Relational Boundary Coverage (missing u1 - u2 = 0) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1(1) - 0 = 0) Full Relational Boundary Coverage Partial Relational Boundary Coverage (missing u1(1) - 0 = -1) Partial Relational Boundary Coverage (missing u1(1) - 0 = +1)  Test Objective: Verify Relational Boundary coverage for If block  Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
Action Port;Basic Coverage Test;Cast;Constant;DC and CC*;DC, CC and MCDC;Data Type Conversion;Data Type Test;Decision, Condition and MCDC;Enable;Enabled Subsystem;Enabled and Triggered Subsystem;EnbScalar;EnbScalar_TrigScalar;EnbScalar_TrigScalar_Partial;EnbScalar_TrigVector;EnbScalar_TrigVector_Partial;EnbVector_Full;EnbVector_Partial;EnbVector_TrigScalar;EnbVector_TrigScalar_Partial;EnbVector_TrigVector;EnbVector_TrigVector_Partial;Execution;For Each;For Each Subsystem;For Iterator;For Iterator Subsystem;Function-Call Feedback Latch;Function-Call Generator;Function-Call Split;Function-Call Subsystem;Gain;IC;If;If Action Subsystem;If Action Subsystem(else branch);If Action Subsystem(if branch);If_EQ;If_GE;If_GT;If_LE;If_LT;If_NC_Scalar;If_NC_Vector;If_NE;In;Mux;NOT;NegativeCase;NeverEnabled;NeverEnabledTriggered;NeverTriggered;Out;PositiveCase;PostiveCase;Pulse Generator;Reference;Relational Boundary;Relational Operator;Repeating Sequence Stair;Reset;Resettable Subsystem;ResettableSS_Full;ResettableSS_Never;ResettableSS_Partial;ShouldTrigger;Signal Builder;Signal Editor;SignalEditor;Sine Wave;Size-Type;Step;SubSystem;Subsystem;Sum;Switch;Switch Case;Switch Case Action Subsystem;Terminator;Terminator_;TrigScalar;TrigScalar_Partial;TrigVector;TrigVector_Partial;Trigger;Triggered Subsystem;Unit Delay;Unit System Configuration;Variant Subsystem;Vector Concatenate;While Iterator;While Iterator Subsystem;double;function;if;int;integer;pure int 0-1-;single;system;uin;unsigend integer;while

BLOCKTYPE:
ActionPort;Concatenate;Constant;DataTypeConversion;DiscretePulseGenerator;EnablePort;ForEach;ForIterator;Function-Call Generator;FunctionCallFeedbackLatch;FunctionCallSplit;Gain;If;Inport;Logic;Mux;Outport;RelationalOperator;Repeating Sequence Stair;Repeating table;ResetPort;SignalEditor;Sin;Step;Sum;Switch;SwitchCase;Terminator;TriggerPort;UnitConfiguration;UnitDelay;WhileIterator


MODELNAME: mSFArithLogic
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSFArithLogic.slx
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Demux;FromWorkspace;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 5;2;1;10;2;1;3
CHECKSUM: 2816F425A24906CE3E3A54D03E8D66CD
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Aux_Switch;Aux_Switch_State;Data Type Conversion;Demux;From Workspace;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch


MODELNAME: mSFConditionLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSFConditionLimit.slx
DESCRIPTION: Verify Model Coverage with Stateflow truth table (64 conditions and 64 decisions)
ANNOTATION: Stateflow Chart with 64 conditions Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Demux;Inport;Outport;Ramp;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;5;67;6;2;4;6
CHECKSUM: 6359A3871663D5ECACEB6B2F2310B5F0
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;64 sources;Chart;Data Type Conversion;Demux;MATLAB Function;Out;Ramp;Reference;ScalarInputs;SubSystem;Terminator;VectorInputs;in;out;u;y


MODELNAME: mSFDecisionLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSFDecisionLimit.slx
DESCRIPTION: Verify Model Coverage with Stateflow truth table (64 conditions and 64 decisions)
ANNOTATION: Stateflow Chart with 64 decisions Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Demux;Inport;Outport;Ramp;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;3;66;3;1;2;3
CHECKSUM: 4E19218482E27779A2B7611C0109F6B5
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;64 sources;Chart;Data Type Conversion;DecisionLimit;Demux;In;MATLAB Function;Out;Ramp;Reference;SubSystem;Terminator;in;out;u;y


MODELNAME: mSFMCDCLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSFMCDCLimit.slx
DESCRIPTION: Verify MCDC instrumented for expressions with mixed logical operator types and 12 conditions.
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: Constant;DataTypeConversion;Demux;Inport;Outport;S-Function;Step;Terminator
BLOCKTYPE_FREQUENCY: 2;1;1;24;2;1;1;2
CHECKSUM: A572564E8BD6890232072CE2CBD0B72A
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;ASS_stop_init;Chart;Constant;Data Type Conversion;In;MCDCLimit;Step;SubSystem;Terminator;in;out


MODELNAME: mSFRelCov
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSFRelCov.slx
BLOCKTYPE_FREQUENCY: 46;24;1;1;1;49;1;36;2;24;51;5
CHECKSUM: F93FFF52D5EF414AAA95F187CCCC2F13
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
single double signed int unsigned int 1) start, 2) update    F1=2;Gain1=5;Gain2=-3;   Misc scalar, time-varying Datatype: double Scalar, time-varying input Full coverage Datatype: double Scalar, time-varying input Partial coverage Dataypes: int16, double Expected Tolerance: varies based on double Dataype: double, uint32 Expected Tolerance: varies based on double Type Combinations Copyright 2014-2016 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Constant;Duration_Timer;Floating-Point Input;Gain;Integer Input;Misc;Mux;Out;Pulse Generator;Reference;Repeating Sequence Stair;SC;Scalar, Time-Varying Input;SubSystem;Subsystem;Terminator;Timer;Trigger;Type Combinations;desired_duration;do_SF_fix();do_subsystem11();do_subsystem22();in;in1_vec;input;input_events;maxval;minval;out;same_x_out;start_event;start_timer();tc;tick;timer_expired;timer_expired_flag;update_event;update_timer();x_in;y

BLOCKTYPE:
Constant;Demux;DiscretePulseGenerator;Duration_Timer;Gain;Inport;Mux;Outport;Repeating Sequence Stair;S-Function;Terminator;TriggerPort


MODELNAME: mSFRelCov_Fxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSFRelCov_Fxp.slx
BLOCKTYPE: Constant;Demux;Inport;Merge;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 23;13;25;1;14;13;26
CHECKSUM: 311C6D810B7E93BF87E3D9A6A4EE3206
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
fixed-point Misc Dataypes: sfix8_En1, sfix16_En2 Expected Tolerance: 0.25 Dataypes: sfix16_En2, double Expected Tolerance: approx 0.5 Dataype: int16, ufix8_En1 Expected Tolerance: 0.5 Dataypes: sfix16_En2, sfix8_En1 Expected Tolerance: 0.25 Dataype: sfix8_En1, int8 Expected Tolerance: 0.5 Type Combinations Dataypes: sfix8_En1, sfix16_En2 Expected Tolerance: 0.25 Dataypes: sfix8_En4, int32 Expected Tolerance: 0.0625 Copyright 2014-2016 The MathWorks, Inc.

BLOCK:
 Demux ; Merge ; SFunction ; Terminator ;Constant;Fixed-Point Input;Misc;State1.State;SubSystem;Terminator;Type Combinations;in;in1_vec;in2_vec;input;maxval;minval;tc;y


MODELNAME: mSF_TooComplexMcdc
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSF_TooComplexMcdc.slx
BLOCK: Demux ; SFunction ; Terminator ;Ground_;Input;Output;SubSystem;Terminator_;test
BLOCKTYPE: Demux;Ground;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;53;53;6;1;7
CHECKSUM: 9ED8B2243E1B7CCAFF59B9830086A8E1
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Verify that expressions too complex for MCDC instrumentation will throw a warning and will not be instrumented in the generated report. This test case model has two examples: mSFTooComplexMcdc/test/State1/State2/State7 mSFTooComplexMcdc/test/State1/State2/State10 Copyright 2009-2020 The MathWorks, Inc.


MODELNAME: mSLConditionLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSLConditionLimit.slx
BLOCKTYPE: DataTypeConversion;Demux;Inport;Logic;Outport;Ramp;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 2;3;2;2;2;2;2;4
CHECKSUM: 40802EF98EC830B56CCBD37EF69AEF25
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
OR block with 64 separate inputs. OR block with 64 element vector input. Simulink logic expression with 64 conditions Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Data Type Conversion;Demux;Logical Operator;MATLAB Function;Ramp;Reference;ScalarInputs;SubSystem;Terminator;VectorInputs;u;y


MODELNAME: mSLDecisionLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSLDecisionLimit.slx
ANNOTATION: Simulink expression with 64 decisions Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: ActionPort;Constant;DataTypeConversion;If;Inport;Outport;Ramp;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 65;65;1;1;64;65;1;65;65
CHECKSUM: C0EEFAB1556E8A6BFC287A9DD9B23F52
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
Action Port;Constant;Data Type Conversion;DecisionLimit;If;If Action Subsystem;In;Out;Ramp;Reference;SubSystem;Terminator;Unit Delay


MODELNAME: mSL_TooComplexMcdc
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSL_TooComplexMcdc.slx
BLOCKTYPE: Constant;Inport;Logic;Outport;Repeating Sequence Stair;Step
BLOCKTYPE_FREQUENCY: 1;2;10;2;25;3
CHECKSUM: 2FFD47697ACFB38D6879AE4B9DE6AF8E
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Verify Simulink Coverage behavior when logic is too complex to be instrumented. The logic on block LogicOp_Root will not be instrumented for MCDC when the configuration parameter Treat Simulink logic blocks as short-circuited is not checked.  Copyright 2022 The MathWorks, Inc.

BLOCK:
ASS_stop_init;And;And_Casc;Constant;In;LogicOp_Root;LogicOp_Root_Casc;Reference;Repeating Sequence Stair;Step


MODELNAME: mSignalAttributes
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalAttributes.slx
DESCRIPTION: Model Coverage test case model for Signal Attributes
BLOCKTYPE_FREQUENCY: 2;2;16;58;2;2;82;2;4;16;2;6;6;2;2;48;2;6;2;22;8;116;6;2
CHECKSUM: 34E732C801FE2AEAACD5ABFE80128B81
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Masked Subsystems, not directly instrumented for Execution coverage Not instrumented for Execution Coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Masked Subsystems, not directly instrumented for Execution coverage Not instrumented for Execution Coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution and Signal Range coverage for all blocks under simulink/Signal Attributes  Scalars Vectors and Matrices Vectors and Matrices Scalars  Test Objective: Verify Saturate on Integer Overflow coverage for Data Type Conversion block   Test Objective: Verify Signal Size coverage for Signal Conversion block   Test Objective: Verify Signal Size coverage for Unit Conversion block  Copyright 2020 The MathWorks, Inc.

BLOCK:
Bus Creator;Bus to Vector;Constant;DTC_off_int;DTC_off_u;DTC_on_int;DTC_on_int16_mat;DTC_on_int16_vec;DTC_on_int32_mat;DTC_on_int32_vec;DTC_on_int64_mat;DTC_on_int64_vec;DTC_on_int8_mat;DTC_on_int8_vec;DTC_on_partial_int;DTC_on_partial_u;DTC_on_u;DTC_on_u16_mat;DTC_on_u16_vec;DTC_on_u32_mat;DTC_on_u32_vec;DTC_on_u64_mat;DTC_on_u64_vec;DTC_on_u8_mat;DTC_on_u8_vec;Data Type Conversion;Data Type Conversion Inherited;Data Type Duplicate;Data Type Propagation;Enable;Execution and Signal Range;Gain;IC;In;NegativeCase;Out;PositiveCase;Probe;Rate Transition;Reference;Repeating Sequence Stair;Saturation on Integer Overflow;Signal Conversion;Signal Size;Signal Specification;Sine Wave;SubSystem;Switch;Terminator;Unit Conversion;Unit Conversion Test;Unit Conversion_matrix;Unit Conversion_vector;Vector Concatenate;Weighted Sample Time;Width

BLOCKTYPE:
BusCreator;BusToVector;Concatenate;Constant;Conversion Inherited;Data Type Propagation;DataTypeConversion;DataTypeDuplicate;EnablePort;Gain;InitialCondition;Inport;Outport;Probe;RateTransition;Repeating Sequence Stair;SampleTimeMath;SignalConversion;SignalSpecification;Sin;Switch;Terminator;UnitConversion;Width


MODELNAME: mSignalRangeLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalRangeLimit.slx
BLOCK: In;Input;Out;SubSystem;Subsystem;Unit Delay
BLOCKTYPE: Constant;Inport;Outport;UnitDelay
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: C6DF42D2400C24210E848BF43FE8C2F8
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Signal Range coverage collected when number of signals (number of elements) is less than or equal to limit (65535). Copyright 2020-2023 The MathWorks, Inc.


MODELNAME: mSignalRangeLimitNeg
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalRangeLimitNeg.slx
BLOCK: In;Input;Out;SubSystem;Subsystem;Unit Delay
BLOCKTYPE: Constant;Inport;Outport;UnitDelay
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: FCB1BF30ECBACEA414D16E0A7C3BF30E
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Signal Range coverage is not collected when number of signals (number of elements) is over the limit (65535). Copyright 2020 The MathWorks, Inc.


MODELNAME: mSignalRangeLimitNegFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalRangeLimitNegFxp.slx
BLOCK: In;Input;Out;SubSystem;Subsystem;Unit Delay
BLOCKTYPE: Constant;Inport;Outport;UnitDelay
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: 88C1F382EBA6F5A8F2905A4D423DCBA5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Signal Range coverage not collected when number of signals (number of elements) is over the limit (65535). Copyright 2020 The MathWorks, Inc.


MODELNAME: mSignalRouting
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalRouting.slx
DESCRIPTION: Model Coverage test case model for Signal Routing
BLOCKTYPE_FREQUENCY: 4;4;4;4;2;2;192;2;2;2;38;2;9;4;2;2;2;2;4;6;2;31;2;4;2;35;2;22;2;2;1;25;94;2;2;2
CHECKSUM: 79E273FDA4AD1E055B10B6EDAE4D95FE
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Full DC Partial DC - missing 1st element and default case Full DC Partial DC - missing 3rd element and default case Full DC Full DC  Note: An Index Vector is a special configuration of a Multiport Switch block in which you specify one data input and the control input is zero-based. The block output is the element of the input vector whose index matches the control input. To configure a Multiport Switch block to work as an Index Vector block, set Number of data ports to 1 and Data port order to Zero-based contiguous. Full DC Partial DC - missing 2nd element  Test Objective: Verify Decision coverage for Index Vector and Multiport Switch Blocks  Partial DC - always false Partial DC - always true Full DC  Test Objective: Verify Decision coverage for Switch Blocks  Verify State Reader and State Writer coverage (always gets execution coverage due to Simulink semantics) Not Instrumented Not instrumented No Instrumented Instrumented for Coverage (Nonvirtual bus)  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Concatenate block duplicated in Signal Routing and Math Operations Concatenate block duplicated in Signal Routing and Math Operations Verify State Reader and State Writer coverage (always gets execution coverage) Not Instrumented Not instrumented No Instrumented Instrumented for Coverage (Nonvirtual bus)  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution and Signal Range coverage for all blocks under simulink/Signal Routing  Missing (tigger - threshold) = 0 Full Relational Boundary coverage Missing (tigger - threshold) = -1 Missing (tigger - threshold) = +1 Full Relational Boundary coverage Missing (trigger-threshold) = [-tol..0] Missing (trigger-threshold) = [0..tol]  Test Objective: Verify Relational Boundary coverage for Switch block   Note: The Index Vector / Multiport Switch block can only overflow when the output casts the output value. Always overflow Overflow positive Overflow negative Never overflow Saturate on Integer Overflow off Overflow negative Overflow positive Always overflow Never overflow Saturate on Integer Overflow off  Test Objective: Verify Saturate on Integer Overflow coverage for Index Vector and Multiport Switch block  Overflow negative Overflow postive Always overflow Never overflow Saturate on Inetger Overflow off  Test Objective: Verify Saturate on Integer Overflow coverage for Switch block   Test Objective: Verify Signal Size coverage for Index Vector and Multiport Switch block   Test Objective: Verify Signal Size coverage for Manual Switch block   Test Objective: Verify Signal Size coverage for Switch block  Copyright 2020-2021 The MathWorks, Inc.

BLOCK:
Action Port;Bus Assignment;Bus Creator;Bus Selector;Bus to Vector;Constant;Control Input;Data Store Memory;Data Store Read;Data Store Write;Data Type Conversion;Decision;Demux;Enable;Event Listener;Execution and Signal Range;From;Goto;Goto Tag Visibility;If;If Action Subsystem;In;Index Vector;Index Vector and Multiport Switch;Initialize Function;Manual Switch;Merge;Multiport Switch;MultiportSwitch_OneBased;MultiportSwitch_ZeroBased;Mux;NegativeCase;Out;PositiveCase;PostiveCase;Ramp;Reference;Relational Boundary;Repeating Sequence Stair;Saturate onInteger Overflow;Selector;Signal Size;Sine Wave;State Reader;State Writer;Step;SubSystem;Switch;Switch_i;Switch_i8_partial;Switch_single;Switch_single_partial;Terminate Function;Terminator;Unit Delay;Variant Sink;Variant Source;Vector Concatenate;Vector of inputs

BLOCKTYPE:
ActionPort;BusAssignment;BusCreator;BusSelector;BusToVector;Concatenate;Constant;DataStoreMemory;DataStoreRead;DataStoreWrite;DataTypeConversion;Demux;EnablePort;EventListener;From;Goto;GotoTagVisibility;If;Inport;ManualSwitch;Merge;MultiPortSwitch;Mux;Outport;Ramp;Repeating Sequence Stair;Selector;Sin;StateReader;StateWriter;Step;Switch;Terminator;UnitDelay;VariantSink;VariantSource


MODELNAME: mSignalSizeLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalSizeLimit.slx
BLOCK: Narrow;Step;Switch;Terminator;Wide
BLOCKTYPE: Constant;Step;Switch;Terminator
BLOCKTYPE_FREQUENCY: 4;2;2;2
CHECKSUM: 2EC3E6102990E332FFF96101D57E9382
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Verify Signal Size coverage is collected when model contains two signals each at the signal width limit. Copyright 2020 The MathWorks, Inc.


MODELNAME: mSignalSizeLimitNeg
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalSizeLimitNeg.slx
BLOCK: Narrow;Step;Switch;Terminator;Wide
BLOCKTYPE: Constant;Step;Switch;Terminator
BLOCKTYPE_FREQUENCY: 2;1;1;1
CHECKSUM: 5C830D0693409860B26E89B754B6A532
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
 Test Objective: Verify Signal Size coverage is not collected when model contains a signal where the signal width is above the limit (65535). Copyright 2020 The MathWorks, Inc.


MODELNAME: mSignalSizeLimitNegFxp
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSignalSizeLimitNegFxp.slx
BLOCK: Narrow;Step;Switch;Terminator;Wide
BLOCKTYPE: Constant;Step;Switch;Terminator
BLOCKTYPE_FREQUENCY: 2;1;1;1
CHECKSUM: EC541A7CA72D4765832BA55EEC3F3892
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2020 The MathWorks, Inc.  Test Objective: Verify Signal Size coverage is not collected when model contains a signal where the signal width is above the limit (65535).


MODELNAME: mSinks
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSinks.slx
DESCRIPTION: Model Coverage test case model for Sinks
BLOCKTYPE_FREQUENCY: 1;2;2;1;2;2;4;2;4;2;4;2;2
CHECKSUM: B7CD0736107B165DB147EF6F0310BB64
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Not instrumented for Execution Coverage Not instrumented for Execution Coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks.  Test Objective: Verify Execution coverage for all blocks under simulink/Sinks  Copyright 2020 The MathWorks, Inc.

BLOCK:
Constant;Digital Clock;Display;Enable;Execution;Floating Scope;NegativeCase;Out;PostiveCase;Scope;Sine Wave;Step;Stop Simulation;SubSystem;Terminator;To File;To Workspace;XY Graph

BLOCKTYPE:
Constant;DigitalClock;Display;EnablePort;Outport;Record;Scope;Sin;Step;Stop;Terminator;ToFile;ToWorkspace


MODELNAME: mSources
PATH: toolbox/qualkits/common/slcov/tests/mcov/mSources.slx
DESCRIPTION: Model Coverage test case model for Source Library blocks
BLOCKTYPE_FREQUENCY: 2;2;5;2;2;2;2;1;2;2;2;2;2;2;2;2;2;2;2;2;2;2;2;50;2;2;2
CHECKSUM: CF377166FA5F1ADDFE0EB23E28B83D64
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Always executed  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Not instrumented for Execution Coverage Masked Subsystems, not directly instrumented for Execution coverage Always executed Masked Subsystems, not directly instrumented for Execution coverage Not instrumented for Execution Coverage  Note: Blocks with Background color set to &quot;orange&quot; are present to support verification of execution coverage. They may receive coverage, however the objective of this test is to show execution coverage of the Simulink library blocks. Copyright 2020-2022 The MathWorks, Inc.  Test Objective: Verify Execution and Signal Range coverage for all blocks under simulink/Sources 

BLOCK:
Band-Limited White Noise;Chirp Signal;Clock;Constant;Counter Free-Running;Counter Limited;Digital Clock;Enable;Enumerated Constant;From File;From Spreadsheet;From Workspace;Ground;In;NegativeCase;PositiveCase;Pulse Generator;Ramp;Random Number;Reference;Repeating Sequence;Repeating Sequence Interpolated;Repeating Sequence Stair;Signal Editor;Signal Generator;Sine Wave;Step;SubSystem;Terminator;Uniform Random Number;Waveform Generator

BLOCKTYPE:
Band-Limited White Noise.;Clock;Constant;Counter Free-Running;Counter Limited;DigitalClock;DiscretePulseGenerator;EnablePort;Enumerated Constant;FromFile;FromSpreadsheet;FromWorkspace;Ground;Inport;Ramp;RandomNumber;Repeating Sequence Interpolated;Repeating Sequence Stair;Repeating table;SignalEditor;SignalGenerator;Sin;Step;Terminator;UniformRandomNumber;WaveformGenerator;chirp


MODELNAME: mString
PATH: toolbox/qualkits/common/slcov/tests/mcov/mString.slx
DESCRIPTION: Model Coverage test case model for String Library blocks
BLOCKTYPE_FREQUENCY: 2;2;13;1;6;2;2;44;6;2;2;2;2;2;2;38;2
CHECKSUM: C86563B0EAE2A8EDE2AA6823EB3D54A5
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Always executed  Test Objective: Verify Execution coverage for all blocks under simulink/String  Copyright 2020 The MathWorks, Inc.

BLOCK:
ASCII to String;Compose String;Constant;Enable;NegativeCase;PositiveCase;Scan String;String Compare;String Concatenate;String Constant;String Contains;String Count;String Ends With;String Find;String Length;String Starts With;String to ASCII;String to Double;String to Enum;String to Single;SubSystem;Substring;Terminator;To String

BLOCKTYPE:
ASCIIToString;ComposeString;Constant;EnablePort;ScanString;StringCompare;StringConcatenate;StringConstant;StringContains;StringCount;StringFind;StringLength;StringToASCII;StringToEnum;Substring;Terminator;ToString


MODELNAME: mStub
PATH: toolbox/qualkits/common/slcov/tests/mcov/mStub.slx
ANNOTATION: Copyright 2015 The MathWorks, Inc.
BLOCKTYPE: ActionPort;Constant;DataTypeConversion;DiscretePulseGenerator;If;Outport;Sum;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 4;4;3;3;1;4;4;4;4
CHECKSUM: 70AC5C40A823FABBB377EF6357EF71E8
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
ActionPort;Constant;Data Type Conversion;Else Subsystem;If;SubSystem;Sum;T=17,W=5,D=;T=4,W=3,D=;T=9,W=2,D=;Terminator_;Unit Delay;count


MODELNAME: mTTNoCondition
PATH: toolbox/qualkits/common/slcov/tests/mcov/mTTNoCondition.slx
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: Demux;Display;Ground;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;1;3;3;1;1;1
CHECKSUM: BC3E06379E0D13409A4D4692A4A3074B
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Choose Start Gear Position;Display;DrvDir;DrvMd;GearPos;Ground;PreShiftReleaseBoolean;SubSystem


MODELNAME: mXORLimit
PATH: toolbox/qualkits/common/slcov/tests/mcov/mXORLimit.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: Constant;Logic;Step;Terminator
BLOCKTYPE_FREQUENCY: 4;4;4;4
CHECKSUM: CEB88D26523801CCB436754FD23D6119
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
Constant;NXORLimit;Step;SubSystem;Terminator;TwelveInputsNXOR;TwelveInputsXOR;VectorNXOR;VectorXOR;XORLimit


MODELNAME: m_sf_data_check
PATH: toolbox/qualkits/common/slcov/tests/mcov/m_sf_data_check.slx
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: Constant;Demux;Inport;Outport;S-Function;Step;Terminator
BLOCKTYPE_FREQUENCY: 2;1;4;4;1;2;5
CHECKSUM: 64F269F3BF7FF255E7DD51E80EDA3096
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;Constant;Step;SubSystem;Terminator;in_w;in_x;in_y;in_z;out_w;out_x;out_y;out_z


MODELNAME: mfcn
PATH: toolbox/qualkits/common/slcov/tests/mcov/mfcn.slx
ANNOTATION: Copyright 2009-2023 The MathWorks, Inc.
BLOCKTYPE: Constant;Fcn;MultiPortSwitch;Mux;Repeating table;Terminator
BLOCKTYPE_FREQUENCY: 12;7;1;6;13;7
CHECKSUM: 9C45A7B28D7693EF324CC388CC3018B4
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
Constant;Multiport Switch;Mux;Reference;Repeating Sequence;SubSystem;Terminator_;arithmetic;basic_and;basic_and_or_not;basic_or;complex_and_or_not;mcdc;mcdc_block


MODELNAME: mmodelblock
PATH: toolbox/qualkits/common/slcov/tests/mcov/mmodelblock.slx
BLOCK: Step;Terminator;condition;decision;eml;lookup;mcdc;multilevel
BLOCKTYPE: ModelReference;Step;Terminator
BLOCKTYPE_FREQUENCY: 6;3;7
CHECKSUM: 2A66D210369FD8D9DBD452BF63937EF8
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Top-level model for testing Model Reference Basic coverage types, each in a sub-model Top of a hierarchy containing both accelerated and normal-mode models. Copyright 2009-2011 The MathWorks, Inc.

EXTERNALFILE_REFERENCE:
mmodelblock_condition___Model_Block___mmodelblock_decision___Model_Block___mmodelblock_eml___Model_Block___mmodelblock_lookup___Model_Block___mmodelblock_mcdc___Model_Block___mmodelblock_multilevel___Model_Block___


MODELNAME: mmodelblock_topSF
PATH: toolbox/qualkits/common/slcov/tests/mcov/mmodelblock_topSF.slx
BLOCK: Step;Terminator;stateflow
BLOCKTYPE: ModelReference;Step;Terminator
BLOCKTYPE_FREQUENCY: 1;2;1
CHECKSUM: 978B5062253829C86E3AA682B42680EE
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
EXTERNALFILE_REFERENCE: mmodelblock_stateflow___Model_Block___
ANNOTATION:
Top-level model for testing Model Reference with Stateflow Basic coverage types, each in a sub-model Copyright 2009-2011 The MathWorks, Inc.


MODELNAME: mstate
PATH: toolbox/qualkits/common/slcov/tests/mcov/mstate.slx
ANNOTATION: Copyright 2009-2016 The MathWorks, Inc.
BLOCKTYPE: Demux;Outport;S-Function;Step;Terminator;TriggerPort
BLOCKTYPE_FREQUENCY: 1;9;1;1;10;1
CHECKSUM: 2F0F6BFF8D06A9498508415B67401231
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;Step;SubSystem;Terminator;d1out;d2out;d3out;d4out;d5out;d6out;d7out;trig


MODELNAME: truth_table_model
PATH: toolbox/qualkits/common/slcov/tests/mcov/truth_table_model.slx
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 22;1;8;5;5;7;2;2;2;8
CHECKSUM: 29BC7BE83B3A29C29917B1F9590B397D
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;2 way source;3 way source;ChartC;ChartD;Constant;Counter Limited;Demux;Full MCDC;LinkA;LinkB;LinkC;LinkD;Multiport Switch;Out;Reference;Repeating Sequence;Step;SubSystem;Terminator;in;out

BLOCKTYPE:
Constant;Counter Limited;Demux;Inport;MultiPortSwitch;Outport;Repeating table;S-Function;Step;Terminator


MODELNAME: mSrSWC
PATH: toolbox/qualkits/common/sldv/tests/mSrSWC.slx
ANNOTATION: Copyright 2016 The MathWorks, Inc.
BLOCKTYPE: ActionPort;Constant;Inport;Mux;Outport;Sum;SwitchCase;UnitDelay
BLOCKTYPE_FREQUENCY: 2;2;1;1;3;2;1;2
CHECKSUM: 9D67E8FC4D2FFC328C4A2918D3F28109
PRODUCT: IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
Action Port;Constant;In;Mux;Out;SubSystem;Sum;Switch Case;Switch Case Action Subsystem;Unit Delay;count


MODELNAME: Driver_Request_UTHarness_usingTestSeq
PATH: toolbox/qualkits/common/slreq/tests/Driver_Request_UTHarness_usingTestSeq.slx
BLOCKTYPE_FREQUENCY: 2;2;3;20;1;1;27;6;21;7;9;3;2;7;11;3;1
CHECKSUM: 847C2DD29550F9823F72F5DE60200D66
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
ANNOTATION:
This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Constant;CountValue;Delay;DriverSwRequest;Enumerated Constant;From_;Goto_;In;Inport_;Input Conversion Subsystem;LogicOp;Out;Outport_;Output Conversion Subsystem;RateTs_;Rate_Transition_;Reference;SigSpec_;SubSystem;Switch;Test Sequence;cncl;counter;dec;dec_out;dec_sw;decrement;delay_;doNot Repeat;else;enbl;in;inc;inc_out;inc_sw;increment;out;prev_req;relop;reqDrInv;reqDrv;reqMode;resume;set

BLOCKTYPE:
Constant;Delay;Demux;Enumerated Constant;From;Goto;Inport;Logic;Outport;RateTransition;RelationalOperator;S-Function;SLDV counter;SignalSpecification;Switch;Terminator;UnitDelay


MODELNAME: crs_controller
PATH: toolbox/qualkits/common/slreq/tests/crs_controller.slx
BLOCKTYPE_FREQUENCY: 3;11;8;5;5;2;1;5;72;30;1;13;1;145;29;2;95;20;57;5;2;2;1;21;6;29;7;6;1
CHECKSUM: 4282F094F8E103A3A1B3A36CA332DCBF
PRODUCT: Embedded Coder;IEC Certification Kit;Requirements Toolbox;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2020-2024 The MathWorks, Inc. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;Activate;Add;Compare To Constant;Constant;Conversion;CountValue;CruiseControlMode;DTI ;Data Type Conversion;Data_Conversion_;Delay;DriverSwRequest;Enable;EnumConst;Enumerated Constant;From;From_;Goto;Goto_;Harness Inputs;In;In_From_;In_Goto_;IncrementDecrement;Inport_;Input Conversion Subsystem;IsKeyPositionOn;IsShiftDrive;Kp;LogicOp;Logical Operator;Merge;Out;Out_From_;Out_Goto_;Outport_;Output Conversion Subsystem;PI controller;Proof Objective;RateTs_;Rate_Transition_;Reference;RelOp;Relational Operator;Saturation;SigSpec_;SubSystem;Sum;Switch;TargetSpeedThrottle;Terminator;Test Assessment Block;Test Sequence;UnitDelay;UsePI;ZOH;activate;activateCondition;activated;brakeP;buttonsShouldBeCalledWhenActivated;cancelActivation;cc_act_status;ccsw_request;cncl;counter;dec;dec_out;dec_sw;decrement;delay_;disableCaseDetection;disableCondition;disable_flag;disabled;doNot Repeat;ec;else;enableCondition;enableToResume;enabled;enbl;exp_reqDrv;gear;getActStatus;getNewTargetSpeed;getThrottleValue;harness_in_;harness_out_;hasCanceled;in;inc;inc_out;inc_sw;increment;isActivated;isDisabled;isEnabled;isResumed;isbrake;keepActivated;key;mode;mode_prev;opMode;out;outOfRange;outRange;outof_range;pressSetSw;prev_req;relop;reqDrInv;reqDrv;reqMode;resume;resumeCondition;resumeToActive;set;status;storeSpeed;stored_targetSp;targetSp;targetSpIn;targetSp_in;targetSp_pre;targetSp_prev;targetSpeed;throt;throtCC;throtDrv;throtPI;throttleCC;toBoolean;turnOffCruise;vehSp;waitingForButtonHolding;yesno

BLOCKTYPE:
Compare To Constant;Constant;DataTypeConversion;Delay;Demux;Design Verifier Proof Objective;DiscreteIntegrator;EnablePort;Enumerated Constant;From;Gain;Goto;Ground;Inport;Logic;Merge;Outport;RateTransition;RelationalOperator;S-Function;SLDV counter;Saturate;SignalEditor;SignalSpecification;Sum;Switch;Terminator;UnitDelay;ZeroOrderHold


MODELNAME: crs_plant
PATH: toolbox/qualkits/common/slreq/tests/crs_plant.slx
ANNOTATION: TORQUE CONVERTER Vehicle
BLOCKTYPE_FREQUENCY: 3;3;1;2;6;22;2;1;4;15;6;3;1;3;1;2;1;1;1
CHECKSUM: AAB743CAD0E761A01E02B1F88EF79E92
PRODUCT: IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ; gear;Data Type Conversion;Engine;Integrator;K factor;Look-Up;Look-Up Table;Ne;Nin;Nout;Product;Proof Objective;Reference;Sign;SubSystem;Sum;Switch;Ti;Tin;Torque Converter;Torque ratio;Tout;Transmission;Tt;Vehicle;brake torque;break;down_th;engine + impeller inertia;engine torque;f;final drive ratio;gear;impeller;interp_down;interp_up;linear speed;mph;out;quotient;road load;selection_state.calc_th;shift_logic;signed load;speed;speed ratio;status;throttDrv;throttle;throttleCC;transmission output speed;transmission output torque;transmission ratio;turbine;up_th;vehSp;vehicle inertia;vehicle speed;wheel speed

BLOCKTYPE:
DataTypeConversion;Demux;Design Verifier Proof Objective;Fcn;Gain;Inport;Integrator;Lookup2D;Lookup_n-D;Outport;Product;S-Function;Signum;Sum;Switch;Terminator;TriggerPort;torque converter;vehicle model


MODELNAME: driver_request
PATH: toolbox/qualkits/common/slreq/tests/driver_request.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;2;2;20;25;6;9;9;2;2;11;2
CHECKSUM: 88B09182C594C94F55623E522DDDEBC2
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Constant;CountValue;Delay;DriverSwRequest;Enumerated Constant;In;LogicOp;Out;Reference;SubSystem;Switch;cncl;counter;dec;dec_out;dec_sw;decrement;doNot Repeat;else;enbl;in;inc;inc_out;inc_sw;increment;out;prev_req;relop;reqDrInv;reqDrv;reqMode;resume;set

BLOCKTYPE:
Constant;Delay;Demux;Enumerated Constant;Inport;Logic;Outport;RelationalOperator;S-Function;SLDV counter;Switch;Terminator


MODELNAME: driver_sw_request_Harness
PATH: toolbox/qualkits/common/slreq/tests/driver_sw_request_Harness.slx
BLOCKTYPE: Demux;From;Goto;Inport;Outport;RateTransition;S-Function;SignalSpecification;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 1;1;1;14;14;7;1;7;1;1
CHECKSUM: 74B89F73085ABADEFCC4897CA207DB52
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
ANNOTATION:
This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;DriverSwRequest;From_;Goto_;Inport_;Input Conversion Subsystem;Outport_;Output Conversion Subsystem;RateTs_;Rate_Transition_;SigSpec_;SubSystem;Test Sequence;cncl;dec;delay_;enbl;harness_in_;harness_out_;inc;reqDrv;resume;set


MODELNAME: mCodeCoverage
PATH: toolbox/qualkits/common/sltest/tests/mCodeCoverage.slx
ANNOTATION: Copyright 2020-2022 The MathWorks, Inc.
BLOCKTYPE: CCaller;DataTypeConversion;EnablePort;Inport;Outport;SignalEditor
BLOCKTYPE_FREQUENCY: 1;4;1;4;8;1
CHECKSUM: 2B69D9C97E1C9A83EEDB92986888B298
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
C Caller;Data Type Conversion;Enable;Enabled Subsystem;Inport;Outport;Reference;Signal Editor;SubSystem


MODELNAME: mCov
PATH: toolbox/qualkits/common/sltest/tests/mCov.slx
ANNOTATION: Copyright 2020-2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;2;9;6;1;2;1;8;1;2;18;2;1;1;1;2;1;1;2
CHECKSUM: B331225CCB6DDA9245B8CB890AFE62BF
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Action Port;Add;Bus Creator;Bus Selector;Button_1_In;Button_1_State;Button_1_Status;Button_2_In;Button_2_State;Button_2_Status;Constant;CustomSaturationBlock;CustomSaturation_Out;Data Type Conversion;Enable;Enabled Subsystem;If;If Action Subsystem;If-else;In;LUT_Out;LookupTable;LowerLimit;MATLAB Function;MinMax;Output;Reference;Relational Operator;Saturation;Saturation_Out;Signal Editor;SignalInput;SubSystem;Subsystem;SwitchBlock;Switch_Out;TT_Out;Unit Delay;UpperLimit;u

BLOCKTYPE:
ActionPort;BusCreator;BusSelector;Constant;DataTypeConversion;Demux;EnablePort;If;Inport;Lookup_n-D;MinMax;Outport;RelationalOperator;S-Function;Saturate;SignalEditor;Sum;Switch;Terminator;UnitDelay


MODELNAME: mCov_SF
PATH: toolbox/qualkits/common/sltest/tests/mCov_SF.slx
ANNOTATION: Copyright 2020-2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;4;4;3;8;1;2;15;3;1;1;1;3
CHECKSUM: 831CE77B8FCE4743F5EF0B5C54ABDC3D
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Bus Creator;Bus Selector;ButtonStuckCheck;Button_1_In;Button_1_State;Button_1_Status;Button_2_In;Button_2_State;Button_2_Status;Constant;CustomSaturationBlock;CustomSaturation_Out;Data Type Conversion;In;LUT_Out;LookupTable;LowerLimit;MATLAB Function;MinMax;Output;Reference;Saturation;Saturation_Out;Signal Editor;SignalInput;SubSystem;SwitchBlock;Switch_Out;TT_Out;TruthTable;UpperLimit;u;y

BLOCKTYPE:
BusCreator;BusSelector;Constant;DataTypeConversion;Demux;Inport;Lookup_n-D;MinMax;Outport;S-Function;Saturate;SignalEditor;Switch;Terminator


MODELNAME: mCov_bottom
PATH: toolbox/qualkits/common/sltest/tests/mCov_bottom.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;9;4;1;2;1;9;1;2;18;2;1;1;2;1;1;2
CHECKSUM: 77720A9B9047F5ADA4FE2B5E55C12A8B
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Action Port;Add;Bus Selector;Button_1_In;Button_1_State;Button_1_Status;Button_2_In;Button_2_State;Button_2_Status;Constant;CustomSaturationBlock;CustomSaturation_Out;Data Type Conversion;Enable;Enabled Subsystem;If;If Action Subsystem;If-else;In;Inport;LUT_Out;LookupTable;LowerLimit;MATLAB Function;MinMax;Output;Relational Operator;Saturation;Saturation_Out;SignalInput;SubSystem;Subsystem;SwitchBlock;Switch_Out;TT_Out;Unit Delay;UpperLimit;u

BLOCKTYPE:
ActionPort;BusSelector;Constant;DataTypeConversion;Demux;EnablePort;If;Inport;Lookup_n-D;MinMax;Outport;RelationalOperator;S-Function;Saturate;Sum;Switch;Terminator;UnitDelay


MODELNAME: mCov_bottom_SF
PATH: toolbox/qualkits/common/sltest/tests/mCov_bottom_SF.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;4;4;3;9;1;2;15;3;1;1;3
CHECKSUM: 4CE00692AB7BCF03F5E6E9AE7BF77238
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Bus Selector;ButtonStuckCheck;Button_1_In;Button_1_State;Button_1_Status;Button_2_In;Button_2_State;Button_2_Status;Constant;CustomSaturationBlock;CustomSaturation_Out;Data Type Conversion;In;Inport;LUT_Out;LookupTable;LowerLimit;MATLAB Function;MinMax;Output;Saturation;Saturation_Out;SignalInput;SubSystem;SwitchBlock;Switch_Out;TT_Out;TruthTable;UpperLimit;u;y

BLOCKTYPE:
BusSelector;Constant;DataTypeConversion;Demux;Inport;Lookup_n-D;MinMax;Outport;S-Function;Saturate;Switch;Terminator


MODELNAME: mCov_top
PATH: toolbox/qualkits/common/sltest/tests/mCov_top.slx
ANNOTATION: Copyright 2020-2022 The MathWorks, Inc.
BLOCKTYPE: BusCreator;Constant;DataTypeConversion;ModelReference;Outport;Saturate;SignalEditor;Sin;Switch
BLOCKTYPE_FREQUENCY: 1;2;2;1;11;1;1;1;1
CHECKSUM: 2A9BD60FB74815EA1551D56060FF0075
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: DO;IE
EXTERNALFILE_REFERENCE: mCov_bottom.slx___Model_Block___
BLOCK:
Bus Creator;Constant;Data Type Conversion;Model;Outport;Reference;Saturation;Signal Editor;Sine Wave;Switch


MODELNAME: mGain
PATH: toolbox/qualkits/common/sltest/tests/mGain.slx
BLOCKTYPE_FREQUENCY: 2;2;2;2;16;6;19;4;2;3;12;2;2
CHECKSUM: 0FD289C2BA409B374CCC6ECFDA082245
PRODUCT: IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
ANNOTATION:
Copyright 2023 The MathWorks, Inc. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the source blocks to the interface required by the harnessed component. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure.

BLOCK:
 Demux ; SFunction ; Terminator ;From_;Gain;Goto_;Harness Inputs;In;Inport_;Input Conversion Subsystem;Out;Outport_;Output Conversion Subsystem;RateTs_;Rate_Transition_;Reference;SigSpec_;SubSystem;Test Sequence;delay_;mGain

BLOCKTYPE:
Demux;From;Gain;Goto;Inport;ModelReference;Outport;RateTransition;S-Function;SignalEditor;SignalSpecification;Terminator;UnitDelay


MODELNAME: mMF
PATH: toolbox/qualkits/common/sltest/tests/mMF.slx
ANNOTATION: Copyright 2015-2021 The MathWorks, Inc. Copyright 2015 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;2;2;1;4;1;2;2;2;1;2
CHECKSUM: 11B4EBA82188D5E6081CD5323C1448E1
PRODUCT: IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
BLOCK:
 ; Demux ; SFunction ; Terminator ;Digital Clock;Out;SubSystem;Test Sequence;bError;bMaint;bOff;bOn;bSwitch;bTC;error;input_;mMF;maint_request;power;sysState

BLOCKTYPE:
Constant;DataTypeConversion;Demux;DigitalClock;Inport;ModelReference;Outport;S-Function;Step;Switch;Terminator


MODELNAME: mOscillBeats
PATH: toolbox/qualkits/common/sltest/tests/mOscillBeats.slx
ANNOTATION: Copyright 2015-2021 The MathWorks, Inc. Copyright 2015 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Demux;Inport;ModelReference;Outport;S-Function;Sin;Sum;Terminator
BLOCKTYPE_FREQUENCY: 2;1;2;1;3;1;2;1;2
CHECKSUM: DF130959D2EFBA95B04A73EEB1D7408D
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Add;Out;SubSystem;Terminator;Test Sequence;bSin_;bSin_1 ;bTC_;input_;mOscillBeats


MODELNAME: mOscillBeatsSngl
PATH: toolbox/qualkits/common/sltest/tests/mOscillBeatsSngl.slx
ANNOTATION: Copyright 2015-2022 The MathWorks, Inc. Copyright 2015 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Demux;Inport;ModelReference;Outport;S-Function;Sin;Sum;Terminator
BLOCKTYPE_FREQUENCY: 2;1;2;1;3;1;2;1;2
CHECKSUM: A89959D5E1A63FE35B75D5919342AA90
PRODUCT: IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Add;Out;SubSystem;Terminator;Test Sequence;bSin_;bSin_1 ;bTC;input_;mOscillBeats


MODELNAME: mPulseBeats
PATH: toolbox/qualkits/common/sltest/tests/mPulseBeats.slx
ANNOTATION: Copyright 2015-2022 The MathWorks, Inc. Copyright 2015 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Demux;FromWorkspace;Inport;ModelReference;Outport;S-Function;Sum;Terminator
BLOCKTYPE_FREQUENCY: 2;1;2;2;1;3;1;1;2
CHECKSUM: D74DAD7A109C18BEDADD67C915617441
PRODUCT: IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Add;From Workspace;Out;SubSystem;Terminator;Test Sequence;bTC_;input_;mPulseBeats


MODELNAME: mSawBeats
PATH: toolbox/qualkits/common/sltest/tests/mSawBeats.slx
ANNOTATION: Copyright 2015-2022 The MathWorks, Inc. Copyright 2015 The MathWorks, Inc.
BLOCKTYPE: Abs;DataTypeConversion;Demux;FromWorkspace;Inport;ModelReference;Outport;S-Function;Sum;Terminator
BLOCKTYPE_FREQUENCY: 2;2;1;2;2;1;3;1;1;2
CHECKSUM: 0666F18BE17DF6334B826D1387BFFCD3
PRODUCT: IEC Certification Kit;Simulink;Simulink Test
PRODUCT_BASECODE: DO;IE
BLOCK:
 Demux ; SFunction ; Terminator ;Add;From Workspace;Out;SubSystem;Terminator;Test Sequence;bAbs_;bTC_;input_;mSawBeats


MODELNAME: SDD_SF_ArithLogic
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_SF_ArithLogic.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: CMBlock;DataTypeConversion;Demux;FromWorkspace;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;5;2;1;10;2;1;3
CHECKSUM: E1F138E25D4E94D7A265948A476CB95B
PRODUCT: DO Qualification Kit;Embedded Coder;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;Aux_Switch;Aux_Switch_State;Data Type Conversion;Demux;From Workspace;Model Info;Reference;SubSystem;Terminator;cmd_RC;raw_Joystick;raw_Switch;state_Joystick;state_RC;state_Switch


MODELNAME: SDD_SF_data_check
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_SF_data_check.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: CMBlock;Constant;Demux;Inport;Outport;S-Function;Step;Terminator
BLOCKTYPE_FREQUENCY: 1;2;1;4;4;1;2;5
CHECKSUM: EB14B5B367D4099513EA298956DFB9E8
PRODUCT: DO Qualification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;Constant;Model Info;Reference;Step;SubSystem;Terminator;in_w;in_x;in_y;in_z;out_w;out_x;out_y;out_z


MODELNAME: SDD_SF_event
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_SF_event.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: CMBlock;Constant;Demux;DiscretePulseGenerator;Inport;Outport;S-Function;Terminator;TriggerPort
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;2;1
CHECKSUM: 1C28FD2CBEA4BCD036B37DF967E4F009
PRODUCT: DO Qualification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;Constant;E;Model Info;Pulse Generator;Reference;SubSystem;Terminator;falsein;out


MODELNAME: SDD_TT_Block
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_TT_Block.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: CMBlock;Demux;Display;Ground;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;1;1;3;3;1;1;1
CHECKSUM: 0E9FE467C734DDF8E55E6751ABB47437
PRODUCT: DO Qualification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;Choose Start Gear Position;Display;DrvDir;DrvMd;GearPos;Ground;Model Info;PreShiftReleaseBoolean;Reference;SubSystem


MODELNAME: SDD_Version_Description_Test
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_Version_Description_Test.slx
ANNOTATION: Copyright 2011 The MathWorks, Inc.
BLOCK: DocBlock;Gain;In;Model Info;Out;Reference
BLOCKTYPE: CMBlock;DocBlock;Gain;Inport;Outport
BLOCKTYPE_FREQUENCY: 1;1;1;1;1
CHECKSUM: 56D0EAE44D66FD197488338441A10DDF
PRODUCT: DO Qualification Kit;Embedded Coder;Simulink
PRODUCT_BASECODE: DO
DESCRIPTION:
This model is for testing the SDD Model Version information, the DOC block information, the Model Configuration information, and the Glossary and report explanation.


MODELNAME: SDD_cont
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_cont.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;1;1;7;1;7;1;1;1;1
CHECKSUM: 67CFD9DC5977E6F64BFD87DE49B00C10
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
BLOCK:
Constant;Derivative;Integrator;Model Info;Reference;Sine Wave;State-Space;Terminator;TransDelay;Transfer Fcn;VarDelay;Zero-Pole

BLOCKTYPE:
CMBlock;Constant;Derivative;Integrator;Sin;StateSpace;Terminator;TransferFcn;TransportDelay;VariableTransportDelay;ZeroPole


MODELNAME: SDD_discont
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_discont.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
BLOCKTYPE: Backlash;CMBlock;DeadZone;HitCross;Quantizer;RateLimiter;Relay;Saturate;Sin;Terminator
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;1;7;7
CHECKSUM: 016AD3E10FD43CFD4089100CA511C819
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
ANNOTATION:
This model should contain all blocks in the Discontinuities library that arent virtual or composed of other blocks. Copyright 2009-2011 The MathWorks, Inc.

BLOCK:
Backlash;Dead Zone;Hit Crossing;Model Info;Quantizer;Rate Limiter;Reference;Relay;Saturation;Sine Wave;Terminator


MODELNAME: SDD_discrete
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_discrete.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;1;1;11;1;11;1;1;1
CHECKSUM: 4AAD6BD49B9A47134E40EDE945592FFC
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
ANNOTATION:
This model should contain all blocks in the Discrete library that arent virtual or made up entirely of other blocks. Copyright 2009-2011 The MathWorks, Inc.

BLOCK:
Filter;Integer Delay;Integrator;Memory;Model Info;Reference;Scope;Sine Wave;Tapped Delay;Terminator;Unit Delay;ZOH;ss;tf;wma;zp

BLOCKTYPE:
CMBlock;Delay;DiscreteFilter;DiscreteIntegrator;DiscreteStateSpace;DiscreteTransferFcn;DiscreteZeroPole;Memory;Scope;Sin;Tapped Delay Line;Terminator;UnitDelay;Weighted Moving Average;ZeroOrderHold


MODELNAME: SDD_logic
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_logic.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2021 The MathWorks, Inc.
BLOCK: CombLogic;Model Info;Pulse Generator;Reference;Terminator;and;bitand;relop
BLOCKTYPE_FREQUENCY: 1;1;1;6;1;1;4
CHECKSUM: 21947AA5A480E6C9D083FDAE93DD328A
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
BLOCKTYPE:
Bitwise Operator;CMBlock;CombinatorialLogic;DiscretePulseGenerator;Logic;RelationalOperator;Terminator


MODELNAME: SDD_lookup
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_lookup.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;1;1;1;3;1;8;6
CHECKSUM: FD883717EBDB26CF5FAFA9949CBC2BC4
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
BLOCK:
1-D Lookup Table;2-D Lookup Table;Constant;Direct Lookup Table (n-D);Interpolation Using Prelookup;Lookup Table Dynamic;Model Info;Prelookup;Reference;Sine Wave;Terminator;n-D Lookup Table

BLOCKTYPE:
CMBlock;Constant;Interpolation_n-D;Lookup Table Dynamic;LookupNDDirect;Lookup_n-D;PreLookup;Sin;Terminator


MODELNAME: SDD_math
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_math.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;2;1;1;1;1;2;1;1;2;1;1;1;1;1;25;1;2;20;1;1
CHECKSUM: 0FE93E2F8326EDE8564063943E064BB8
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
ANNOTATION:
This model should contain all blocks in the Math Operations library that arent actually masked subsystems. Copyright 2009-2011 The MathWorks, Inc.

BLOCK:
Abs;Add;Assignment;Bias;Constant;Dot Product;Gain;Math Function;Max;Min;Model Info;Permute Dimensions;Polynomial;Product;Reference;Reshape;Round;Sign;Sine Wave;Squeeze;Sumel;Terminator;Trig;Unary Minus;c2ma;c2ri;concat;elprod;ma2c;ri2c;timemath

BLOCKTYPE:
Abs;Assignment;Bias;CMBlock;ComplexToMagnitudeAngle;ComplexToRealImag;Concatenate;Constant;DotProduct;Gain;MagnitudeAngleToComplex;Math;MinMax;PermuteDimensions;Polyval;Product;RealImagToComplex;Reshape;Rounding;SampleTimeMath;Signum;Sin;Squeeze;Sum;Terminator;Trigonometry;UnaryMinus


MODELNAME: SDD_other
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_other.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: CMBlock;Demux;Fcn;Inport;MATLABFcn;Outport;S-Function;Sin;Terminator
BLOCKTYPE_FREQUENCY: 1;3;1;3;1;3;3;5;8
CHECKSUM: 408DB0E2961A05779FDDE0C517157792
PRODUCT: DO Qualification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;EML;Fcn;MATLAB Fcn;Model Info;Reference;Sine Wave;SubSystem;Terminator;Truth Table;indata;outdata;u;y


MODELNAME: SDD_signals
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_signals.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
BLOCKTYPE_FREQUENCY: 3;1;1;1;2;1;1;1;1;1;1;1;1;1;1;1;1;1;1;1;14;1;13;1;1
CHECKSUM: 667BEE908B3F07C3D5306A7445CAD5A1
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
ANNOTATION:
This model should contain all blocks in the Signal Attributes and Signal Routing library that arent actually masked subsystems. Copyright 2009-2011 The MathWorks, Inc.

BLOCK:
Bus Creator;Bus Output;Bus Selector;Chirp Signal;Clock;Constant;Data Store Memory;Data Type Conversion;From;Goto;IC;In;MP switch;Model Info;Out;Probe;Pulse Generator;Rate Transition;Reference;Signal Conversion;Sine Wave;SubSystem;Subsystem;Switch;Terminator;Width;dsr;dsw

BLOCKTYPE:
BusCreator;BusSelector;CMBlock;Clock;Constant;DataStoreMemory;DataStoreRead;DataStoreWrite;DataTypeConversion;DiscretePulseGenerator;From;Goto;InitialCondition;Inport;MultiPortSwitch;Outport;Probe;RateTransition;Scope;SignalConversion;Sin;Switch;Terminator;Width;chirp


MODELNAME: SDD_sldemo_mdlref_basic
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_sldemo_mdlref_basic.slx
BLOCKTYPE: Constant;DiscretePulseGenerator;ModelReference;Outport;Scope
BLOCKTYPE_FREQUENCY: 2;3;3;3;3
CHECKSUM: C70DF174752C51E36914DDA8B56B3A3C
PRODUCT: DO Qualification Kit;MATLAB;Simulink
PRODUCT_BASECODE: DO
EXTERNALFILE_REFERENCE: mdlref_counter___Model_Block___
ANNOTATION:
Bus Block Demonstration This demonstration shows how signals may be grouped and ungrouped while retaining their names. In this demonstration, 5 signals are created and labelled appropriately. These signals are then muxd together to create a bus of signals. This bus of signals is then fed into the Bus Selector block. Inside of the Bus Selector block, the Pulse and Chirp signals are chosen to be output from the original signal bus. It is possible to place a nest signal buses and then still retrieve the original signal with its label.  Component-Based Modeling with Model Reference Copyright 1990-2014 The MathWorks, Inc.

BLOCK:
C;CounterA;CounterB;CounterC;More Info;OutA;OutB;OutC;Pulse Generator with Ts=0.;Pulse Generator with Ts=1.;ScopeA;ScopeB;ScopeC;SubSystem


MODELNAME: SDD_slvnvdemo_fuelsys_docreq
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_slvnvdemo_fuelsys_docreq.slx
BLOCKTYPE_FREQUENCY: 1;22;1;3;2;1;1;5;5;1;1;34;1;2;1;5;5;2;2;3;22;7;5;1;2;2;9;1;6;6;5;1;1;2
CHECKSUM: DEC4F28EA3E31EB9048A8640FA419C1F
PRODUCT: DO Qualification Kit;Embedded Coder;Simulink
PRODUCT_BASECODE: DO
DESCRIPTION:
Fault-Tolerant Fuel Control System with Microsoft(R) Word 2003 Requirements This example illustrates the association of Microsoft(R) Word requirements for a fault-tolerant fuel control system with its model implemented in Simulink(R) and Stateflow(R).

ANNOTATION:
Intake Manifold Vacuum Throttle Flow vs. Valve Angle and Pressure Air-Fuel Intake Dynamics Intake Airflow Estimation and Closed-Loop Correction Feedback Control Feedforward Control Loop Compensation and Filtering Fuel Rate Calculation MAP Estimation fuel rate controller Fault-Tolerant Fuel Control System with Microsoft(R) Word 2003 Requirements  Copyright 1990-2006 The MathWorks, Inc. Copyright 1990-2020 The MathWorks, Inc.

BLOCK:
Airflow calculation;Atmospheric Pressure, Pa (bar);Atmospheric Pressure, Pa (bar) ;Clock;Constant;Corrected;Data Type Conversion;Demux;Discrete Transfer Fcn (with initial outputs);EGO;EGO Sensor;EGO sensor;Enable;Engine Speed, N;F/A Norm;F/A Rich;Failures;Fcn;Fuel Calculation;Ground;High Speed (rad./sec.);In;Intake Manifold;Integrator;LOW Mode;Limit to Positive;Logic;Logical Operator;Look-Up Table;MAP;MAP (bar);MAP Estimate;MAP sensor;Manifold Pressure, Pm (bar);Mass Airflow Rate;Metered Fuel;MinMax;Mixing & Combustion;Multiport Switch;Mux;N (rad/sec);Nominal Speed;O2 fail (warmup);Out;Oxygen Sensor Switching Threshold;Pressure Estimate (2-D);Product;Pumping;Pumping Constant;RICH Mode;RT/Vm;Ramp Rate (Ki);Reference;Relational Operator;Selector;Sensor correction and Fault Redundancy;Sensors;Shutdown;Shutoff Mode;Sonic Flow ;Speed Estimate;Speed Table (2-D);SubSystem;Sum;Switch;Switchable Compensation;Terminator;Thrott Estimation Table (2-D);Throttle;Throttle & Manifold;Throttle Ang.;Throttle Angle, theta (deg);Throttle Estimate;Throttle Flow, mdot (g/s);Throttle transient correction;Zero-Order Hold;air flow;air/fuel mixture ratio;air/fuel ratio;direction;disablemode;engine gas dynamics;engine speed;est. air flow;f(theta);feedback correction;feedforward fuel rate;fuel;fuel rate;fuel rate controller;g(pratio);hold integrator;limit output;map;mdot Input (g/s);mdot to Cylinder (g/s);mode;o2_out;out_;p0 = 0.589 bar;sens_in;speed sensor;system lag;threshold = 0.;throttle;throttle angle;throttle command;throttle sensor;we

BLOCKTYPE:
Clock;Constant;DataTypeConversion;Demux;Discrete Transfer Function with Initial Outputs;DiscreteIntegrator;DiscreteTransferFcn;EnablePort;Fcn;Gain;Ground;Inport;Integrator;Logic;Lookup;Lookup2D;ManualSwitch;MinMax;MultiPortSwitch;Mux;Outport;Product;RelationalOperator;Repeating table;Saturate;Scope;Selector;Signum;Sum;Switch;Terminator;Transfer Function with Initial Outputs;ZeroOrderHold;enabled discrete-time transfer function


MODELNAME: SDD_slvnvdemo_fuelsys_htmreq
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_slvnvdemo_fuelsys_htmreq.slx
BLOCKTYPE_FREQUENCY: 1;22;1;3;2;1;1;5;5;1;1;34;1;2;1;5;5;2;2;3;22;7;5;1;2;2;9;1;6;6;5;1;1;2
CHECKSUM: 5900A3C4B32CF99B6D847C9CA504C7F3
PRODUCT: DO Qualification Kit;Embedded Coder;Simulink
PRODUCT_BASECODE: DO
DESCRIPTION:
Fault-Tolerant Fuel Control System with HTML Requirements This example illustrates the association of HTML requirements for a fault-tolerant fuel control system with its model implemented in Simulink(R) and Stateflow(R).

ANNOTATION:
Intake Manifold Vacuum Throttle Flow vs. Valve Angle and Pressure Air-Fuel Intake Dynamics Intake Airflow Estimation and Closed-Loop Correction Feedback Control Feedforward Control Loop Compensation and Filtering Fuel Rate Calculation MAP Estimation fuel rate controller Fault-Tolerant Fuel Control System with HTML Requirements Copyright 1990-2020 The MathWorks, Inc.

BLOCK:
Airflow calculation;Atmospheric Pressure, Pa (bar);Atmospheric Pressure, Pa (bar) ;Clock;Constant;Corrected;Data Type Conversion;Demux;Discrete Transfer Fcn (with initial outputs);EGO;EGO Sensor;EGO sensor;Enable;Engine Speed, N;F/A Norm;F/A Rich;Failures;Fcn;Fuel Calculation;Ground;High Speed (rad./sec.);In;Intake Manifold;Integrator;LOW Mode;Limit to Positive;Logic;Logical Operator;Look-Up Table;MAP;MAP (bar);MAP Estimate;MAP sensor;Manifold Pressure, Pm (bar);Mass Airflow Rate;Metered Fuel;MinMax;Mixing & Combustion;Multiport Switch;Mux;N (rad/sec);Nominal Speed;O2 fail (warmup);Out;Oxygen Sensor Switching Threshold;Pressure Estimate (2-D);Product;Pumping;Pumping Constant;RICH Mode;RT/Vm;Ramp Rate (Ki);Reference;Relational Operator;Selector;Sensor correction and Fault Redundancy;Sensors;Shutdown;Shutoff Mode;Sonic Flow ;Speed Estimate;Speed Table (2-D);SubSystem;Sum;Switch;Switchable Compensation;Terminator;Thrott Estimation Table (2-D);Throttle;Throttle & Manifold;Throttle Ang.;Throttle Angle, theta (deg);Throttle Estimate;Throttle Flow, mdot (g/s);Throttle transient correction;Zero-Order Hold;air flow;air/fuel mixture ratio;air/fuel ratio;direction;disablemode;engine gas dynamics;engine speed;est. air flow;f(theta);feedback correction;feedforward fuel rate;fuel;fuel rate;fuel rate controller;g(pratio);hold integrator;limit output;map;mdot Input (g/s);mdot to Cylinder (g/s);mode;o2_out;out_;p0 = 0.589 bar;sens_in;speed sensor;system lag;threshold = 0.;throttle;throttle angle;throttle command;throttle sensor;we

BLOCKTYPE:
Clock;Constant;DataTypeConversion;Demux;Discrete Transfer Function with Initial Outputs;DiscreteIntegrator;DiscreteTransferFcn;EnablePort;Fcn;Gain;Ground;Inport;Integrator;Logic;Lookup;Lookup2D;ManualSwitch;MinMax;MultiPortSwitch;Mux;Outport;Product;RelationalOperator;Repeating table;Saturate;Scope;Selector;Signum;Sum;Switch;Terminator;Transfer Function with Initial Outputs;ZeroOrderHold;enabled discrete-time transfer function


MODELNAME: SDD_sources
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_sources.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;1;1;1;1;11;1
CHECKSUM: E483880F72939FA728B8A069D28B9701
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
ANNOTATION:
This model should contain all blocks in the Sources library that arent actually masked subsystems. Copyright 2009-2011 The MathWorks, Inc.

BLOCK:
Clock;Constant;Digital Clock;From File;Model Info;Pulse Gen.;Rand;Reference;SignalGen;Sine Wave;Step;Terminator;URN;from workspace

BLOCKTYPE:
CMBlock;Clock;Constant;DigitalClock;DiscretePulseGenerator;FromFile;FromWorkspace;RandomNumber;SignalGenerator;Sin;Step;Terminator;UniformRandomNumber


MODELNAME: SDD_subsys
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_subsys.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
BLOCKTYPE_FREQUENCY: 11;4;4;1;21;1;4;1;3;1;4;1;6;1;57;1;3;4;65;1;3;1;1;1;14;1;1;7;4;12;2;1
CHECKSUM: F4A03FD9048B9966EBC51EF7CCD40FB3
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
ANNOTATION:
Other logic your model may need. Here we just count the number of times weve beed called. (Non iterated input) Other logic your model may need. Here we just count the number of times weve beed called. Other logic your model may need. Here we just count the number of times weve been called. Other logic your model may need. Here we just count the number of times weve been called. Copyright 2009-2022 The MathWorks, Inc.

BLOCK:
Abs;Abs Subsystem;Bus;Coefficients;Coeffs;Common Gain;Constant;Demux;Digital Clock;Discrete FIR Filter;Else Body subsystem;Enable;FS;Filter Each Element;For Each;For Iterator;For Iterator Subsystem;Funciton Call ;Function Call ;Function-Call Generator;Gain;If;If Body subsystem;IfAction;In;Logical Operator;Merge;Model Info;Mux;Out;OutNonVirBus;OutNonVirBusVect;OutVirBus;Product;Reference;Relational Operator;Scope;Signal;Sine Wave;Step;SubSystem;Sum;Switch;SwitchCase;Terminator;Trigger;Unit Delay;While Iterator;While Iterator Subsystem;Width;absIn;absOut;case off (default);case on;constant;count;counter with time;counter_case_off;counter_case_on;counter_else;counter_if;f;forIn;g;ifin;inInt;scalar_enb;swcasein;trig;trig_enb_scalar;vector_enb;voltage off;voltage on;voltage_to_hardware;whileIn;whileOut

BLOCKTYPE:
Abs;ActionPort;BusCreator;CMBlock;Constant;Demux;DigitalClock;DiscreteFir;EnablePort;ForEach;ForIterator;Function-Call Generator;Gain;If;Inport;Logic;Merge;Mux;Outport;Product;RelationalOperator;Scope;Sin;Step;Sum;Switch;SwitchCase;Terminator;TriggerPort;UnitDelay;WhileIterator;Width


MODELNAME: SDD_truth_table_model
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/SDD_truth_table_model.slx
DESCRIPTION: Simulink Report Generator (SDD Report) Test Model
ANNOTATION: Copyright 2009-2011 The MathWorks, Inc.
BLOCKTYPE: CMBlock;Constant;Demux;Inport;MultiPortSwitch;Outport;Repeating table;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;7;4;3;2;3;2;1;4
CHECKSUM: 4897008E945D3361FD552463F80A615B
PRODUCT: DO Qualification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;3 way source;ChartC;Constant;Demux;LinkA;LinkC;Model Info;Multiport Switch;Out;Reference;Repeating Sequence;SubSystem;Terminator;in;out


MODELNAME: mdlref_counter
PATH: toolbox/qualkits/do/rptgenext/src/rptgenext_project/tests/mdlref_counter.slx
ANNOTATION: Copyright 1990-2014 The MathWorks, Inc.
BLOCKTYPE: From;Goto;Inport;Logic;Outport;RelationalOperator;Scope;Sum;Switch;UnitDelay
BLOCKTYPE_FREQUENCY: 4;2;3;1;1;2;1;1;2;1
CHECKSUM: FD0B683B97368F3B2D13CA6060910FA7
PRODUCT: DO Qualification Kit;Simulink
PRODUCT_BASECODE: DO
BLOCK:
 input; input GE lower; limit; upper;Add;And;From;Goto;Previous Output;ScopeA;Switch;lower;output;upper GE input


MODELNAME: sf_car_base
PATH: toolbox/qualkits/do/slcmp/src/slcmp_project/tests/sf_car_base.slx
BLOCKTYPE_FREQUENCY: 3;2;6;18;2;5;14;6;3;1;1;1;3;2;1;1;1
CHECKSUM: F4AE171F314F3C60D31DCCC804EF21D4
PRODUCT: DO Qualification Kit;MATLAB;Simulink;Stateflow
PRODUCT_BASECODE: DO
ANNOTATION:
Vehicle TORQUE CONVERTER gear Double-click to open the GUI and select an input maneuver  Copyright 1997-2015 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ; gear;Engine;Integrator;K factor;Look-Up;Look-Up Table;Ne;Nin;Nout;Product;Reference;Sign;SubSystem;Sum;Ti;Tin;Torque Converter;Torque ratio;Tout;Tt;User Inputs;Vehicle;brake torque;down_th;engine + impeller inertia;engine RPM;engine torque;f;final drive ratio;gear;impeller;interp_down;interp_up;linear speed;mph;out;quotient;road load;selection_state.calc_th;shift_logic;signed load;speed;speed ratio;throttle;transmission;transmission output speed;transmission output torque;transmission ratio;turbine;up_th;vehicle inertia;vehicle speed;wheel speed

BLOCKTYPE:
Demux;Fcn;Gain;Inport;Integrator;Lookup_n-D;Outport;Product;S-Function;Scope;SignalEditor;Signum;Sum;Terminator;TriggerPort;torque converter;vehicle model


MODELNAME: sf_gfdemo_base
PATH: toolbox/qualkits/do/slcmp/src/slcmp_project/tests/sf_gfdemo_base.slx
ANNOTATION: Copyright 2001-2015 The MathWorks, Inc.
BLOCKTYPE: Demux;Gain;Inport;Outport;S-Function;Scope;Sin;Terminator
BLOCKTYPE_FREQUENCY: 2;2;4;2;2;1;2;2
CHECKSUM: BF8A4B52AD129950CF08649764A0DC1B
PRODUCT: DO Qualification Kit;Simulink;Stateflow
PRODUCT_BASECODE: DO
BLOCK:
 Demux ; SFunction ; Terminator ;Gain;Scope;Sine Wave;SubSystem;With Graphical Functions;Without Graphical Functions;inverse_input;normal_input;output


MODELNAME: baseModelConfiguration
DESCRIPTION: This is the base model from which the default model configurations are derived.
BLOCK: In;Out;Unit_Delay
BLOCKTYPE: Inport;Outport;UnitDelay
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: CEFA3463F2F972F598A4D5DAFA175150
PRODUCT: DO Qualification Kit;Embedded Coder;Simulink
PRODUCT_BASECODE: DO
PATH:
toolbox/qualkits/do/templates/templatessrc/src/do178_project/tools/templates/model_configurations/baseModelConfiguration.slx

ANNOTATION:
 This model is to be used for exporting model configuration. The model configuration has been verified against Modeling Standards for DO-178C/DO-331 and Simulink Code Inspector Compatibilities. The following procedure has been taken to achieve the final configuration: Verified against Code Generation Advisor with objectives set to Execution efficiency, ROM efficiency, RAM efficiency. Verified against Model Advisor checks under By Task &gt; Modeling Standards for DO-178C/DO-331. Verified against Model Advisor checks under By Product &gt; Simulink Code Inspector. ReturnWorkspaceOutputs enabled to avoid the need of Simulink Test override. Standard math library set to C99(ISO)


MODELNAME: doModelTemplate
DESCRIPTION: This is the base model from which the DO model template is derived.
CHECKSUM: 92BF720D4DFFC66E9108A5C9A7E46837
PRODUCT: DO Qualification Kit;Embedded Coder;Simulink
PRODUCT_BASECODE: DO
PATH:
toolbox/qualkits/do/templates/templatessrc/src/do178_project/tools/templates/model_templates/doModelTemplate.slx


MODELNAME: EC004
PATH: toolbox/qualkits/iec/ecoder/src/ecoder_project/tests/EC004/EC004.slx
BLOCKTYPE: CMBlock;Demux;Inport;Math;Outport;RelationalOperator;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;1;3;1;2;1;1;1
CHECKSUM: 604C44DF4C28848311611523BA86E1C4
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: IE
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;Math;Model Info;Reference;Relational Operator;SubSystem;a;i;in.;out.


MODELNAME: EC007
PATH: toolbox/qualkits/iec/ecoder/src/ecoder_project/tests/EC007/EC007.slx
BLOCKTYPE: CMBlock;Constant;DataTypeConversion;Inport;JKFlipFlop;Logic;Outport;Switch;Terminator
BLOCKTYPE_FREQUENCY: 1;1;3;2;1;1;1;1;1
CHECKSUM: D204F7344A2AA5D3F2F5FD1E95AE2453
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: IE
BLOCK:
Constant;Data Type Conversion;In;J-K Flip-Flop;Logical Operator;Model Info;Out;Reference;Switch;Terminator


MODELNAME: EC016
PATH: toolbox/qualkits/iec/ecoder/src/ecoder_project/tests/EC016/EC016.slx
BLOCKTYPE: CMBlock;Demux;DiscreteIntegrator;Inport;Outport;Product;S-Function;Sum;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 1;1;1;6;2;1;1;1;1;1
CHECKSUM: EF9537D7637A0E0038866833F888B7E2
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink;Stateflow
PRODUCT_BASECODE: IE
BLOCK:
 Demux ; SFunction ; Terminator ;Chart;Discrete-Time Integrator;Model Info;Product;Reference;SubSystem;Sum;Unit Delay;in.;k;l;m;n;out.


MODELNAME: EC201
PATH: toolbox/qualkits/iec/ecoder/src/ecoder_project/tests/EC201/EC201.slx
ANNOTATION: Copyright 2008-2012 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;4;2;11;1;1;3;1;1;1;1;1
CHECKSUM: 94204537628FCDC15FCA5B233DEEE519
PRODUCT: Embedded Coder;IEC Certification Kit;Simulink
PRODUCT_BASECODE: IE
BLOCK:
Abs;Bias;Complex to Real-Imag;Dot Product;Gain;In;Matrix Concatenate;MinMax Running Resettable;Model Info;Out;Polynomial;Reference;Rounding Function;Sign;Slider Gain;Squeeze;Subtract;Terminator;Trigonometric Function

BLOCKTYPE:
Abs;Bias;CMBlock;ComplexToRealImag;Concatenate;DotProduct;Gain;Inport;MinMax Running Resettable;Outport;Polyval;Rounding;Signum;Slider Gain;Squeeze;Sum;Terminator;Trigonometry


MODELNAME: ad9361_qpsk
PATH: toolbox/rfblks/supportpackages/adiagile/ad9361/blocks/ad9361_qpsk.slx
CHECKSUM: C78BC2C43E166DB3276B7AC0233F98BA
PRODUCT_BASECODE: SIM_RF_TRANS
ANNOTATION:
Start DFE only once in a bluemoon  General Notes: This block needs some noise on the input since packet gaps (aka all zeros) will cause false peaks Power Path Signal Path FeedForward Taps Decision Feedback Taps Generate training sequence when barker is found This inflation is necessary Proportional-plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence Max Phase Lock Delay= 1.3/(NormLoopBandwidth*SampleRate) Frequency Lock Delay = SampleRate*4*NormalizedPullInRange^2)/ (SampleRate*NormLoopBandwidth)^3; Pull in range (Hz) = 2*pi*sqrt(2)*DampingFactor*NormLoopBandwidth*SampleRate This is for QPSK and 4 SamplesPerSymbol ONLY An input of 4 should not happen unless the input is all zeros Mu is always positive e<<1/SPS

BLOCK:
 ; Demux ; SFunction ; Terminator ;1/SPS;Abs;Add;Add Constant;Backward Taps;Barker Code Generator;Barker Locate;Bias;Calculate New mu;Check Only Strobe Condition;Compare To Constant;Compare To Zero;Complex Phase Shift;Complex to Real-Imag;Constant;Convolutional Encoder;CountNCycles;Counter;DFE;Decision Buffer;Decision Directed;Delay;Delay To Reference Tap;Delay data so DFE can reset;Delay ref so DFE can reset;Detector;Direct Lookup Table (n-D);Discrete FIR Filter;Display;Dot Product;Downsample;Enable;End Pad;Error Rate Calculation;Extract Bits;Find Delay;Find Max and Set Output Shift;Forward Taps;Frame Conversion;Frame Recover;Frequency Recovery;Gain;Gardner TED Blocks;Gardner Timing Recovery;General CRC Generator;HDL Counter;Header;Imag Error;In;InputBuffer;Intergrator Gain;InterpControl_Blocks;Interpolator;K;LO_RX;LO_TX;Logical Operator;Loop Filter;LoopFilter;Mag;Map Symbol;Map [0,1,2,3,4] to [0,1,2,2,2];Math Function;Math Reciprocal;Matrix Concatenate;Maximum;Measure Phase Ambiguity;Middle Indx;Mod;Mod ;Multipath Rayleigh Fading Channel;Multiport Switch;NCOCounter;NCOCounter State;Normalize;OUT;One;Out;Out1 ;Output;PED;PN Sequence Generator;Packeted To Unpacked;Payload;Phase Ambiguity Correct;Phase Shift FP;Phi;Power;Product;Proportional Gain;QPSK Decisions;QPSK Demodulator Baseband;QPSK Modulator Baseband;QPSK_TX;RX;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;Real Error;Receiver;Ref;Reference;Reshape;Root;Rx;Rx Constellation;Sample and Hold;Scrambler;Squared;Start Pad;Strobe Buffer;Sub;SubSystem;Subsystem;Subtract;Sum;Sum of Elements;Switch;TED Buffer Update;TX;Terminator;Time Scope;Timing Preamble;Trigger;Unbuffer;Update mu on strobe;Vector Concatenate;W;Zero bit;Zero-Order Hold;ad9361_rx;ad9361_tx;available power [dBFS];available power [dBm];available power [dbFS];d;dB Conversion;dB Gain;dBFS Scale;data;dataIn;decision;e;eqOut;err;iqIn;lagBits;mu;new data;oldest;reset;resetTag;resetTagFrom;saved mu;start;strobe;strobe == W>NCOCounter;strobe sum;training;trigger;txData;v

BLOCKTYPE:
Abs;Barker Code Generator;Bias;Buffer;Compare To Constant;Compare To Zero;Complex Phase Shift;ComplexToRealImag;Concatenate;Constant;ConstellationDiagram;Convolutional Encoder;Counter;Delay;Demux;DiscreteFir;Display;DotProduct;DownSample;EnablePort;Error Rate Calculation;Extract Bits;Find Delay;FrameConversion;From;Gain;General CRC Generator;Goto;HDL Counter;Inport;Logic;LookupNDDirect;Math;Maximum;Memory;MultiPortSwitch;Outport;PN Sequence Generator;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;Random Integer Generator;RelationalOperator;Reshape;S-Function;SISO Fading Channel;Sample and Hold;Scope;Scrambler;Sqrt;Sum;Switch;Tapped Delay Line;Terminator;Unbuffer;ZeroOrderHold;ad9361_RX;ad9361_TX;dB Conversion;dB Gain

BLOCKTYPE_FREQUENCY:
1;2;2;3;4;2;1;6;4;14;1;1;1;32;1;6;12;2;1;1;1;2;1;3;2;9;1;1;1;48;2;3;7;1;2;8;43;2;12;2;8;2;1;4;1;2;1;1;1;1;1;3;28;7;3;3;1;1;1;1;3;1

PRODUCT:
Communications Toolbox;DSP System Toolbox;RF Blockset Models for Analog Devices RF Transceivers;Simulink


MODELNAME: ad9361_rx
PATH: toolbox/rfblks/supportpackages/adiagile/ad9361/blocks/ad9361_rx.slx
BLOCKTYPE_FREQUENCY: 4;1;3;1;1;1;1;6;4;1;1;1;6;1;3;1;3;5;2;1;5;4;1;1;5
CHECKSUM: 4A41982D521F27223E293ED6C2FE99EA
PRODUCT: DSP System Toolbox;MATLAB;RF Blockset Models for Analog Devices RF Transceivers;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
2Tones;Add;AntiAliasing;AntiAliasing ;Available Power [dBm];CW;CW+Modulation;ChannelOffset;Complex to Real-Imag;Constant;CountNCycles;CustomSignal;Delay;External LO;Frame Conversion;Gain;Ideal Source;In;Interpolation;Interpolation ;LTE;LTE_blocker;Manual Switch;Multiport Switch;Out;Power;Product;RX Signal;Real-Imag to Complex;Reference;Root;Spectrum Baseband [dBm];Spectrum RX [dBFS];Squared;SubSystem;Subsystem;Sum;Sum of Elements;Test Source;Zero-Order Hold;Zero-Order Hold ;ad9361_rx;dB Conversion;dB Gain;dB Gain CW blocker;dB Gain Custom Signal;dB Gain LTE;dB Gain LTE Blocker;dBFS Scaling

BLOCKTYPE:
Analog Filter Design;Buffer;ComplexToRealImag;Constant;Delay;Display;FrameConversion;Gain;Inport;ManualSwitch;Math;MultiPortSwitch;Outport;Product;RealImagToComplex;Scope;Signal From Workspace;Sine Wave;SpectrumAnalyzer;Sqrt;Sum;ZeroOrderHold;ad9361_RX;dB Conversion;dB Gain


MODELNAME: ad9361_rx_interferer
PATH: toolbox/rfblks/supportpackages/adiagile/ad9361/blocks/ad9361_rx_interferer.slx
CHECKSUM: 485F80B465C8C4669827193241023CE9
PRODUCT_BASECODE: SIM_RF_TRANS
ANNOTATION:
 The interfering signal in concatenated The output signal is complex BB with 2 signals, one representing the desired signal and one the interferer. Notice that they must have the same time step!  Added in the mask of the AD9361_RX and of the RF_RX, a parameter for the center frequency of the interfering signal. The distance (RF-Int) should be be larger than the envelope, otherwise simulation (of noise) will not be correct. In the mask of the RF_RX block simple calculations are done to reduce the harmonic order to speed up simulation. Simulation now will be slower as we are simulating more frequency bandwidths. The RF Blockset input port under the mask now accepts two signal envelopes.

BLOCK:
 Demux ; Rload; SFunction ; Terminator ;1/;ADC Overload Detector;ADC_H;ADC_I;ADC_L;ADC_Q;ADC_RX;AGC;Abs;Add;Amp_I;Amp_Q;Amplifier;Analog phase;AnalogPhase;AntiAliasing;AntiAliasing ;Assertion;Attack mode;Available Power [dBm];Average Power Meter;Bypass;Combinatorial Logic;Compare To Constant;Complex Phase Shift;Complex to Real-Imag;Configuration;Constant;Constant IP;CountNCycles;CountNCycles ;DCLeakage;DCleak;DDC_Filters_RX;Data Type Conversion;Delay;Demod;Demodulator;Demux;Detect Change;DetectChange;Direct Lookup Gain Table (n-D);Direct Lookup Phase Table (n-D);Equivalent Noise Figure;External LNA;External LO;ExternalLNA;ExternalLNA on/off;FIR Decimation;FIR Interpolation;Frame Conversion;Frame Conversion ;Gain;Gain Demod;Gain LPF [dB];Gain TIA;Gain TIA [dB];Gain Table;GainDemod;GainDemod [dB];GainImb;GainImbalance;GainLNA;GainLNA [dB];GainLPF;GainLPF ;GainTIA;Gnd;HTh;High;High ;HighThreshold;Hm;IP;IP2 Demod;Idealized ADC quantizer;In;In_I;In_Q;Index;Index ;Inner imag;Inner real;Inport;Integrator;Interpolation;Interpolation ;Invert Control;LMT Peak Detector;LMT_H;LMT_L;LNA;LNA ON;LNA on input;LNA on ouput;LO;LO Signal;LPF;LPFGain;LPF_I;LPF_Q ;LPF_RX;LTE;LTE_blocker;LTh;Leak;Logical Operator;Low;Low ;LowThreshold;Math Function;Math Function ;Max saturation power dBm;Mixer_I;Mixer_Q;Multiply;Mux;Out;OutLTh;OutQ;Out_HTh;Out_I;Out_Q;Outer imag;Outer real;Outport_I;Outport_Q;Peak;Peak Detector;Phase Shift;PhaseRF;Phase[deg];Power;Power [dBFS];PowerSensor;Product;Pulse Generator;Quantizer;R;R = f(gain, DCleak);RF Non Idealities;RF NonIdealities;RF phase;RF_RX;RMS;RX Signal;Real-Imag to Complex;Reference;Rload;Root;Rsource;START;Saturation;Sign;Sin;Sine Wave;Spectrum Baseband [dBm];Spectrum RX [dBFS];Squared;Step;SubSystem;Subsystem;Subtract;Sum;Sum ;Sum of Elements;TIA;TIA LPF I;TIA LPF Q;TIA_I;TIA_Q;Test Source;Times;ToRadians;Transport Delay;Trigger;Variable Phase Shift;Variable ResistorI;Variable ResistorQ;Vector Concatenate;VerifySampleTime;Wblk;Weighted Sample Time;Win;Wout;Zero-Order Hold;Zero-Order Hold ;a;ad9361_rx;avg_power;b;d;dB Conversion;dB Gain LTE;dB Gain LTE Blocker;dB2lin;dBFS;dBFS Scaling;demod;exp;expon;gain;gainImbalance;gain_index;in;input events;k;lna;log;lpf;mode;out;tia;u;y;y = f(gain, gainImbalance)

BLOCKTYPE:
Abs;Amplifier;Analog Filter Design;Assertion;Buffer;CombinatorialLogic;Compare To Constant;Complex Phase Shift;ComplexToRealImag;Concatenate;Configuration;Constant;DataTypeConversion;Delay;Demux;Detect Change;DiscretePulseGenerator;Display;Electrical Reference;FIR Decimation;FIR Interpolation;FrameConversion;Gain;IdealADC;Inport;Integrator;Logic;LookupNDDirect;Math;Mixer;Mux;Noise Source;Outport;PMIOPort;Phase Shift;Potentiometer;Product;Quantizer;RealImagToComplex;RelationalOperator;Resistor;S-Function;SampleTimeMath;Saturate;Scope;Signal From Workspace;Signum;Sine Wave;SpectrumAnalyzer;Sqrt;Step;Sum;Switch Two Terminal;Terminator;TransportDelay;TriggerPort;VGA;Variable Phase;ZeroOrderHold;ad9361_RX;dB Conversion;dB Gain

BLOCKTYPE_FREQUENCY:
4;1;8;1;4;3;1;1;9;1;1;21;6;4;4;5;3;15;2;3;2;4;38;2;75;6;9;2;9;2;4;1;62;8;1;2;6;3;6;6;3;2;1;5;1;2;2;1;2;2;1;22;3;4;2;2;5;1;8;1;2;2

PRODUCT:
Communications Toolbox;DSP System Toolbox;MATLAB;RF Blockset;RF Blockset Models for Analog Devices RF Transceivers;Simulink;Stateflow


MODELNAME: ad9361_tx
PATH: toolbox/rfblks/supportpackages/adiagile/ad9361/blocks/ad9361_tx.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;3;1;1;1;1;3;1;2;3;1;1;3;1;1;2
CHECKSUM: 7F6FA65174A590C8825D4ABDC8FFD8E0
PRODUCT: DSP System Toolbox;MATLAB;RF Blockset Models for Analog Devices RF Transceivers;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
2Tones;Add;Average Power [dBm];CW;CW+Modulation;Constant;CountNCycles;CustomSignal;External LO;Frame Conversion;Gain;Ideal Source;In;LTE;Manual Switch;Multiport Switch;Out;Power;Real-Imag to Complex;Reference;Root;Spectrum TX [dBm];Squared;SubSystem;Subsystem;Sum;Sum of Elements;Test Source;ad9361_tx;dB Conversion;dB Gain

BLOCKTYPE:
Buffer;Constant;Display;FrameConversion;Gain;Inport;ManualSwitch;Math;MultiPortSwitch;Outport;RealImagToComplex;Signal From Workspace;Sine Wave;SpectrumAnalyzer;Sqrt;Sum;ad9361_TX;dB Conversion;dB Gain


MODELNAME: ad9371_dpd
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_dpd.slx
CHECKSUM: 4B2CDF67D16A1AD76B996D873F5A66A0
PRODUCT_BASECODE: SIM_RF_TRANS
ANNOTATION:
Li Gan and Emad Abd-Elrady. Digital Predistortion of Memory Polynomial Systems Using Direct and Indirect Learning Architectures. Proceedings of the IASTED International Conference on Signal and Image Processing, SIP 2009. Use this block to estimate the delay introduced by the RF chain and align transmitted and received signals Regenerate a QPSK-modulated unipolar Barker code sequence to be compared with the received data  1. The original signal is expressed as y(t) = x(t)e^{j\phi}+n(t), t = 1, 2, ..., N 2. y_1(t) = x{*}(t)y(t) = e^{j\phi} + x{*}(t)n(t) The goal is to estimate the value \phi from the observation y_1(t), t = 1, 2, ...N i.e., estimate the value B = e^{j\phi}, and \phi = angle(B) 3. Suppose n(t) yields to a i.i.d. complex AWGN distribution N(0,\sigma^2). Then a non-biased estimator could be B_{est} = 1/N*sum(y_1(1:N)), and \phi_{est} = angle(B_{est}) and the variance of B_{est} is \sigma^2/N Each data frame contains 26 bits header (For Sync Purpose) and 174 bits data bits, first 105 bits contain Hello world ### message. Scrambler is there to improve data transition density and frequency offset estimation. ON CHIP RX ON CHIP TX

BLOCK:
 AnalogFilter ; Att; Demux ; SFunction ; Terminator ;+(1-L0);1-D Lookup Table;1/;1/Fs;ADC_I;ADC_Q;ADC_RX;AGC;ATT == ;Abs;Actual Attenuation ;Actual RFAtt;Actual TA;Actual_TA;Adaptive DPD Coefficient Calculation RPEM algorithm;Add;Align TX and RX;Amp_I;Amp_Q;Amplifier;Amplifier_I;Amplifier_Q;AnalogFilter;Assertion;Att;Att_Enable;Att_NF;Attenuation;Attenuation Dependent NoiseFigure;Attenuation Dependent NoiseFloor;Attenuator on input;Attenuator on ouput;BB;Band-Limited White Noise;Barker Code SS;Barker Code Symbol Generation ;BarkerRef;Bias;Bit Generation;BitsToDecimal;Buffer;Bypass;C;Coarse Frequency Compensation;Coef;Compare To Constant;Complex Phase Shift;Complex to Magnitude-Angle;Complex to Real-Imag;Compute R leakage;Configuration;Conj;Conjugate;Constant;Constant Barker Code;Constellation RX;Convert 1-D to 2-D;CountNCycles;Coupler;Cout;D = f(gain, gainImbalance);DC Offset [dBFS];DC offset;DDC_Filters_RX;DPD;DUC_Filters_TX;Data;Data Decoding;Data Type Conversion;DataOut;Delay;Delta;Demodulator;Demux;Descrambler;Descrambling;Digital Gain/Att;DigitalAtt;DigitalAttEnable;DigitalGain/Attenuation;DigitalGain/Attenuation ;Digital_Att;Digital_Att ;Direct Lookup Table (n-D);Divide;Divider;Dot Product;ERROR;Enable;Error;External ATT;External Attenuation Enabled ;External LO;External_Att;Fine Frequency Compensation;Frame Conversion;Frame Synchronizer;Gain;Gain Table;GainCorrection;Gain_Att;Gnd;Hermitian Transpose;I;IIP2 [dBm];IIP3 [dBm];IP2 = f(Att);IP3 = f(Att);IR;ImageReject [dBc];ImageRejection = f(Att);In;In_I;In_Q;Index;Index ;Internal ATT;Internal Attenuation;InternalATT_dB ;Interpolation filter;Interpolation filter ;Inverse Linear PA Gain;Invert Control;L;L(n-1);LO;LO Signal;LPF_RX;LPF_TX;Logical Operator;Lookup Table;MATLAB Function;Manual Switch;ManualGainIndex;Math Function;Matrix Concatenate;Mean;Mean Error Meas.;Mixer_I;Mixer_Q;Modulator;NF = f(Att);NF [dB];Noise;NoiseFloor;NominalGain;NominalGain [dB];OFF;OIP;OIP2 [dBm];OIP3 [dBm];ON;Out;OutI_Q;Out_I;Outport_I;Outport_Q;P;PA;PA In;PA Out;Phase;Phase Offset Detection;Phase Offset Estimator;Phase Shift;Phase/ Frequency Offset;Power ;Power Amplifier;Product;Product ;Q;Q gain [dB];QPSK Demodulator Baseband;QPSK Modulator Baseband;QPSK Receiver;QPSK TX;Quantizer;R;R = f(Att, Gain);R = f(Attenuation);R leakage [Ohm];RF;RF Attenuation;RF Signal;RFAntiAliasing;RFAntiAliasing ;RF_Att;RF_RX;RF_TX;RLoadI;RLoadQ;RPEM;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;Real-Imag to Complex;Reference;Repeat;Reset Signal;Reshape;Root;Rsource;Rx;S-parameters Antenna;Saturation;Scope;Scrambler;Selector;Signal Combiner;Signal From Workspace;Spectrum ADC;Spectrum RF;Spectrum TX - RX [dBFS];Squared;Stage;Sub ;SubSystem;Subsystem;Subtract;Sum;TA;TIA I;TIA Q ;Terminator;Thermal Noise;Times;Timing Recovery;TotalAttenuation;Transmission Line;Transport Delay;Unbuffer;Unit Delay;VGA;Variable Attenuator;VariableResistorI;VariableResistorQ;Vector Concatenate;VerifySampleTime;Weighted Sample Time;ad9371_orx;ad9371_tx;available power [dBm];dB Conversion;dB Gain;dB2lin;dBFS2dBm;dBFS2lin ;dataIn;disp ;exp;expon;gain;gainImbalance;in;index;log;out;u;v;y

BLOCKTYPE:
AGC;Abs;Amplifier;Analog Filter Design;Assertion;Band-Limited White Noise.;Bias;Buffer;Carrier Synchronizer;Coarse Frequency Compensator;Compare To Constant;Complex Phase Shift;ComplexToMagnitudeAngle;ComplexToRealImag;Concatenate;Configuration;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Descrambler;Display;DotProduct;Electrical Reference;EnablePort;FIR Decimation;FIR Interpolation;FrameConversion;Gain;Ideal Couplers;Ideal Dividers;Inport;Logic;LookupNDDirect;Lookup_n-D;MATLABSystem;ManualSwitch;Math;Mean;Mixer;Noise Source;Outport;PMIOPort;Phase Shift;Phase/Frequency Offset;Potentiometer;Power Amplifier with Memory;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;Quantizer;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;RandomNumber;RealImagToComplex;Repeat;Reshape;Resistor;S-Function;S-parameters;SampleTimeMath;Saturate;Scope;Scrambler;Selector;Signal Combiner;Signal From Workspace;SpectrumAnalyzer;Sqrt;Sum;Switch Two Terminal;Symbol Synchronizer;Terminator;Transmission Line;TransportDelay;Unbuffer;UnitDelay;VGA;Variable Attenuator;ZeroOrderHold;ad9371_orx;ad9371_tx;dB Conversion;dB Gain

BLOCKTYPE_FREQUENCY:
1;4;2;8;2;1;7;3;1;1;3;1;1;3;4;2;25;1;6;7;12;1;31;2;4;1;1;1;1;33;1;1;88;1;1;12;1;1;14;3;4;2;63;22;2;1;4;1;8;1;2;1;1;1;2;2;2;4;10;11;1;2;3;3;1;3;2;1;3;1;24;3;1;13;1;2;1;2;8;2;2;1;1;1;5

PRODUCT:
Communications Toolbox;DSP System Toolbox;MATLAB;RF Blockset;RF Blockset Models for Analog Devices RF Transceivers;Simulink;Stateflow


MODELNAME: ad9371_orx
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_orx.slx
BLOCKTYPE: Display;ManualSwitch;SpectrumAnalyzer;ad9371_orx
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: 7804B01F1136C53C968862661CEB01FD
PRODUCT: RF Blockset Models for Analog Devices RF Transceivers;Simscape;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
CW Signal;External LO;LTE signal;Manual Switch;Power ;Reference;Spectrum Baseband [dBm];Spectrum ORX [dBFS];SubSystem;Subsystem;ad9371_orx;available power [dBm]


MODELNAME: ad9371_orx_lte
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_orx_lte.slx
BLOCKTYPE: Display;SpectrumAnalyzer;ToWorkspace;ad9371_orx
BLOCKTYPE_FREQUENCY: 1;2;1;1
CHECKSUM: 9D2637D8A09D368D120F55D04133A0F3
PRODUCT: RF Blockset Models for Analog Devices RF Transceivers;Simscape;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
External LO;Power ;Reference;Spectrum Baseband [dBm];Spectrum RX [dBFS];SubSystem;Subsystem;TestSignalTX;To Workspace;ad9371_orx;available power [dBm] 


MODELNAME: ad9371_rf
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_rf.slx
BLOCKTYPE: Display;ManualSwitch;SpectrumAnalyzer;ad9371_rx
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: 9F0A808069E6167976210ACFADCF4FAA
PRODUCT: RF Blockset Models for Analog Devices RF Transceivers;Simscape;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
CW Signal;External LO;LTE signal;Manual Switch;Power ;Reference;Spectrum Baseband [dBm];Spectrum RX [dBFS];SubSystem;Subsystem;ad9371_rx;available power [dBm]


MODELNAME: ad9371_rx_lte
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_rx_lte.slx
BLOCKTYPE: Display;SpectrumAnalyzer;ToWorkspace;ad9371_rx
BLOCKTYPE_FREQUENCY: 1;2;1;1
CHECKSUM: E8AE5E4EF4093EF2B680C4EA67A6FFE0
PRODUCT: RF Blockset Models for Analog Devices RF Transceivers;Simscape;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
External LO;Power ;Reference;Spectrum Baseband [dBm];Spectrum RX [dBFS];SubSystem;Subsystem;TestSignalTX;To Workspace;ad9371_rx;available power [dBm]


MODELNAME: ad9371_snf
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_snf.slx
BLOCKTYPE: Display;ManualSwitch;SpectrumAnalyzer;ad9371_snf
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: F03A6E43BACEB04D0E06A839A48195F4
PRODUCT: RF Blockset Models for Analog Devices RF Transceivers;Simscape;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
CW Signal;LTE signal;Manual Switch;Power ;Reference;Spectrum Baseband [dBm];Spectrum SNF [dBFS];SubSystem;Subsystem;ad9371_snf;available power [dBm]


MODELNAME: ad9371_tx
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_tx.slx
ANNOTATION: Copyright 2016-2018 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Inport;ManualSwitch;Outport;SpectrumAnalyzer;ad9371_tx;dB Gain
BLOCKTYPE_FREQUENCY: 1;1;1;1;2;1;1
CHECKSUM: 83344FEA6779214225C37C5529D470D6
PRODUCT: DSP System Toolbox;RF Blockset Models for Analog Devices RF Transceivers;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
CW Signal;External LO;FixedPoint;In;LTE signal;Manual Switch;Out;Reference;Spectrum Baseband [dBFS];Spectrum TX [dBm];SubSystem;ad9371_tx;dBm2dBFS


MODELNAME: ad9371_tx_lte
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_tx_lte.slx
BLOCKTYPE: DataTypeConversion;Inport;Outport;SpectrumAnalyzer;ToWorkspace;ad9371_tx;dB Gain
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1
CHECKSUM: 3D039B64C60AB2ED47D4425D0FA15523
PRODUCT: DSP System Toolbox;RF Blockset Models for Analog Devices RF Transceivers;Simulink
PRODUCT_BASECODE: SIM_RF_TRANS
BLOCK:
External LO;FixedPoint;In;Out;Reference;Spectrum TX [dBm];SubSystem;Subsystem;TestSignalTX;To Workspace;ad9371_tx;dBm2dBFS


MODELNAME: ad9371_tx_orx_qpsk
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_tx_orx_qpsk.slx
CHECKSUM: 1F191987701AA225E66E25A3D9F3FD28
PRODUCT_BASECODE: SIM_RF_TRANS
ANNOTATION:
Regenerate a QPSK-modulated unipolar Barker code sequence to be compared with the received data  1. The original signal is expressed as y(t) = x(t)e^{j\phi}+n(t), t = 1, 2, ..., N 2. y_1(t) = x{*}(t)y(t) = e^{j\phi} + x{*}(t)n(t) The goal is to estimate the value \phi from the observation y_1(t), t = 1, 2, ...N i.e., estimate the value B = e^{j\phi}, and \phi = angle(B) 3. Suppose n(t) yields to a i.i.d. complex AWGN distribution N(0,\sigma^2). Then a non-biased estimator could be B_{est} = 1/N*sum(y_1(1:N)), and \phi_{est} = angle(B_{est}) and the variance of B_{est} is \sigma^2/N Each data frame contains 26 bits header (For Sync Purpose) and 174 bits data bits, first 105 bits contain Hello world ### message. Scrambler is there to improve data transition density and frequency offset estimation. ON CHIP RX ON CHIP TX Copyright 2016-2021 The MathWorks, Inc.

BLOCK:
 AnalogFilter ; Att; Demux ; Ground ; SFunction ; Terminator ;1-D Lookup Table;1/;1/Fs;ADC_I;ADC_Q;ADC_RX;AGC;ATT == ;Abs;Actual Attenuation ;Actual RFAtt;Actual TA;Actual_TA;Add;Amp_I;Amp_Q;Amplifier;Amplifier_I;Amplifier_Q;AnalogFilter;Antenna Impedance;Assertion;Att;Att_Enable;Att_NF;Attenuation;Attenuation Dependent NoiseFigure;Attenuation Dependent NoiseFloor;Attenuator on input;Attenuator on ouput;BB;Band-Limited White Noise;Barker Code SS;Barker Code Symbol Generation ;BarkerRef;Bernoulli Binary Generator;Bias;Bit Generation;BitsToDecimal;Buffer;Bypass;Coarse Frequency Compensation;Compare To Constant;Complex Phase Shift;Complex to Magnitude-Angle;Complex to Real-Imag;Compute R leakage;Configuration;Constant;Constant Barker Code;Constellation RX;Constellation TX;CountNCycles;Coupler;D = f(gain, gainImbalance);DC Offset [dBFS];DC offset;DDC_Filters_RX;DUC_Filters_TX;Data;Data Decoding;Data Type Conversion;DataOut;Delay;Delta;Demodulator;Demux;Descrambler;Descrambling;Digital Gain/Att;DigitalAtt;DigitalAttEnable;DigitalGain/Attenuation;DigitalGain/Attenuation ;Digital_Att;Digital_Att ;Direct Lookup Table (n-D);Divider;Enable;External ATT;External Attenuation Enabled ;External LO;External_Att;Fine Frequency Compensation;Frame Conversion;Frame Synchronizer;Gain;Gain Table;GainCorrection;Gain_Att;Gnd;I;IIP2 [dBm];IIP3 [dBm];IP2 = f(Att);IP3 = f(Att);IR;ImageReject [dBc];ImageRejection = f(Att);In;In_I;In_Q;Index;Index ;Internal ATT;Internal Attenuation;InternalATT_dB ;Interpolation filter;Interpolation filter ;Invert Control;LO;LO Signal;LPF_RX;LPF_TX;Logical Operator;Lookup Table;MATLAB Function;ManualGainIndex;Math Function;Matrix Concatenate;Mean;Message Generator;Message Source;Mixer_I;Mixer_Q;Modulator;NF = f(Att);NF [dB];Noise;NoiseFloor;NominalGain;NominalGain [dB];OFF;OIP;OIP2 [dBm];OIP3 [dBm];ON;Out;OutI_Q;Out_I;Outport_I;Outport_Q;PA;Phase;Phase Offset Detection;Phase Offset Estimator;Phase Shift;Phase/ Frequency Offset;Power ;Product;Q;Q gain [dB];QPSK Demodulator Baseband;QPSK Modulator Baseband;QPSK Receiver;QPSK TX;Quantizer;R;R = f(Att, Gain);R = f(Attenuation);R leakage [Ohm];RF;RF Attenuation;RF Signal;RF delay;RFAntiAliasing;RFAntiAliasing ;RF_Att;RF_RX;RF_TX;RLoadI;RLoadQ;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;Real-Imag to Complex;Reference;Repeat;Reset Signal;Reshape;Root;Rsource;Rx;Saturation;Scrambler;Selector;Signal Combiner;Spectrum ADC;Spectrum Baseband [dBFS];Spectrum ORX [dBFS];Spectrum RF;Spectrum TX [dBm];Squared;Stage;SubSystem;Subsystem;Subtract;Sum;TA;TIA I;TIA Q ;Terminator;Thermal Noise;Times;Timing Recovery;TotalAttenuation;Transport Delay;Unbuffer;Unit Delay;VGA;Variable Attenuator;VariableResistorI;VariableResistorQ;Vector Concatenate;VerifySampleTime;Weighted Sample Time;ad9371_orx;ad9371_tx;available power [dBm];dB Conversion;dB Gain;dB2lin;dBFS2dBm;dBFS2lin ;dataIn;disp ;exp;expon;gain;gainImbalance;in;index;log;msg;out;u;v;y

BLOCKTYPE:
AGC;Abs;Amplifier;Analog Filter Design;Assertion;Band-Limited White Noise.;Bernoulli Binary Generator;Bias;Buffer;Carrier Synchronizer;Coarse Frequency Compensator;Compare To Constant;Complex Phase Shift;ComplexToMagnitudeAngle;ComplexToRealImag;Concatenate;Configuration;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Descrambler;Display;Electrical Reference;EnablePort;FIR Decimation;FIR Interpolation;FrameConversion;Gain;Ground;Ideal Couplers;Ideal Dividers;Inport;Logic;LookupNDDirect;Lookup_n-D;MATLABSystem;Math;Mean;Mixer;Noise Source;Outport;PMIOPort;Phase Shift;Phase/Frequency Offset;Potentiometer;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;Quantizer;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;RandomNumber;RealImagToComplex;Repeat;Reshape;Resistor;S-Function;SampleTimeMath;Saturate;Scope;Scrambler;Selector;Signal Combiner;SpectrumAnalyzer;Sqrt;Sum;Switch Two Terminal;Symbol Synchronizer;Terminator;Transmission Line;TransportDelay;Unbuffer;UnitDelay;VGA;Variable Attenuator;ZeroOrderHold;ad9371_orx;ad9371_tx;dB Conversion;dB Gain

BLOCKTYPE_FREQUENCY:
1;2;2;8;2;1;1;6;2;1;1;3;1;1;2;4;2;25;2;6;1;11;1;31;5;1;1;1;1;31;1;1;1;79;1;1;12;1;10;2;4;2;60;22;2;1;4;4;1;2;1;1;1;2;2;2;1;11;10;2;3;1;1;3;2;5;1;20;3;1;12;1;2;1;2;8;2;2;1;1;1;5

PRODUCT:
Communications Toolbox;DSP System Toolbox;MATLAB;RF Blockset;RF Blockset Models for Analog Devices RF Transceivers;Simulink;Stateflow


MODELNAME: ad9371_tx_rx_qpsk
PATH: toolbox/rfblks/supportpackages/adiagile/ad9371/blocks/ad9371_tx_rx_qpsk.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;3;1;2;1;1;3;8;1;1;2;8;1;1;1;2;1;1;2;1;2;1;1;3;1;3;1;4;1;1;1;1
CHECKSUM: 9D1CBD3B1E9DD6011DF2BC589B9C33AF
PRODUCT_BASECODE: SIM_RF_TRANS
ANNOTATION:
Regenerate a QPSK-modulated unipolar Barker code sequence to be compared with the received data  1. The original signal is expressed as y(t) = x(t)e^{j\phi}+n(t), t = 1, 2, ..., N 2. y_1(t) = x{*}(t)y(t) = e^{j\phi} + x{*}(t)n(t) The goal is to estimate the value \phi from the observation y_1(t), t = 1, 2, ...N i.e., estimate the value B = e^{j\phi}, and \phi = angle(B) 3. Suppose n(t) yields to a i.i.d. complex AWGN distribution N(0,\sigma^2). Then a non-biased estimator could be B_{est} = 1/N*sum(y_1(1:N)), and \phi_{est} = angle(B_{est}) and the variance of B_{est} is \sigma^2/N Each data frame contains 26 bits header (For Sync Purpose) and 174 bits data bits, first 105 bits contain Hello world ### message. Scrambler is there to improve data transition density and frequency offset estimation.

BLOCK:
 Demux ; SFunction ; Terminator ;AGC;Barker Code SS;Barker Code Symbol Generation ;BarkerRef;Bit Generation;BitsToDecimal;Buffer;Coarse Frequency Compensation;Complex Phase Shift;Complex to Magnitude-Angle;Constant Barker Code;Constellation RX;Data;Data Decoding;DataOut;Descrambler;Descrambling;Enable;External LO;Fine Frequency Compensation;Frame Synchronizer;Gain;In;Math Function;Matrix Concatenate;Mean;Multipath Rayleigh Fading Channel;Out;Phase;Phase Offset Detection;Phase Offset Estimator;Phase/ Frequency Offset;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;QPSK Receiver;QPSK TX;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;Reference;Repeat;Reset Signal;Reshape;Rx;Scrambler;Selector;Signal From Workspace;Spectrum Baseband [dBFS];Spectrum RX [dBFS];Spectrum TX [dBm];SubSystem;Subsystem;Terminator;Timing Recovery;Unbuffer;ad9371_rx;ad9371_tx;dB Gain;dataIn;u

BLOCKTYPE:
AGC;Buffer;Carrier Synchronizer;Coarse Frequency Compensator;Complex Phase Shift;ComplexToMagnitudeAngle;Concatenate;Constant;ConstellationDiagram;Demux;Descrambler;EnablePort;Gain;Inport;MATLABSystem;Math;Mean;Outport;Phase/Frequency Offset;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;Raised Cosine Receive Filter;Raised Cosine Transmit Filter;Repeat;Reshape;S-Function;SISO Fading Channel;Scrambler;Selector;Signal From Workspace;SpectrumAnalyzer;Symbol Synchronizer;Terminator;Unbuffer;ad9371_rx;ad9371_tx;dB Gain

PRODUCT:
Communications Toolbox;DSP System Toolbox;MATLAB;RF Blockset Models for Analog Devices RF Transceivers;Simulink


MODELNAME: rlCartPoleSimscapeModel
PATH: toolbox/rl/rl/simulink/models/rlCartPoleSimscapeModel.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;5;8;3;1;1;11;4;1;1;1;4;1;3;2;2;1;2;5;1;1
CHECKSUM: 30B46E811A87F497AA636D23C008F988
PRODUCT: Reinforcement Learning Toolbox;Simscape;Simscape Multibody;Simulink
PRODUCT_BASECODE: RL
BLOCK:
Abs;ActionScope;Cart;Compare To Constant;Cos;Disturbance Force;Environment;External Force and Torque;F;Force;Gain;Math Function;Mechanism Configuration;Mux;ObservationScope;PS-Simulink Converter;Pendulum;Plant;Prismatic Joint;RL Agent;Reference;Revolute Joint;RewardScope;Rigid Transform;Saturation;Simulink-PS Converter;Sin;Solver Configuration;SubSystem;Sum;Trigonometric Function;Unit Delay;World Frame;angle;angle_wrap;dF;force;hit limit;is done;observations;qr reward;r;reward;theta;theta_dot;theta_in;theta_out;x;x limit penalty;xdot

BLOCKTYPE:
Abs;Compare To Constant;Constant;External Force and Torque;Gain;Inport;Math;Mechanism Configuration;Mux;Outport;PS-Simulink Converter;Prismatic Joint;RL Agent;Revolute Joint;Rigid Transform;Saturate;Scope;Simulink-PS Converter;Solid;Solver Configuration;Sum;Trigonometry;UnitDelay;World Frame


MODELNAME: rlPusherModel
PATH: toolbox/rl/rl/simulink/models/rlPusherModel.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc. Multi-Agent Pusher Environment
BLOCKTYPE_FREQUENCY: 1;4;3;8;15;1;4;2;9;2;1;3;2;1;14;1;9;3
CHECKSUM: BB4ADC130DEEF42B2474271B9B0E5118
PRODUCT: MATLAB;Reinforcement Learning Toolbox;Simulink
PRODUCT_BASECODE: RL
BLOCK:
 Demux ; SFunction ; Terminator ;Add;AgentA;AgentB;Clock;Constant;Dynamics;Gain;GreaterThanOrEqual;Integrator;IsDone;MATLAB Function;Mux;Observation;Pusher Dynamics;Reference;Reward;Scope;Sqrt;Square;SubSystem;Sum of Elements;Visualization;X;coll;coll ac;coll bc;dX;doPlot;oA;oB;posA;posB;posC;rA;rB;s;t;uA;uB;ua;ub;velA;velB;velC;x;y

BLOCKTYPE:
Clock;Constant;Demux;Gain;Inport;Integrator;Math;Mux;Outport;RL Agent;RelationalOperator;S-Function;Saturate;Scope;Selector;Sqrt;Sum;Terminator


MODELNAME: rlSimplePendulumModel
PATH: toolbox/rl/rl/simulink/models/rlSimplePendulumModel.slx
ANNOTATION: (I + ml^2) theta_ddot = tau - c theta_dot + mgl sin(theta)
BLOCKTYPE_FREQUENCY: 1;1;8;15;3;2;8;1;1;1;1;1;2;1;8;1
CHECKSUM: E237BAD4B6939086A9531390D92D3C99
PRODUCT: MATLAB;Reinforcement Learning Toolbox;Simulink
PRODUCT_BASECODE: RL
BLOCK:
 Demux ; SFunction ; Terminator ; observations;Constant;Gain;I^-;Integrator, Second-Order;L;MATLAB Function;Math Function;Mux;RL Agent;Reference;Saturation;Scope;SubSystem;Sum;Trigonometric Function;Unit Delay;angle_wrap;c;calculate reward;create observations;dtheta;dtheta ;isdone;mgl;observations;pendulum;r;sin/cos;tau;theta;theta ;theta_dot;theta_in;theta_out;u;visualizer;x;y

BLOCKTYPE:
Constant;Demux;Gain;Inport;Math;Mux;Outport;RL Agent;S-Function;Saturate;Scope;SecondOrderIntegrator;Sum;Terminator;Trigonometry;UnitDelay


MODELNAME: rlSimplePendulumModel_bus
PATH: toolbox/rl/rl/simulink/models/rlSimplePendulumModel_bus.slx
ANNOTATION: (I + ml^2) theta_ddot = tau - c theta_dot + mgl sin(theta)
BLOCKTYPE_FREQUENCY: 1;1;1;1;8;11;3;6;1;1;1;1;1;2;1;8;1
CHECKSUM: 81131AA662DDEA71485A28C5AECD5023
PRODUCT: MATLAB;Reinforcement Learning Toolbox;Simulink
PRODUCT_BASECODE: RL
BLOCK:
 Demux ; SFunction ; Terminator ;Bus Creator;Bus Selector;Constant;Gain;I^-;Integrator, Second-Order;L;MATLAB Function;Math Function;RL Agent;Reference;Saturation;Scope;SubSystem;Sum;Trigonometric Function;Unit Delay;angle_wrap;c;calculate reward;create observations;dtheta;isdone;mgl;observations;pendulum;r;tau;theta;theta_dot;theta_in;theta_out;u;visualizer;x;y

BLOCKTYPE:
BusCreator;BusSelector;Constant;Demux;Gain;Inport;Math;Outport;RL Agent;S-Function;Saturate;Scope;SecondOrderIntegrator;Sum;Terminator;Trigonometry;UnitDelay


MODELNAME: ManipulatorPositionControl
PATH: toolbox/robotics/supportpackages/robotlibrary/Examples/ManipulatorPositionControl.slx
BLOCKTYPE_FREQUENCY: 3;2;2;2;2;8;29;3;29;1;8;5;1;1;1;4;5;18;21;2;9;7;38;2;2;7;1;7;2;1;1;1;1
CHECKSUM: 4085121C726E413135102F7AB9CE97B1
PRODUCT_BASECODE: RO_Robot_Lib
ANNOTATION:
Computed Torque Controller  MassMatrix(ddqd - Kd*dqe - Kp*qe)  Velocity Product Torque + Gravity Torque  dqe  qe  Copyright 2021 The MathWorks, Inc. Copyright 2021 The MathWorks, Inc.

BLOCK:
Actuator;Actuator1_AxisInvTransform;Actuator1_AxisTransform;Actuator1_OriginTransform;Actuator2_AxisInvTransform;Actuator2_AxisTransform;Actuator2_OriginTransform;Actuator3_AxisInvTransform;Actuator3_AxisTransform;Actuator3_OriginTransform;Actuator4_AxisInvTransform;Actuator4_AxisTransform;Actuator4_OriginTransform;Actuator5_AxisInvTransform;Actuator5_AxisTransform;Actuator5_OriginTransform;Actuator6_AxisInvTransform;Actuator6_AxisTransform;Actuator6_OriginTransform;Actuator7_AxisInvTransform;Actuator7_AxisTransform;Actuator7_OriginTransform;Add;Applied Torque;Bracelet_Link;Computed Torque Controller;Constant;Coordinate Transformation Conversion;Delay;Desired Configuration;Discrete Derivative;Discrete Filter;EndEffector_Link;Endeffector;Endeffector_OriginTransform;F;ForeArm_Link;From_tau_Actuator;Goto_Q_Actuator;Goto_Qddot_Actuator;Goto_Qdot_Actuator;Gravity Torque;HalfArm1_Link;HalfArm2_Link;Inertia;InertiaOriginTransform;Inverse Kinematics;Joint Space Mass Matrix;Kd;Kp;Measured Configuration;Measured Velocities;MechanismConfiguration;PSS Q_Actuator;PSS Qddot_Actuator;PSS Qdot_Actuator;Product;Q_Actuator;Q_State Mux;Q_out;Qddot_Actuator;Qddot_State Mux;Qddot_out;Qdot_Actuator;Qdot_State Mux;Qdot_out;Reference;ReferenceFrame;Robot;SPS tau_Actuator;Saturation;Scope;Shoulder_Link;Solver Configuration;SubSystem;Terminator;Velocity Product Torque;Visual;VisualOriginTransform;World;Wrist1_Link;Wrist2_Link;base_link;tau_Actuator;tau_Demux;tau_in

BLOCKTYPE:
Constant;Delay;Demux;Discrete Derivative;DiscreteFilter;File Solid;From;Gain;Goto;Gravity Torque;Inertia;Inport;Inverse Kinematics;Joint Space Mass Matrix;Mechanism Configuration;Mux;Outport;PMIOPort;PS-Simulink Converter;Product;Reference Frame;Revolute Joint;Rigid Transform;Saturate;Scope;Simulink-PS Converter;Solver Configuration;Sum;Terminator;Velocity Product Torque;Weld Joint;World Frame;robotics.slcore.internal.block.CoordinateTransformationConversion

PRODUCT:
MATLAB;Robotics System Toolbox;Robotics System Toolbox Robot Library Data;Simscape;Simscape Multibody;Simulink


MODELNAME: ManipulatorTrajectoryPlanning
PATH: toolbox/robotics/supportpackages/robotlibrary/Examples/ManipulatorTrajectoryPlanning.slx
ANNOTATION: Copyright 2021 The MathWorks, Inc. Copyright 2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;4;8;29;29;8;4;1;2;2;18;7;9;7;38;2;7;1;1;1;1
CHECKSUM: 504A9F9E9E955142D3AF8EF1AE42C802
PRODUCT: Robotics System Toolbox Robot Library Data;Simscape;Simscape Multibody;Simulink;UAV Toolbox
PRODUCT_BASECODE: RO_Robot_Lib
BLOCK:
Actuator;Actuator1_AxisInvTransform;Actuator1_AxisTransform;Actuator1_OriginTransform;Actuator2_AxisInvTransform;Actuator2_AxisTransform;Actuator2_OriginTransform;Actuator3_AxisInvTransform;Actuator3_AxisTransform;Actuator3_OriginTransform;Actuator4_AxisInvTransform;Actuator4_AxisTransform;Actuator4_OriginTransform;Actuator5_AxisInvTransform;Actuator5_AxisTransform;Actuator5_OriginTransform;Actuator6_AxisInvTransform;Actuator6_AxisTransform;Actuator6_OriginTransform;Actuator7_AxisInvTransform;Actuator7_AxisTransform;Actuator7_OriginTransform;Bracelet_Link;Clock;EndEffector_Link;Endeffector;Endeffector_OriginTransform;F;ForeArm_Link;From_Q_Actuator;From_Qddot_Actuator;From_Qdot_Actuator;Goto_t_Actuator;HalfArm1_Link;HalfArm2_Link;Inertia;InertiaOriginTransform;MechanismConfiguration;PSS t_Actuator;Q_Actuator;Q_Demux;Q_in;Qddot_Actuator;Qddot_Demux;Qddot_in;Qdot_Actuator;Qdot_Demux;Qdot_in;Reference;ReferenceFrame;Robot;SPS Q_Actuator;Scope;Shoulder_Link;Solver Configuration;SubSystem;Trapezoidal Velocity Profile Trajectory;Visual;VisualOriginTransform;World;Wrist1_Link;Wrist2_Link;base_link;t_Actuator;t_State Mux;t_out

BLOCKTYPE:
Clock;Demux;File Solid;From;Goto;Inertia;Inport;Mechanism Configuration;Mux;Outport;PMIOPort;PS-Simulink Converter;Reference Frame;Revolute Joint;Rigid Transform;Scope;Simulink-PS Converter;Solver Configuration;Weld Joint;World Frame;robotics.slcore.internal.block.TrapVelTrajSys


MODELNAME: slrgex_annotation
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_annotation.slx
CHECKSUM: DE2C438034FBA005C2F59F8E86C0D2D6
PRODUCT: Simulink;Simulink Report Generator
PRODUCT_BASECODE: SR
ANNOTATION:
 Click here to go to MathWorks.com 2. Power factor angle, \phi  1. General relativity is a theory of gravitation developed by Einstein in the years 1907-1915  


MODELNAME: slrgex_f14
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_f14.slx
BLOCKTYPE_FREQUENCY: 1;1;2;13;9;8;1;3;1;8;9
CHECKSUM: 2669C7BCD1A8F452986A3830777983A8
PRODUCT: Simulink;Simulink Report Generator
PRODUCT_BASECODE: SR
ANNOTATION:
Nz pilot calculation Nz = (dq/dt*22.8 + q*Uo - dw/dt)/g F-14 Flight Control Copyright 1990-2014 The MathWorks, Inc.

BLOCK:
Actuator Model;Aircraft Dynamics Model;Alpha-sensor Low-pass Filter;Angle of Attack;Band-Limited White Noise;Constant;Controller;Derivative;Dryden Wind Gust Models;Elevator Command (deg);Elevator Deflection d (deg);Gain;Nz Pilot (g);Nz pilot calculation;Pilot;Pilot G force Scope;Pilot g force (g);Pitch Rate Lead Filter;Pitch Rate q (rad/sec);Product;Proportional plus integral compensator;Q-gust model;Qg;Reference;Rotary Gust qGust (rad/sec);Stick Input;Stick Input (in);Stick Prefilter;SubSystem;Sum;Transfer Fcn.;Vertical Gust wGust (ft/sec);Vertical Velocity w (ft/sec);W-gust model;Wg;alpha (rad);q;q (rad/sec);u;w

BLOCKTYPE:
Band-Limited White Noise.;Constant;Derivative;Gain;Inport;Outport;Product;Scope;SignalGenerator;Sum;TransferFcn


MODELNAME: slrgex_fuelsys
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_fuelsys.slx
BLOCKTYPE_FREQUENCY: 1;1;12;2;5;4;1;1;22;1;4;2;1;16;4;1;2;1;4;1;1;1;1;4;2;5;4;1;1
CHECKSUM: 852724BCE3EBD5498A8E52B644DEFBF7
PRODUCT: Embedded Coder;Simulink;Simulink Report Generator
PRODUCT_BASECODE: SR
EXTERNALFILE_REFERENCE: slrgex_fuelsys_fuel_rate_control___Model_Block___
DESCRIPTION:
This is a model of a fuel control system where Stateflow(R) is used to handle the fault management of the system. The system contains four separate sensors: a throttle sensor, a speed sensor, an oxygen sensor, and a pressure sensor. Each of these sensors is represented by a parallel state in Stateflow. Each parallel state contains two substates, a normal state and a failed state (the exception being the oxygen sensor, which also contains a warmup state). If any of the sensor readings is outside an acceptable range, then a fault is registered in Stateflow, and the substate of the corresponding subsystem transitions to the failed state. If a subsystem recovers, it can transition back to the normal state. The number of failures in the system at any given time is represented in the Fail parallel state. The last parallel state in the Stateflow chart is called Fueling_Mode. This state regulates the oxygen to fuel mixture ratio. If a failure is detected, then the oxygen to fuel ratio is increased. If multiple failures are detected, then the fuel system is disabled until there are no longer multiple failures in the system. 

ANNOTATION:
Inputs Fault Injection Air/Fuel Ratio Fuel (g/s)  Throttle Angle  Engine Speed  EGO  Fault-Tolerant Fuel Control System Dashboard  MAP  Engine Speed (rpm)  Normal Range  Full Range  Update Diagram (Ctrl+D) to bind switches to model workspace variables. Intake Manifold Vacuum Throttle Flow vs. Valve Angle and Pressure Air-Fuel Intake Dynamics This system: - Packs individual sensors into a EngSensors bus signal - Permits bus elements data types to change - Converts signals from continuous to discrete time This system: - Permits upstream signal data type to change - Converts signals from discrete to continuous time Fault-Tolerant Fuel Control System Copyright 1990-2017 The MathWorks, Inc.  Open the Dashboard subsystem to simulate any combination of sensor failures.

BLOCK:
 Demux ; SFunction ; Terminator ;Atmospheric Pressure, Pa (bar);Atmospheric Pressure, Pa (bar) ;Bus Creator;Constant;DTC;Dashboard;Dashboard Scope;EGO Fault Switch;EGO Sensor;Engine Gas Dynamics;Engine Speed;Engine Speed Fault Switch;Engine Speed, N;Engine_Speed_Selector;Gauge;Half Gauge;In;Intake Manifold;Lamp;Limit to Positive;MAP;MAP (bar);MAP Fault Switch;MAP_Selector;MATLAB Function;Manifold Pressure, Pm (bar);Mass Airflow Rate;MinMax;Mixing & Combustion;N (rad/sec);O2_Voltage_Selector;Out;Product;Quarter Gauge;RT/Vm;Rate Transition;Reference;Scope;Sensor Info;Slider Switch;Sonic Flow ;SubSystem;Sum;System Lag;Throttle;Throttle & Manifold;Throttle Ang.;Throttle Angle Fault Switch;Throttle Angle, theta (deg);Throttle Command;Throttle Flow, mdot (g/s);Throttle_Angle_Selector;To Controller;To Plant;Toggle Switch;air flow;air/fuel ratio;direction;ego;engine speed;f(theta);fuel;fuel rate;fuel_rate_control;g(pratio);map;mdot Input (g/s);mdot to Cylinder (g/s);o2_out;p0 = 0.589 bar;sensors;speed;threshold = 0.;throttle;throttle angle;u;y

BLOCKTYPE:
BusCreator;CircularGaugeBlock;Constant;DashboardScope;DataTypeConversion;Demux;DocBlock;Gain;Inport;Integrator;LampBlock;MinMax;ModelReference;Outport;Product;QuarterGaugeBlock;RateTransition;Repeating table;S-Function;Saturate;Scope;SemiCircularGaugeBlock;Signum;SliderSwitchBlock;Sum;Switch;Terminator;ToggleSwitchBlock;Transfer Function with Initial Outputs


MODELNAME: slrgex_fuelsys_fuel_rate_control
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_fuelsys_fuel_rate_control.slx
BLOCKTYPE_FREQUENCY: 3;2;1;8;2;2;3;1;1;1;1;24;1;5;1;1;15;1;4;2;1;1;5;1;1;1;3;1
CHECKSUM: D7CF8B19874422386CBC54969FB5FF41
PRODUCT: Embedded Coder;MATLAB;Simulink;Simulink Report Generator;Stateflow
PRODUCT_BASECODE: SR
ANNOTATION:
Feedforward Control Feedback Control Intake Airflow Estimation and Closed-Loop Correction MAP Estimation Speed Estimation Throttle Estimation Feedforward Fuel Rate Disabled Mode Fuel Mode Low Mode Fuel Mode Rich Mode Fuel Mode Loop Compensation and Filtering Fuel Rate Calculation Verify sample time: aspects of the design assume a 0.01 second sample time. The contents of this subsystem are excluded from the code Simulink Coder generates. To work correctly this system must continue to * Contain no output ports * Enable its Treat as Atomic Unit parameter * Specify its Mask type parameter as VerificationSubsystem Fuel Rate Control Subsystem

BLOCK:
 Demux ; O2_normal; SFunction ;Action Port;Actual Sample Time;Bus Selector;CheckRange;Constant;Data Type Conversion;Demux;Discrete Filter;Discrete Integrator;Enumerated Constant;Expected Sample Time;From;Goto;In;Logic;Merge;Multiport Switch;O2_normal;Oxygen Sensor Switching Threshold;Pressure Estimation;Pressure.map_estimate;Product;Pumping Constant;Ramp Rate Ki;Reference;Relational Operator;Saturation;Speed Estimation;Speed.speed_estimate;SubSystem;Sum;Switch Case;Terminator;Throttle Estimation;Throttle Transient;Throttle.throttle_estimate;airflow_calc;control_logic;disabled_mode;es_i;es_o;est_airflow;f;fb_correction;feedforward_fuel_rate;ff_fuel_rate;fuel_calc;fuel_mode;fuel_rate;hold integrator;low_mode;map;normal;rich;rich_mode;sensors;shutdown;shutoff;speed;switchable_compensation;throttle;validate_sample_time

BLOCKTYPE:
ActionPort;BusSelector;Checks_SRange;Constant;DataTypeConversion;Demux;DiscreteFilter;DiscreteIntegrator;Enumerated Constant;From;Goto;Inport;Logic;Lookup_n-D;Merge;MultiPortSwitch;Outport;Probe;Product;RelationalOperator;S-Function;Saturate;Sum;Switch;SwitchCase;Terminator;TriggerPort;VerificationSubsystem


MODELNAME: slrgex_radar_eml
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_radar_eml.slx
ANNOTATION: Radar Tracking Using MATLAB Function Block Copyright 1990-2014 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;3;3;3;1;3;1;1;6;1;2;1;1;1;1
CHECKSUM: A5C8E1524FC5D3EED0073F6BAD14CD73
PRODUCT: Embedded Coder;MATLAB;Simulink;Simulink Report Generator
PRODUCT_BASECODE: SR
DESCRIPTION:
Radar Tracking Using MATLAB Function Block This example shows how to use an extended Kalman filter with the MATLAB(R) Function block in Simulink(R) to estimate an aircrafts position from radar measurements. The filter implementation is found in the MATLAB Function block, the contents of which are stored in the Simulink model itself. At the end of the simulation, three figures display the following information: the actual trajectory compared to the estimated trajectory; the estimation residual for range; and the actual, measured, and estimated positions. 

BLOCK:
 Demux ; SFunction ; Terminator ;Demux;Est. Position [x, xdot, y, ydot];F;Gain;Gravity;Integrator;MATLAB Function;Meas. noise intensity;Mux;Radar Measurement Noise;Random aircraft motion;Reference;Residuals;Rth;SubSystem;Sum;XY;XY Acceleration Model;XY to Range-Bearing;XYPosition;XYVelocity;ZOH;a;bearing;meas;range;residual;xhatOut

BLOCKTYPE:
Band-Limited White Noise.;Demux;Gain;Inport;InportShadow;Integrator;Math;Mux;Outport;S-Function;Sum;Terminator;Trigonometry;ZeroOrderHold;xy2rtheta


MODELNAME: slrgex_sf_car
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_sf_car.slx
BLOCKTYPE_FREQUENCY: 3;2;6;18;2;5;1;14;6;3;2;1;1;3;2;1;1;1
CHECKSUM: 263CA7A42C4E7BE85A3F5091FC71C9D2
PRODUCT: Simulink;Simulink Report Generator;Stateflow
PRODUCT_BASECODE: SR
ANNOTATION:
Vehicle TORQUE CONVERTER Double-click to open the UI and select an input maneuver  Copyright 1997-2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ; gear;Engine;Integrator;K factor;Look-Up;Look-Up Table;Mux;Ne;Nin;Nout;Product;Reference;Scope;Sign;SubSystem;Sum;Ti;Tin;Torque Converter;Torque ratio;Tout;Tt;User Inputs;Vehicle;brake torque;down_th;engine + impeller inertia;engine torque;f;final drive ratio;gear;impeller;interp_down;interp_up;linear speed;mph;out;quotient;road load;selection_state.calc_th;shift_logic;signed load;speed;speed ratio;throttle;transmission;transmission output speed;transmission output torque;transmission ratio;turbine;up_th;vehicle inertia;vehicle speed;wheel speed

BLOCKTYPE:
Demux;Fcn;Gain;Inport;Integrator;Lookup_n-D;Mux;Outport;Product;S-Function;Scope;SignalEditor;Signum;Sum;Terminator;TriggerPort;torque converter;vehicle model


MODELNAME: slrgex_sf_climate_control
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_sf_climate_control.slx
BLOCKTYPE: Constant;Demux;Gain;Inport;Outport;S-Function;Scope;Sin;Slider Gain;Sum;Switch;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 12;1;2;11;10;1;2;2;2;6;5;1;2
CHECKSUM: DA51BE49382B8120AB8A72E6337FD110
PRODUCT: Simulink;Simulink Report Generator;Stateflow
PRODUCT_BASECODE: SR
ANNOTATION:
Cooler when on produces -1 unit of heat per time step and -0.5 unit of humidity Cooler when on produces -1 unit of heat per time step and -0.5 unit of humidity Humidifier when on produces 1 unit of humidity per time step Subsystem to calculate heat flow into the house based on house temperature and outside temperature heatFlow = heatCoeff * (externalTemp - roomTemperature) Subsystem to calculate heat flow into the house based on house temperature and outside temperature heatFlow = heatCoeff * (externalTemp - roomTemperature) Home climate (temperature and humidity) controller using Truth Table  Copyright 2005-2013 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;C;ClimateController;Constant;Cooler;H_thresh;Heater;Humidifier;HumidityScope;In;Reference;SubSystem;Switch;T_thresh;addh;addt;cooler;desiredHumidity;desiredTemp;dh;dt;externalHeatFlow;externalHumid;externalHumidityFlow;externalTemp;h;heatCoeff;heatFlow;heater;humidAccumulate;humidCoeff;humidDiff;humidFlow;humidifier;humidity;roomHumid;roomTemp;t;tempAccumulate;tempDiff;temperature;temperatureScope


MODELNAME: slrgex_slexLawOfLargeNumbersExample
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_slexLawOfLargeNumbersExample.slx
BLOCKTYPE: Compare To Constant;Display;EnablePort;MATLABSystem;Outport;Terminator;UniformRandomNumber
BLOCKTYPE_FREQUENCY: 1;4;1;3;2;1;1
CHECKSUM: 0A7BF3C48F39B23215C9DB7302BF4EEE
PRODUCT: MATLAB;Simulink;Simulink Report Generator
PRODUCT_BASECODE: SR
DESCRIPTION:
Illustration of Law of Large Numbers This example shows how to use MATLAB System blocks to illustrate the law of large numbers. The law of large numbers states that the cumulative average probability of an event approaches the expected value as the number of trials approaches infinity. You can see this in the generated plot. A Uniform Random Number block connected to Compare To Constant block acts as a Bernoulli trial. The example uses the high value as successful outcome of the experiment. This example highlights the use of MATLAB System block as follows: * The Success Counter counts the number of successful trials. The Total Trials Counter counts the total number of trials. Both blocks use the same System object(TM). This System object is a source block that uses the resetImpl method to count the number of times the block has run at consecutive time steps. * The Analysis and Plot block calculates the average probability and plots it. It uses a System object that inherits from the interface classes matlab.System. The interface class matlab.System is required for all System objects. To use features not supported for code generation, such as unsupported functions, define propagator methods for the System object. As a result, this block cannot simulate in Code generation mode. It must simulate in Interpreted execution mode. * The two MATLAB System blocks use custom icons. The Analysis and Plot block uses an image file icon. The Total Trials Counter block uses a multiline text icon. The getIconImpl methods of the corresponding System objects define these custom icons. 

ANNOTATION:
    Copyright 2013 The Mathworks, Inc.   MATLAB System Block Example: Illustration of Law of Large Numbers   

BLOCK:
Analysis and Plot;Compare To Constant;Cumulative Probability Calculation;Enable;Experiment;More Info;Number of times called consecutively;Out;Reference;SubSystem;Success Counter;Successful Trials;Successful Trials Counter;Terminator;Total Trials;Total Trials Counter;Uniform Random Number


MODELNAME: slrgex_sltestTestSequenceDebouncerExample
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_sltestTestSequenceDebouncerExample.slx
DESCRIPTION: Modeling and testing a simple debouncer using the Test Sequence block
BLOCK: Demux ; SFunction ; Terminator ;Debouncer_Logic;Debouncer_Test;Scope;SubSystem;Unit Delay;u;y
BLOCKTYPE: Demux;Inport;Outport;S-Function;Scope;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 2;2;2;2;1;2;1
CHECKSUM: DFA632972EDAA5F7F12BE9F314D4422B
PRODUCT: Simulink;Simulink Report Generator;Simulink Test
PRODUCT_BASECODE: SR
ANNOTATION:
 Modeling and Testing a Simple Debouncer  This example demonstrates the multiple uses of the Test Sequence block: 1. A complex test sequence with sub-steps to test a debouncer 2. Debouncer logic implemented using the duration() keyword 3. Asessment block to ensure that the debouncer logic actually worked Copyright 2015 The MathWorks, Inc.


MODELNAME: slrgex_stt_boiler
PATH: toolbox/rptgenext/rptgenextdemos/slrgex_stt_boiler.slx
BLOCKTYPE_FREQUENCY: 6;2;1;2;8;1;5;1;1;1;1;1;1;1
CHECKSUM: 3BFAF85E709DAB05611ABCA21BEA1A54
PRODUCT: Embedded Coder;Simulink;Simulink Report Generator;Stateflow
PRODUCT_BASECODE: SR
ANNOTATION:
This subsystem models a typical 8-bit analog-to-digital converter having an input range of 0-5 volts This subsystem models a digital thermometer composed of a simple temperature sensor and an ADC. The transfer function of the sensor is: V = .05 * T + 0.75 for T in degrees C. The conversion block inverts the combined transfer function of the sensor and ADC so that the output is an sfix(8) code representing T in degrees C. Copyright 2018-2021 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC;ALARM;Boiler Plant model;CLEAR;Data Type Conversion;Gain;HIGH;Integrator;LOW;Linear fixed point conversion;Scope;State Transition Table;SubSystem;Switch;actual temp;boiler_cmd;cooling rate;digital temp;digital thermometer;heating rate;limit;on/off;pcm;quantize;reference_high;reference_low;scale;sensor;temp;voltage

BLOCKTYPE:
Constant;DataTypeConversion;Demux;Gain;Inport;Integrator;Outport;Polyval;Quantizer;S-Function;Saturate;Scope;Switch;Terminator


MODELNAME: ctrlKalmanNavigationExample
PATH: toolbox/shared/controllib/engine/blocks/ctrlKalmanNavigationExample.slx
ANNOTATION: Copyright 2014 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;1;3;1;1;2;8;8;4;3;1;8;10;2;5;2;1;1;1;5;5;3;1;1
CHECKSUM: AA3EEAA9805020E14C02ECF9F6BFDF73
PRODUCT: Simulink;System Identification Toolbox
PRODUCT_BASECODE: CT;ID
BLOCK:
1/VehicleMass [1/kg];AvoidDivisionByZero;Band-Limited White Noise East Position Measurement;Band-Limited White Noise North Position Measurement;Constant;CurrentOrientation;CurrentVelocities;Demux;DesiredOrientation;DesiredSpeed;Digital Clock;Divide;EnginePower [W];From Workspace Desired Orientation;From Workspace Desired Speed;Gain;Integrator - xe;Integrator- xn;IntegratorOrientation;Integratorx - v;Kalman Filter;Math Function;Math Function [ve^2; vn^2];Matrix Concatenate;MeasurementNoise;MinMax;Mux;Noise;Orientation [deg];PI Controller Orientation;PI Controller Speed;Product;Q;Reference;Saturation;Scope;Selector;Speed And Orientation Tracking;Sqrt;SteeringAngle [deg] ;SteeringCmd;SubSystem;Subtract;Sum;Sum of Elements ve^2+vn^;ThrottleCmd;ThrottlePosition [-];Time-Varying Process Noise Covariance;To Workspace - Error Covariance;To Workspace - Estimated States;To Workspace - Measurements;To Workspace - Time;To Workspace - True States;Trigonometric Function;Vehicle Model;Zero-Order Hold;deg2rad;rad2deg;u;ve [m/s];vn [m/s];xe [m];xhat;xn [m];y

BLOCKTYPE:
Band-Limited White Noise.;Concatenate;Constant;Demux;DigitalClock;FromWorkspace;Gain;Inport;Integrator;Math;MinMax;Mux;Outport;PID 1dof;Product;Saturate;Scope;Selector;Sqrt;Sum;ToWorkspace;Trigonometry;ZeroOrderHold;ctrlKalmanFilter


MODELNAME: focZynqArmDeployment
PATH: toolbox/shared/hdlmotorcontrol/MotorControl/FocZynq/focZynqArmDeployment.slx
BLOCKTYPE_FREQUENCY: 1;2;1;3;1;5;4;1;1;2;1;2;1;1;1;1;1;1;1;1;1
CHECKSUM: F660C41908ADC4AB437A30AA68D609F3
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: focZynqC___Model_Block___
ANNOTATION:
Enum Data Type Conversion Field-Oriented Control of Velocity Zynq ARM Deployment for Trenz Motor Control Kit Copyright 2015-2020 The MathWorks, Inc.

BLOCK:
AXI_Interface;Algorithm_C;Bus_Creator;Bus_Selector;Command_Mode;Constant;Data Type Conversion;Data_Type_Int;Delay;Demux;Display;Enum_Data_Type;Enum_Data_Type_Conversion;In;Input_Source;Int32_Data_Type;Manual_Switch;Motor_On_Switch;Mux;Out;Reference;Scope;Select_Source;Signal_Builder_Experiments;Sine Wave;Slider_Gain;SubSystem;Terminator

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;BusCreator;BusSelector;Constant;Convert to enumerated data type;DataTypeConversion;Delay;Demux;Display;Enumerated Constant;Inport;ManualSwitch;ModelReference;MultiPortSwitch;Mux;Outport;Scope;SignalEditor;Sin;Slider Gain;Terminator


MODELNAME: focZynqC
PATH: toolbox/shared/hdlmotorcontrol/MotorControl/FocZynq/focZynqC.slx
BLOCKTYPE_FREQUENCY: 2;1;25;5;11;1;4;1;9;1;37;5;7;1;1;35;6;8;1;1;5;18;12;1;1;2
CHECKSUM: 7A3709F7277DD06AD6DC119F543E37D4
PRODUCT: Embedded Coder;Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
Count To Limit Negate Zero To Two Pi Wrap Neg Pi To Pi Once Encoder Calibration Calibrate Encoder Offset Mod Two Pi Once Electrical Velocity To Position Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Detect Change Set Acceleration Ramp Velocity Rotor Velocity To Volts Open Loop Velocity Control Open Loop Velocity Control Disabled Velocity Control Velocity Control Copyright 2015-2024 The MathWorks, Inc. Field-Oriented Control of Velocity Zynq C Specification

BLOCK:
 Demux ; SFunction ; Terminator ; calibrateEncoder; closedLoop; enableInverter; openLoop;A;ABC;AND_Neg;AND_Pos;Abs;Acceleration;Add;Alpha;At_Limit;Beta;Calibrate_Encoder_Offset;Command_Type;Command_Velocity;Constant;Continue_Count;Cos_Coefficient;Count_To_Limit;Current;Current_Command;Current_Fixed_Point;D;Delay;Detect_Change;Difference;Direct_Voltage;Duration;EP;EV;Electrical_Velocity;Electrical_Velocity_To_Position;En_Closed_Loop;En_Inverter;Enable;Encoder_Calibration;Encoder_Index_Found;Encoder_Offset;Error;Frequency_To_Voltage;From;Gain;Goto;Greater_Or_Equal;Greater_Than;In;Input_Range;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Latch_Target;Less_Than;Limit;Logical_OR;Max_Abs_Error;Merge;Mod_Two_Pi_Once;Mod_X_Two_Pi;Mode_Scheduler;Mode_Scheduler_State;Motor_On;Mux;NOT;Neg_Pi;Negate_Zero_To_Two_Pi;Not_Equal;Not_Equal_Zero;Number_Of_Pole_Pairs;OR;Offset_Fixed_Point;Open_Loop_Velocity_Control;Out;Output_Range;PI;Phase Voltage;Phase_Voltage;Phase_Voltage_Amplitude;Position;Position_At_Zero_Count;Position_At_Zero_Count_Valid;Position_Single;Position_Valid;Product;Proportional_Gain;Q;Q_Current_Command;RV;Ramp_Velocity;Reference;Reset;Reset_Count;Rotor_Position;Rotor_Velocity;Rotor_Velocity_To_Volts;Sample_Frequency;Sample_Time;Saturate_Magnitude;Saturate_Output;Set_Acceleration;Sin_Coefficient;Sine_Cosine;StandBy;Stop_Count;SubSystem;Subtract;Sum;Switch;Switch_Dir;Switch_Stop;Two_Pi;Unary_Minus;V;V_Current;V_Target;Velocity_Command;Velocity_Control;Velocity_Measured;Velocity_Single;Voltage_Bias;Voltage_Fixed_Point;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Y;Zero;Zero_During_Calibration;commandType;encoderIndexFound;encoderOffsetFound;error;mode;motorOn

BLOCKTYPE:
Abs;Compare To Zero;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Logic;Merge;Mux;Outport;Product;RelationalOperator;S-Function;Saturation Dynamic;SignalSpecification;Sum;Switch;Terminator;Trigonometry;UnaryMinus


MODELNAME: focZynqHdl
PATH: toolbox/shared/hdlmotorcontrol/MotorControl/FocZynq/focZynqHdl.slx
BLOCKTYPE_FREQUENCY: 1;2;39;15;31;5;1;21;106;19;7;4;4;70;25;9;1;2;6;4;4;5;1;38;14;2;1;4
CHECKSUM: BF11C9FEE6065DDAAEF46FF896E728E3
PRODUCT: Embedded Coder;Fixed-Point Designer;Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Count to Current Mod Two Pi Once Encoder Count To Rotor Position Wrap Neg Pi To Pi Once Rotor Position Delta If detect positive rise in valid, this is a bad sample since encoder index just reset First two velocity calculations are not valid If offset changes, this is a bad sample since the encoder was calibrated to a new value Rotor Position Delta To Velocity Rotor To Electrical Position  Fixed-point implementation which avoids overflow Encoder To Position And Velocity Clarke Transform Converts balanced three-phase quantities into balanced two-phase quantities. The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component. The alpha and beta components are still dependent on time and speed. Delay With Reset D Current Control Delay With Reset Q Current Control DQ Current Control Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Park Transform Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame. Sine Cosine Fixed Point LUT Space Vector Modulation FOC Current Control Clarke Transform Converts balanced three-phase quantities into balanced two-phase quantities. The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component. The alpha and beta components are still dependent on time and speed. D Current Control Q Current Control DQ Current Control Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Park Transform Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame. Space Vector Modulation FOC Current Control  FOC Encoder Current Loop current control floating-point algorithm Over Current Detector Voltage To PWM Compare FOC Encoder Current Loop Field-Oriented Control of Velocity Zynq HDL Specification Copyright 2015-20120 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;A;ABC;ABC_SVM;ADC_Count_To_Current;ADC_Phase_Currents;AND;AXI_Current_Command;AXI_Electrical_Position;AXI_Enable_Closed_Loop;AXI_Enable_Inverter;AXI_Encoder_Index_Found;AXI_Encoder_Offset;AXI_Overcurrent_Error;AXI_Phase_Current_A;AXI_Phase_Current_B;AXI_Phase_Voltage_A;AXI_Phase_Voltage_B;AXI_Phase_Voltage_C;AXI_Rotor_Position;AXI_Rotor_Velocity;Abs;Add;Alpha;Alpha_Gain;B;Beta;Beta_Gain;Bias;Bias_To_Remove;Clarke_Transform;Compare;Constant;Cos;Cos_Coefficient;Count;Current;Current_Command;Current_Measured;D;DQ_Current_Control;D_Command;D_Current;D_Current_Control;D_Voltage;Data Type Conversion;Data_Type_Conversion;Data_Type_Convert;Delay;Demux;Detect_Change;Detect_Over_Current_Error;Detect_Rise;E;Electrical_Position;En_Inv;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Count_To_Rotor_Position;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Offset;Encoder_To_Position_And_Velocity;Error;Extract_Lower_Bits;FOC_Current_Control;FOC_Velocity_Encoder;FloatingPoint_FOC_Control;Gain;Greater_Than;IP_ADC_A_Count;IP_ADC_B_Count;IP_Encoder_A_Leads_B;IP_Encoder_Count;IP_Encoder_Count_Per_Revolution;IP_Encoder_Index_Found;IP_Inverter_Enable;IP_PWM_A_Compare;IP_PWM_B_Compare;IP_PWM_C_Compare;IP_PWM_Counter_Max;IP_PWM_Dead_Time_Count;In;Index_Found;Input_Range;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Last_Valid_Position_Delta;Less_Than;Logical Operator;Logical_AND;Max;Min;Mod_Two_Pi_Once;Mod_X_Two_Pi;Motor_On;Mux;NOT;Neg_Pi;No_Change_Detected;No_Rise_Detected;Normalize;Normalize_Position;Not_Equal;Offset;Out;Output_Range;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;P;PI;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;Park_Transform;Phase_Current;Phase_Currents;Phase_Voltage;Phase_Voltage_Command;Pole_Pair_Gain;Position;Position_At_Zero_Count;Position_Delta;Product;Proportional_Gain;Q;Q_Command;Q_Current;Q_Current_Control;Q_Voltage;R;Reference;Register;Reset;Rotor_Position;Rotor_Position_Delta;Rotor_Position_Delta_To_Velocity;Rotor_Position_Per_Count;Rotor_To_Electrical_Position_No_Overflow_Fixpt;Rotor_Velocity;Sample_Time;Sat;Saturate;Saturate_Magnitude;Saturate_Output;Saturation;Scalar;Scale_To_Two_Pi;Signed_Fixpt;Sin;Sin_Coefficient;Sine_Cosine;Sine_Cosine_LUT;Slope;Space_Vector_Modulation;SubSystem;Subtract;Switch;Tick_Per_Sec;Trigonometric Function;Two_Pi;Unary_Minus;Unsigned_Fixpt;Unsigned_Integer;Velocity;Voltage;Voltage_To_PWM_Compare;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Zero;enableOverCurrentDetect;error;overCurrentDurationTicks;overCurrentLimit;phaseCurrentA;phaseCurrentB;positionDelta;rotorVelocity

BLOCKTYPE:
Abs;Bitwise Operator;Constant;DataTypeConversion;Delay;Demux;Detect Change;Gain;Inport;InportShadow;Logic;MinMax;Mux;Outport;Product;RelationalOperator;Rotor position delta to velocity;S-Function;Saturate;Saturation Dynamic;Selector;SignalSpecification;Sine and Cosine;Sum;Switch;Terminator;Trigonometry;UnaryMinus


MODELNAME: focZynqTestBench
PATH: toolbox/shared/hdlmotorcontrol/MotorControl/FocZynq/focZynqTestBench.slx
BLOCKTYPE_FREQUENCY: 3;9;1;1;11;4;4;16;2;3;13;4;24;1;1;1;9
CHECKSUM: 50E7C8D715BAD4B9CD5949D4AE8DA040
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: focZynqC___Model_Block___focZynqHdl___Model_Block___
ANNOTATION:
Continuous To Discrete Controller Algorithm Discrete To Continuous Enum Data Type Conversion System Inputs Three Phase Equivalent DC Current Verify Outputs Field-Oriented Control of Velocity Hardware/Software Test Bench Copyright 2015-2020 The MathWorks, Inc.

BLOCK:
ADC_Count;Algorithm_C;Algorithm_HDL;Bus_Creator;Bus_Selector;Command_Type;Continuous_To_Discrete;Controller_Algorithm;Controller_Mode;Current_DC;Data_Type_Conversion;Delay;Demux;Discrete_To_Continuous;Encoder_Count;Encoder_Index_Found;Enum_Data_Type;Enum_Data_Type_Conversion;Iabc;Idc;In;Int32_Data_Type;Inverter_Enable;Motor_And_Load;Motor_Commands;Motor_Measurements;Motor_On;Mux;Out;PWM_Compare;Power_A;Power_ABC;Power_B;Power_C;RT;Rate_Transition;Reference;Signal_Builder_Experiments;SubSystem;System_Inputs;System_Measurements;System_Response;Terminator;Three_Phase_Equivalent_DC_Current;Vabc;Velocity_Command;Verify_Outputs;Voltage_DC

BLOCKTYPE:
BusCreator;BusSelector;Constant;Convert to enumerated data type;DataTypeConversion;Delay;Demux;Inport;ModelReference;Mux;Outport;Product;RateTransition;Scope;SignalEditor;Sum;Terminator


MODELNAME: PEZynqArmDeployment
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/PEZynqArmDeployment.slx
BLOCKTYPE_FREQUENCY: 1;1;9;2;1;1;1;1;1;1;2;6
CHECKSUM: 0E3AF51F2CF83AFFCF584F9D875EFE31
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: PEZynqC.slx___Model_Block___
ANNOTATION:
 Rs (ohm) Parameter Estimation Zynq ARM Deployment for Trenz Motor Control Kit  Copyright 2023 The MathWorks, Inc.  Ld (H)  Lq (H)  Ke (Vpk_LL/krpm)   J (Kgm^2)   B (N m s)

BLOCK:
AXI_Interface;Algorithm_C;Data Type Conversion;Delay;Demux;Estimated Parameters;Mux;Reference;Status;Terminator;TestConfiguration;TestEnable;To Workspace

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;DataTypeConversion;Delay;Demux;Display;ModelReference;Mux;PMSM Parameter Estimation Configurator;Scope;Step;Terminator;ToWorkspace


MODELNAME: PEZynqC
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/PEZynqC.slx
BLOCKTYPE_FREQUENCY: 2;18;5;10;13;6;3;8;27;3;19;50;6;1;2;1;2;4;49;1;1;2;5;3
CHECKSUM: 8FF72FEA03A26C99A5016B29538C0AE3
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Calibration Param Est Disabled  Copyright 2023 The MathWorks, Inc. Parameter Estimation of PMSM Processor Specification 

BLOCK:
; ; Demux ; PE; SFunction ; Terminator ; enableInverter;ADCCaFlag;ADCCounts;ADCOffsetPhA;ADCOffsetPhB;ADCOffsets;ADC_Calibration;ADC_Counts_Ph_A;ADC_Counts_Ph_B;AND;ActiveTest;B;Bus Creator;Bus Selector;Compare To Constant;Config;Constant;Conver;Current_Command;Current_Fixed_Point;Data Type Conversion;DebugData;DebugSignals;Delay;Demux;EnCalibration;EnPrev;En_Closed_Loop;En_Inverter;Enable;Encoder_Index_Found;Encoder_Offset;Error;Flag;From;Gain;Goto;HWInpust;HWInputs;Init;InverterEn;J;Ke;LDStatus;Ld;Ld Estimator;LdLog;LdStatus;LdTest;Log;Lq;Lq Estimator;LqLog;LqStatus;LqTest;MATLAB Function;MechLog;MechParam;MechStatus;Mechanical Parameter Estimator;Merge;MotorParam;MotorParams;Mux;NOT;Offset_Fixed_Point;Out;PE;PU Converstion;Phase Voltage;PhaseCurrentA;PhaseCurrentB;PhaseCurrentC;Phase_Voltage;RadPersec to rpm;Reference;Rotor_Position;Rotor_Position_elec;Rotor_Velocity;Rs;Rs Estimator;RsLog;RsStatus;RsTest;Samples;StandBy;StartEst;SubSystem;Terminator;Test Selection;TestConfig;TestEnable;TestNum;Test_State;Testnum;Ts;Unit Delay;Vabc;Velocity_Single;Voltage_Fixed_Point;adcCalibration;adcCalibrationStatus;error;mode

BLOCKTYPE:
BusCreator;BusSelector;Compare To Constant;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Ld Estimator;Logic;Lq Estimator;Merge;Mux;Outport;PMSM Mechanical Parameter Estimator;Rs Estimator;S-Function;Terminator;UnitDelay


MODELNAME: PEZynqCElecEst
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/PEZynqCElecEst.slx
BLOCKTYPE_FREQUENCY: 2;17;5;10;13;5;3;8;26;3;18;49;6;1;2;1;2;4;48;1;1;2;5;3
CHECKSUM: 0C4A965495D0916B1BD74973D169934E
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Calibration Param Est Disabled  Copyright 2023 The MathWorks, Inc. Parameter Estimation of PMSM Processor Specification 

BLOCK:
; ; Demux ; PE; SFunction ; Terminator ; enableInverter;ADCCaFlag;ADCCounts;ADCOffsetPhA;ADCOffsetPhB;ADCOffsets;ADC_Calibration;ADC_Counts_Ph_A;ADC_Counts_Ph_B;AND;ActiveTest;B;Bus Creator;Bus Selector;Compare To Constant;Config;Constant;Conver;Current_Command;Current_Fixed_Point;Data Type Conversion;DebugData;DebugSignals;Delay;Demux;EnCalibration;EnPrev;En_Closed_Loop;En_Inverter;Enable;Encoder_Index_Found;Encoder_Offset;Error;Flag;From;Gain;Goto;HWInpust;HWInputs;Init;InverterEn;J;Ke;LDStatus;Ld;Ld Estimator;LdLog;LdStatus;LdTest;Log;Lq;Lq Estimator;LqLog;LqStatus;LqTest;MATLAB Function;MechLog;MechParam;Mechanical Parameter Estimator;Merge;MotorParam;MotorParams;Mux;NOT;Offset_Fixed_Point;Out;PE;PU Converstion;Phase Voltage;PhaseCurrentA;PhaseCurrentB;PhaseCurrentC;Phase_Voltage;RadPersec to rpm;Reference;Rotor_Position;Rotor_Position_elec;Rotor_Velocity;Rs;Rs Estimator;RsLog;RsStatus;RsTest;Samples;StandBy;StartEst;SubSystem;Terminator;Test Selection;TestConfig;TestEnable;TestNum;Test_State;Testnum;Ts;Unit Delay;Vabc;Velocity_Single;Voltage_Fixed_Point;adcCalibration;adcCalibrationStatus;error;mode

BLOCKTYPE:
BusCreator;BusSelector;Compare To Constant;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Ld Estimator;Logic;Lq Estimator;Merge;Mux;Outport;PMSM Mechanical Parameter Estimator;Rs Estimator;S-Function;Terminator;UnitDelay


MODELNAME: PEZynqCMechEst
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/PEZynqCMechEst.slx
BLOCKTYPE_FREQUENCY: 2;2;6;2;1;34;14;13;4;7;11;13;10;55;5;8;1;2;6;60;1;4;7;2;5;15;11;3;1;1;2
CHECKSUM: 41DC48F0F35F0C060B3FAFDA401CE46C
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Calibration Count To Limit Negate Zero To Two Pi Wrap Neg Pi To Pi Once Encoder Calibration Calibrate Encoder Offset Mod Two Pi Once Electrical Velocity To Position Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Detect Change Set Acceleration Ramp Velocity Rotor Velocity To Volts Open Loop Velocity Control Open Loop Velocity Control Param Est Disabled  Copyright 2023 The MathWorks, Inc. Parameter Estimation of PMSM Processor Specification 

BLOCK:
; ; Calibrate_Encoder_Offset; Demux ; Open_Loop; PE; SFunction ; Terminator ; enableInverter;A;ABC;ADCCaFlag;ADCCounts;ADCOffsetPhA;ADCOffsetPhB;ADCOffsets;ADC_Calibration;ADC_Counts_Ph_A;ADC_Counts_Ph_B;AND;AND_Neg;AND_Pos;Abs;Acceleration;ActiveTest;Add;Alpha;At_Limit;B;Beta;Bus Creator;Bus Selector;Calibrate_Encoder_Offset;Compare To Constant;Config;Constant;Continue_Count;Conver;Cos_Coefficient;Count_To_Limit;Current_Command;Current_Fixed_Point;D;Data Type Conversion;DebugData;DebugSignals;Delay;Demux;Detect_Change;Difference;Direct_Voltage;Duration;EP;EV;Electrical_Velocity;Electrical_Velocity_To_Position;EnCalibration;EnPrev;En_Closed_Loop;En_Inverter;Enable;Encoder_Calibration;Encoder_Index_Found;Encoder_Offset;Error;Flag;Frequency_To_Voltage;From;Gain;Goto;Greater_Or_Equal;Greater_Than;HWInpust;HWInputs;In;Init;Input_Range;Inverse_Clarke_Transform;Inverse_Park_Transform;InverterEn;J;Ke;Latch_Target;Less_Than;Limit;Log;Logical_OR;MATLAB Function;Manual Switch;Max_Abs_Error;MechLog;MechParam;MechStatus;Mechanical Parameter Estimator;Merge;Mod_Two_Pi_Once;Mod_X_Two_Pi;MotorParam;MotorParams;MotorParamsRsLd;Mux;NOT;Neg_Pi;Negate_Zero_To_Two_Pi;Not_Equal_Zero;Number_Of_Pole_Pairs;OR;Offset_Fixed_Point;Open_Loop_Velocity_Control;Out;Output_Range;PE;PI;PU Converstion;Phase Voltage;PhaseCurrentA;PhaseCurrentB;PhaseCurrentC;Phase_Voltage;Phase_Voltage_Amplitude;Position;Position_At_Zero_Count;Position_At_Zero_Count_Valid;Position_Valid;Product;Q;RV;RadPersec to rpm;Ramp_Velocity;Reference;Reset;Reset_Count;Rotor_Position;Rotor_Position_elec;Rotor_Velocity;Rotor_Velocity_To_Volts;Sample_Frequency;Samples;Set_Acceleration;Sin_Coefficient;Sine_Cosine;StandBy;StartEst;Stop_Count;SubSystem;Subtract;Sum;Switch;Switch_Dir;Switch_Stop;Terminator;Test Selection;TestConfig;TestEnable;TestNum;Test_State;Testnum;Ts;Two_Pi;Unary_Minus;Unit Delay;V;V_Current;V_Target;Vabc;Velocity_Command;Velocity_Single;Voltage_Bias;Voltage_Fixed_Point;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Y;Zero;Zero_During_Calibration;adcCalibration;adcCalibrationStatus;encoderIndexFound;encoderOffsetFound;error;mode

BLOCKTYPE:
Abs;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Logic;ManualSwitch;Merge;Mux;Outport;PMSM Mechanical Parameter Estimator;Product;RelationalOperator;S-Function;SignalSpecification;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitDelay


MODELNAME: PEZynqHdl
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/PEZynqHdl.slx
BLOCKTYPE_FREQUENCY: 1;10;1;30;5;1;5;39;2;6;1;3;36;1;1;1;1;2;1;2;1;3
CHECKSUM: 34636470D7F34D95F84CBFEF6A605A54
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Count to Current If offset changes, this is a bad sample since the encoder was calibrated to a new value First two velocity calculations are not valid If detect positive rise in valid, this is a bad sample since encoder index just reset Rotor Position Delta Encoder To Position And Velocity Over Current Detector Voltage To PWM Compare  PMSM Parameter Estimation Zynq HDL Specification Copyright 2015-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC_Count_To_Current;ADC_Counts;ADC_Offset_PhA;ADC_Offset_PhB;ADC_Offsets;ADC_Phase_Currents;AND;AXI_ADC_Counts_phA;AXI_ADC_Counts_phB;AXI_ADC_Offset_PhA;AXI_ADC_Offset_PhB;AXI_Current_Command;AXI_Electrical_Position;AXI_Enable_Closed_Loop;AXI_Enable_Inverter;AXI_Encoder_Index_Found;AXI_Encoder_Offset;AXI_Overcurrent_Error;AXI_Phase_Current_A;AXI_Phase_Current_B;AXI_Phase_Voltage_A;AXI_Phase_Voltage_B;AXI_Phase_Voltage_C;AXI_Rotor_Position;AXI_Rotor_Velocity;Abs;Add;Bias;Compare;Constant;Count;Current;Current_Command;Data_Type_Convert;Delay;Demux;Detect_Change;Detect_Over_Current_Error;Detect_Rise;Electrical_Position;En_Inv;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Offset;Encoder_To_Position_And_Velocity;Error;Gain;IP_ADC_A_Count;IP_ADC_B_Count;IP_Encoder_A_Leads_B;IP_Encoder_Count;IP_Encoder_Count_Per_Revolution;IP_Encoder_Index_Found;IP_Inverter_Enable;IP_PWM_A_Compare;IP_PWM_B_Compare;IP_PWM_C_Compare;IP_PWM_Counter_Max;IP_PWM_Dead_Time_Count;Index_Found;Last_Valid_Position;Logical_AND;Mechanical to Electrical Position;Motor_On;Mux;NOT;No_Change_Detected;No_Rise_Detected;Offset;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;PE;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;Phase_Current;Phase_Currents;Phase_Voltage_Command;Position_Delta;Product;Quadrature Decoder;Reference;Register;Rotor_Position;Rotor_Position_Valid;Rotor_Velocity;Sat;Saturation;Scalar;Slope;Speed Measurement;SubSystem;Switch;Terminator;Voltage;Voltage_To_PWM_Compare;enableOverCurrentDetect;error;overCurrentDurationTicks;overCurrentLimit;phaseCurrentA;phaseCurrentB

BLOCKTYPE:
Abs;Constant;DataTypeConversion;Delay;Demux;Detect Change;Gain;Inport;InportShadow;Logic;Mechanical to Electrical Position;Mux;Outport;Product;Quadrature Decoder;RelationalOperator;S-Function;Saturate;Speed Measurement;Sum;Switch;Terminator


MODELNAME: PEZynqTestBench
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/PEZynqTestBench.slx
BLOCKTYPE_FREQUENCY: 1;2;6;10;16;2;5;1;5;25;2;2;2;2;4;22;1;1;37;1;1;1;2;4;3;8
CHECKSUM: 49E7B7DAA0FDEB1E948A107C57C59DD6
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: PEZynqC.slx___Model_Block___PEZynqHdl.slx___Model_Block___
ANNOTATION:
Continuous To Discrete Controller Algorithm Discrete To Continuous  Note: The PMSM block does not simulate magentic effects of the rotor when Vd is applied. In order to simulate locking of the rotor at zero position, PMSM block is used in zero speed input during Rs, Ld and Lq estimation. Do not use simulation to determine the Vd value required to align the rotor at zero position. Scaling Delays Inverter Motor and Load  Outputs Rs  PMSM Parameter Estimation Copyright 2023 The MathWorks, Inc. Ld  Lq  Ke  B 

BLOCK:
<pwmCompare>;ADC_Count;ADC_Transducer_Volt_At_Zero_Ampere;Active Test;ActiveTest;Add;Add Offset;Algorithm_C;Algorithm_HDL;Average-Value Inverter;Bus Selector;Bus_Creator;Bus_Selector;Constant;Continuous_To_Discrete;Controller;Controller_Algorithm;Controller_Mode;Count_At_Zero_Transducer_Volt;Data Type Conversion;Data_Type_Conversion;Delay;Demux;Discrete_To_Continuous;Duty;Duty_abc;Encoder_Count;Encoder_Index_Found;Estimated Parameters;Get Current Sense Voltage;Get_PU;Get_PU ;Get_QEP_Counts;Iabc;IndexOffset in PU;Info;Interior PMSM with free rotor (Ke, J, B);Interior PMSM with locked rotor (Rs, Ld, Lq);Inverter;InverterEnable;Inverter_Enable;Mod;Motor Params;MotorParams;MotorSpeed;Motor_And_Load;Motor_Commands;Motor_Measurements;Motor_On;Mux;Normalize [-0.5 to 0.5];Out;Outport;PU;PWM;PWM_Compare;PWM_Count_to_Duty;PhaseCurr;Plant;Product;RT;Rate Transition;Rate_Transition;Reference;Saturate at ADC Vref;Selector;Sensor_Measurements;Sim_fb;Step;SubSystem;Sum;Switch;Switch to closed loop ;System_Measurements;System_Response;Terminator;TestConfig;TestConfiguration;TestEnable;Test_Config_In;Test_Config_Out;Test_State;Test_number;Theta;Vabc;Verify_Outputs;Wrap;in;out;rad

BLOCKTYPE:
Average Value Inverter;BusCreator;BusSelector;Constant;DataTypeConversion;Delay;Demux;Display;Gain;Inport;InportShadow;Interior PMSM;Math;ModelReference;Mux;Outport;PMSM Parameter Estimation Configurator;Product;RateTransition;Saturate;Scope;Selector;Step;Sum;Switch;Terminator


MODELNAME: focZynqArmDeployment
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqArmDeployment.slx
BLOCKTYPE_FREQUENCY: 1;2;1;3;1;4;6;1;1;2;1;1;1;1;1;1;1;1;1;1
CHECKSUM: 07D5DADC5977A718A569B5A6ED24C851
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: focZynqC___Model_Block___
ANNOTATION:
Enum Data Type Conversion Field-Oriented Control of Velocity Zynq ARM Deployment for Trenz Motor Control Kit Copyright 2015-2022 The MathWorks, Inc.

BLOCK:
AXI_Interface;Algorithm_C;Bus_Creator;Bus_Selector;Command_Mode;Constant;Data_Type_Int;Delay;Demux;Display;Enum_Data_Type;Enum_Data_Type_Conversion;In;Input_Source;Int32_Data_Type;Motor_On_Switch;Mux;Out;Reference;Scope;Select_Source;Signal Editor;Slider_Gain;SubSystem;Terminator

BLOCKTYPE:
AXI4-Lite/AXI4 Interface;BusCreator;BusSelector;Constant;Convert to enumerated data type;DataTypeConversion;Delay;Demux;Display;Enumerated Constant;Inport;ManualSwitch;ModelReference;MultiPortSwitch;Mux;Outport;Scope;SignalEditor;Slider Gain;Terminator


MODELNAME: focZynqC
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqC.slx
BLOCKTYPE_FREQUENCY: 2;1;28;8;13;2;5;2;9;2;46;5;7;1;2;44;6;8;2;1;5;18;12;2;1;2
CHECKSUM: 9725B8CE86D7F386BF4203CA76B5DA13
PRODUCT: Embedded Coder;Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Calibration Count To Limit Negate Zero To Two Pi Wrap Neg Pi To Pi Once Encoder Calibration Calibrate Encoder Offset Mod Two Pi Once Electrical Velocity To Position Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Detect Change Set Acceleration Ramp Velocity Rotor Velocity To Volts Open Loop Velocity Control Open Loop Velocity Control Disabled Velocity Control Velocity Control Copyright 2015-2020 The MathWorks, Inc. Field-Oriented Control of Velocity Zynq C Specification

BLOCK:
 Demux ; SFunction ; Terminator ; calibrateEncoder; closedLoop; enableInverter; openLoop;A;ABC;ADCCaFlag;ADCCounts;ADCOffsetPhA;ADCOffsetPhB;ADCOffsets;ADC_Calibration;ADC_Counts_Ph_A;ADC_Counts_Ph_B;AND_Neg;AND_Pos;Abs;Acceleration;Add;Alpha;At_Limit;Beta;Calibrate_Encoder_Offset;Command_Type;Command_Velocity;Constant;Continue_Count;Cos_Coefficient;Count_To_Limit;Current;Current_Command;Current_Fixed_Point;D;Data Type Conversion;Delay;Detect_Change;Difference;Direct_Voltage;Duration;EP;EV;Electrical_Velocity;Electrical_Velocity_To_Position;EnCalibration;En_Closed_Loop;En_Inverter;Enable;Encoder_Calibration;Encoder_Index_Found;Encoder_Offset;Error;Flag;Frequency_To_Voltage;From;Gain;Goto;Greater_Or_Equal;Greater_Than;In;Input_Range;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Latch_Target;Less_Than;Limit;Logical_OR;MATLAB Function;Max_Abs_Error;Merge;Mod_Two_Pi_Once;Mod_X_Two_Pi;Mode_Scheduler;Mode_Scheduler_State;Motor_On;Mux;NOT;Neg_Pi;Negate_Zero_To_Two_Pi;Not_Equal;Not_Equal_Zero;Number_Of_Pole_Pairs;OR;Offset_Fixed_Point;Open_Loop_Velocity_Control;Out;Output_Range;PI;Phase Voltage;Phase_Voltage;Phase_Voltage_Amplitude;Position;Position_At_Zero_Count;Position_At_Zero_Count_Valid;Position_Single;Position_Valid;Product;Proportional_Gain;Q;Q_Current_Command;RV;Ramp_Velocity;Reference;Reset;Reset_Count;Rotor_Position;Rotor_Velocity;Rotor_Velocity_To_Volts;Sample_Frequency;Sample_Time;Samples;Saturate_Magnitude;Saturate_Output;Set_Acceleration;Sin_Coefficient;Sine_Cosine;StandBy;Stop_Count;SubSystem;Subtract;Sum;Switch;Switch_Dir;Switch_Stop;Two_Pi;Unary_Minus;V;V_Current;V_Target;Velocity_Command;Velocity_Control;Velocity_Measured;Velocity_Single;Voltage_Bias;Voltage_Fixed_Point;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Y;Zero;Zero_During_Calibration;adcCalibration;adcCalibrationStatus;commandType;encoderIndexFound;encoderOffsetFound;error;mode;motorOn

BLOCKTYPE:
Abs;Compare To Zero;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Logic;Merge;Mux;Outport;Product;RelationalOperator;S-Function;Saturation Dynamic;SignalSpecification;Sum;Switch;Terminator;Trigonometry;UnaryMinus


MODELNAME: focZynqCFO
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqCFO.slx
BLOCKTYPE_FREQUENCY: 1;12;7;3;2;4;1;2;1;26;2;1;1;1;2;24;1;1;3;1;2;1;1;1;3;1;4;1
CHECKSUM: 66F264D4A28C2E7423AF8BD1F35F2046
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Calibration Open_Loop_Velocity_Control Open Loop Velocity Control Open Loop Velocity Control Disabled Velocity Control Velocity Control Copyright 2022 The MathWorks, Inc. Field-Oriented Control of Velocity Zynq C Specification

BLOCK:
 Demux ; Open_Loop; SFunction ; Terminator ; closedLoop; enableInverter;ADCCaFlag;ADCCounts;ADCOffsetPhA;ADCOffsetPhB;ADCOffsets;ADC_Calibration;ADC_Counts_Ph_A;ADC_Counts_Ph_B;Abs;Add;Command_Type;Command_Velocity;Constant;Current;Current_Command;Current_Fixed_Point;Data Type Conversion;Delay;EnCalibration;En_Closed_Loop;En_Inverter;Enable;Encoder_Offset;Error;Flag;From;Gain;Goto;IndexFound;Integral_Gain;Inverse Park Transform;MATLAB Function;Merge;Mode_Scheduler;Mode_Scheduler_State;Motor_On;Mux;NOT;Not_Equal;Offset_Fixed_Point;OpenLoopSpeed;Open_Loop_Control;Open_Loop_Velocity_Control;PWM Reference Generator;Phase Voltage;Phase_Voltage;Pos_PU_Out;Position Generator;Product;Proportional_Gain;Q_Current_Command;Reference;Rotor_Position;Rotor_Velocity;Sample_Time;Samples;Saturate_Magnitude;Saturate_Output;Sign;Sine-Cosine Lookup;SpeedRef;StandBy;SubSystem;Switch;Terminator;Unary_Minus;Velocity_Command;Velocity_Control;Velocity_Measured;Velocity_Single;Voltage_Fixed_Point;Zero;adcCalibration;adcCalibrationStatus;commandType;error;mode;motorOn

BLOCKTYPE:
Abs;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Inverse Park Transform;Logic;Merge;Mux;Outport;PWM Modulation;Position Generator;Product;RelationalOperator;S-Function;Saturation Dynamic;Signum;Sine-Cosine Lookup;Sum;Switch;Terminator;UnaryMinus


MODELNAME: focZynqHdl
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqHdl.slx
BLOCKTYPE_FREQUENCY: 1;2;18;8;30;7;1;6;64;5;2;2;7;1;5;46;4;2;2;3;1;1;1;4;1;1;6;2;1;1
CHECKSUM: 9CDE13F20FE2A5BE23A1DC69751AC2E9
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Count to Current If offset changes, this is a bad sample since the encoder was calibrated to a new value First two velocity calculations are not valid If detect positive rise in valid, this is a bad sample since encoder index just reset Rotor Position Delta Encoder To Position And Velocity DQ Current Control Sine Cosine Fixed Point LUT FOC Current Control DQ Current Control FOC Current Control Over Current Detector Voltage To PWM Compare FOC Encoder Current Loop Field-Oriented Control of Velocity Zynq HDL Specification Copyright 2015-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC_Count_To_Current;ADC_Counts;ADC_Offset_PhA;ADC_Offset_PhB;ADC_Offsets;ADC_Phase_Currents;AND;AXI_ADC_Counts_phA;AXI_ADC_Counts_phB;AXI_ADC_Offset_PhA;AXI_ADC_Offset_PhB;AXI_Current_Command;AXI_Electrical_Position;AXI_Enable_Closed_Loop;AXI_Enable_Inverter;AXI_Encoder_Index_Found;AXI_Encoder_Offset;AXI_Overcurrent_Error;AXI_Phase_Current_A;AXI_Phase_Current_B;AXI_Phase_Voltage_A;AXI_Phase_Voltage_B;AXI_Phase_Voltage_C;AXI_Rotor_Position;AXI_Rotor_Velocity;Abs;Add;Bias;Clarke Transform;Compare;Constant;Cos;Count;Current;Current_Command;DQ_Current_Control;D_Command;D_Control;D_Current;D_Voltage;Data Type Conversion;Data_Type_Conversion;Data_Type_Convert;Delay;Demux;Detect_Change;Detect_Over_Current_Error;Detect_Rise;Electrical_Position;En_Inv;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Offset;Encoder_To_Position_And_Velocity;Error;FOC_Current_Control;FOC_Current_Control_Fixdt;FOC_Current_Control_Single;FOC_Velocity_Encoder;Gain;IP_ADC_A_Count;IP_ADC_B_Count;IP_Encoder_A_Leads_B;IP_Encoder_Count;IP_Encoder_Count_Per_Revolution;IP_Encoder_Index_Found;IP_Inverter_Enable;IP_PWM_A_Compare;IP_PWM_B_Compare;IP_PWM_C_Compare;IP_PWM_Counter_Max;IP_PWM_Dead_Time_Count;Index_Found;Integral_Gain;Inverse Clarke Transform;Inverse Park Transform;Last_Valid_Position;Logical Operator;Logical_AND;Mechanical to Electrical Position;Motor_On;Mux;NOT;No_Change_Detected;No_Rise_Detected;Normalize_Position;Offset;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;P;PWM Reference Generator;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;Park Transform;Phase_Current;Phase_Currents;Phase_Voltage;Phase_Voltage_Command;Position_Delta;Product;Q_Command;Q_Control;Q_Current;Q_Voltage;Quadrature Decoder;Reference;Register;Reset;Rotor_Position;Rotor_Position_Valid;Rotor_Velocity;Sample_Time;Sat;Saturation;Scalar;Sin;Sine_Cosine;Sine_Cosine_LUT;Slope;Speed Measurement;SubSystem;Switch;Tick_Per_Sec;Trigonometric Function;Voltage;Voltage_To_PWM_Compare;enableOverCurrentDetect;error;overCurrentDurationTicks;overCurrentLimit;phaseCurrentA;phaseCurrentB

BLOCKTYPE:
Abs;Clarke Transform;Constant;DataTypeConversion;Delay;Demux;Detect Change;Gain;Inport;InportShadow;Inverse Clarke Transform;Inverse Park Transform;Logic;Mechanical to Electrical Position;Mux;Outport;PID 1dof;PWM Modulation;Park Transform;Product;Quadrature Decoder;RelationalOperator;S-Function;Saturate;Sine and Cosine;Speed Measurement;Sum;Switch;Terminator;Trigonometry


MODELNAME: focZynqHdlFO
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqHdlFO.slx
BLOCKTYPE_FREQUENCY: 1;1;13;8;27;7;1;3;4;3;44;5;1;1;5;5;41;2;1;1;2;1;3;1;1;4;1;4
CHECKSUM: 2C8209C208BDBD2D520D7D6E56815D0C
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Count to Current DQ Current Control Sine Cosine Fixed Point LUT FOC Current Control Fo Position And Velocity Over Current Detector Voltage To PWM Compare FOC Current Control Loop Field-Oriented Control of Velocity Zynq HDL Specification Copyright 2015-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC_Count_To_Current;ADC_Counts;ADC_Offset_PhA;ADC_Offset_PhB;ADC_Offsets;ADC_Phase_Currents;AND;AXI_ADC_Counts_phA;AXI_ADC_Counts_phB;AXI_ADC_Offset_PhA;AXI_ADC_Offset_PhB;AXI_Current_Command;AXI_Electrical_Position;AXI_Enable_Closed_Loop;AXI_Enable_Inverter;AXI_Encoder_Index_Found;AXI_Encoder_Offset;AXI_Overcurrent_Error;AXI_Phase_Current_A;AXI_Phase_Current_B;AXI_Phase_Voltage_A;AXI_Phase_Voltage_B;AXI_Phase_Voltage_C;AXI_Rotor_Position;AXI_Rotor_Velocity;Abs;Add;Bias;Clarke Transform;Compare;Cos;Count;Current;Current_Command;DQ_Current_Control;D_Command;D_Control;D_Current;D_Voltage;Data Type Conversion;Data_Type_Conversion;Data_Type_Convert;Delay;Demux;Detect_Over_Current_Error;Electrical_Position;En_Inv;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Offset;Error;FOC_Current_Control;FO_Position_Velocity;Flux Observer;From;Goto;IP_ADC_A_Count;IP_ADC_B_Count;IP_Encoder_A_Leads_B;IP_Encoder_Count;IP_Encoder_Count_Per_Revolution;IP_Encoder_Index_Found;IP_Inverter_Enable;IP_PWM_A_Compare;IP_PWM_B_Compare;IP_PWM_C_Compare;IP_PWM_Counter_Max;IP_PWM_Dead_Time_Count;Integral_Gain;Inverse Clarke Transform;Inverse Park Transform;Logical Operator;Motor_On;Mux;NOT;Normalize_Position;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;P;PWM Reference Generator;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;Park Transform;Phase_Current;Phase_Currents;Phase_Voltage;Phase_Voltage_Command;Product;Q_Command;Q_Control;Q_Current;Q_Voltage;Reference;Register;Reset;Rotor_Position;Rotor_Velocity;Sample_Time;Sat;Saturation;Scalar;Sin;Sine_Cosine;Sine_Cosine_LUT;Slope;Speed Measurement;SubSystem;Switch;Terminator;Tick_Per_Sec;VIFb;VI_Fb;Voltage;Voltage_To_PWM_Compare;elect2mech;enableOverCurrentDetect;error;overCurrentDurationTicks;overCurrentLimit;phaseCurrentA;phaseCurrentB

BLOCKTYPE:
Abs;Clarke Transform;Constant;DataTypeConversion;Delay;Demux;Flux Observer;From;Gain;Goto;Inport;InportShadow;Inverse Clarke Transform;Inverse Park Transform;Logic;Mux;Outport;PID 1dof;PWM Modulation;Park Transform;Product;S-Function;Saturate;Sine and Cosine;Speed Measurement;Sum;Switch;Terminator


MODELNAME: focZynqTestBench
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqTestBench.slx
BLOCKTYPE_FREQUENCY: 1;4;9;11;3;1;1;21;2;4;1;3;9;3;1;1;1;33;1;1;2;3;2;4;28;6;1;4;1;1;36;1;1;7;1;7;1;4;5;1;5;11
CHECKSUM: 66E864BCEA7360938DA3EE5BD8406D2F
PRODUCT: Embedded Coder;Motor Control Blockset;Simscape;Simscape Electrical;Simulink
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: focZynqC___Model_Block___focZynqHdl___Model_Block___
ANNOTATION:
Continuous To Discrete Controller Algorithm Discrete To Continuous Enum Data Type Conversion PWM Peripheral And Inverter Scaling Delays Inverter Motor and Load  Outputs Permanent Magnet Synchronous Motor Field Oriented Control Copyright 2015-2022 The MathWorks, Inc.

BLOCK:
<pwmCompare>;A;ADC_Count;ADC_Transducer_Volt_At_Zero_Ampere;Add;Add Offset;Algorithm_C;Algorithm_HDL;Average-Value Inverter;B;Bias;Bus Selector;Bus_Creator;Bus_Selector;C;Command_Type;Constant;Continuous_To_Discrete;Controlled_Voltage_Source;Controller;Controller_Algorithm;Controller_Mode;Count;Count_At_Zero_Transducer_Volt;Current Sensor (Three-Phase);Data Type Conversion;Data_Type_Conversion;Delay;Demux;Discrete_To_Continuous;Duty;Duty_abc;Electrical_Reference;En;Encoder_Count;Encoder_Index_Found;Enum_Data_Type;Enum_Data_Type_Conversion;From;Gain;Get Current Sense Voltage;Get_PU;Get_PU ;Get_QEP_Counts;Goto;IIR Filter;Iabc;Ideal Rotational Motion Sensor;Ideal Torque Source;Ideal_Switch;In;IndexOffset in PU;Info;Int32_Data_Type;Inverter;InverterEnable;Inverter_Enable;Line Voltage Sensor (Three-Phase);Load;Load_Profile (Torque);Load_Trq;Low-Pass Filter (Discrete or Continuous);MCB;Mechanical Rotational Reference;Mod;MotorSpeed;Motor_And_Load;Motor_Commands;Motor_Measurements;Motor_On;Mux;No_load_during_Standby;No_load_load_selctor;Noload;Normalize [-0.5 to 0.5];Out;PMSM;PS-Simulink Converter;PU;PWM_Compare;PWM_Count_to_Duty;PWM_Peripheral_And_Inverter;Phase Splitter;PhaseCurr;Plant ;Plant Selection;R ;RT;Radio Button;Rate Transition;Rate_Transition;Reference;Saturate at ADC Vref;Selector;Sensor_Measurements;Sim_fb;Simscape;Simulink-PS Converter;Simulink_To_PS;Slope;Solver Configuration;SubSystem;Subsystem;Sum;Surface Mount PMSM;Switch;Switch to closed loop ;SystemInput;System_Inputs;System_Measurements;System_Response;T_load;Terminator;Theta;Tm;Vabc;Velocity_Command;Verify_Outputs;Volts_Per_PWM_Count;Wrap;in;measVI;out;rad;~

BLOCKTYPE:
Average Value Inverter;BusCreator;BusSelector;Constant;Controlled Voltage Source;Convert to enumerated data type;Current Sensor (Three-Phase);DataTypeConversion;Delay;Demux;Electrical Reference;From;Gain;Goto;IIR Filter;Ideal Rotational Motion Sensor;Ideal Torque Source;Inport;Line Voltage Sensor (Three-Phase);Low-Pass Filter (Discrete or Continuous);Math;Mechanical Rotational Reference;ModelReference;Mux;Outport;PMIOPort;PMSM;PS-Simulink Converter;Phase Splitter;RadioButtonGroup;RateTransition;Saturate;Scope;Selector;SignalEditor;Simulink-PS Converter;Solver Configuration;Step;Sum;Surface Mount PMSM;Switch;Terminator


MODELNAME: focZynqTestBenchFO
PATH: toolbox/shared/hdlmotorcontrol/mcbMotorControlFpgaDemo/FocZynq/focZynqTestBenchFO.slx
BLOCKTYPE_FREQUENCY: 1;4;9;11;3;1;1;21;2;4;1;3;9;3;1;1;1;33;1;1;2;3;2;4;28;6;1;4;1;1;36;1;1;7;1;7;1;4;5;1;5;11
CHECKSUM: 786868695F6ED597E3EF9A99C07458FC
PRODUCT: Embedded Coder;Motor Control Blockset;Simscape;Simscape Electrical;Simulink
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: focZynqCFO.slx___Model_Block___focZynqHdlFO.slx___Model_Block___
ANNOTATION:
Continuous To Discrete Controller Algorithm Discrete To Continuous Enum Data Type Conversion PWM Peripheral And Inverter Scaling Delays Inverter Motor and Load  Outputs Permanent Magnet Synchronous Motor Field Oriented Control Copyright 2022 The MathWorks, Inc.

BLOCK:
<pwmCompare>;A;ADC_Count;ADC_Transducer_Volt_At_Zero_Ampere;Add;Add Offset;Algorithm_C;Algorithm_HDL;Average-Value Inverter;B;Bias;Bus Selector;Bus_Creator;Bus_Selector;C;Command_Type;Constant;Continuous_To_Discrete;Controlled_Voltage_Source;Controller;Controller_Algorithm;Controller_Mode;Count;Count_At_Zero_Transducer_Volt;Current Sensor (Three-Phase);Data Type Conversion;Data_Type_Conversion;Delay;Demux;Discrete_To_Continuous;Duty;Duty_abc;Electrical_Reference;En;Encoder_Count;Encoder_Index_Found;Enum_Data_Type;Enum_Data_Type_Conversion;From;Gain;Get Current Sense Voltage;Get_PU;Get_PU ;Get_QEP_Counts;Goto;IIR Filter;Iabc;Ideal Rotational Motion Sensor;Ideal Torque Source;Ideal_Switch;In;IndexOffset in PU;Info;Int32_Data_Type;Inverter;InverterEnable;Inverter_Enable;Line Voltage Sensor (Three-Phase);Load;Load_Profile (Torque);Load_Trq;Low-Pass Filter (Discrete or Continuous);MCB;Mechanical Rotational Reference;Mod;MotorSpeed;Motor_And_Load;Motor_Commands;Motor_Measurements;Motor_On;Mux;No_load_during_Standby;No_load_load_selctor;Noload;Normalize [-0.5 to 0.5];Out;PMSM;PS-Simulink Converter;PU;PWM_Compare;PWM_Count_to_Duty;PWM_Peripheral_And_Inverter;Phase Splitter;PhaseCurr;Plant ;Plant Selection;R ;RT;Radio Button;Rate Transition;Rate_Transition;Reference;Saturate at ADC Vref;Selector;Sensor_Measurements;Sim_fb;Simscape;Simulink-PS Converter;Simulink_To_PS;Slope;Solver Configuration;SubSystem;Subsystem;Sum;Surface Mount PMSM;Switch;Switch to closed loop ;SystemInput;System_Inputs;System_Measurements;System_Response;T_load;Terminator;Theta;Tm;Vabc;Velocity_Command;Verify_Outputs;Volts_Per_PWM_Count;Wrap;in;measVI;out;rad;~

BLOCKTYPE:
Average Value Inverter;BusCreator;BusSelector;Constant;Controlled Voltage Source;Convert to enumerated data type;Current Sensor (Three-Phase);DataTypeConversion;Delay;Demux;Electrical Reference;From;Gain;Goto;IIR Filter;Ideal Rotational Motion Sensor;Ideal Torque Source;Inport;Line Voltage Sensor (Three-Phase);Low-Pass Filter (Discrete or Continuous);Math;Mechanical Rotational Reference;ModelReference;Mux;Outport;PMIOPort;PMSM;PS-Simulink Converter;Phase Splitter;RadioButtonGroup;RateTransition;Saturate;Scope;Selector;SignalEditor;Simulink-PS Converter;Solver Configuration;Step;Sum;Surface Mount PMSM;Switch;Terminator


MODELNAME: soc_trenz_fpga
PATH: toolbox/shared/hdlmotorcontrol/socMotorControl/soc_trenz_fpga.slx
BLOCKTYPE_FREQUENCY: 1;2;18;8;30;7;1;6;77;5;2;2;7;1;5;59;4;2;2;3;1;1;1;4;1;1;6;2;5;1
CHECKSUM: F42FF9E7844EC7629E81F685091D8F7A
PRODUCT: Embedded Coder;Motor Control Blockset;Simulink;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
ADC Count to Current If offset changes, this is a bad sample since the encoder was calibrated to a new value First two velocity calculations are not valid If detect positive rise in valid, this is a bad sample since encoder index just reset Rotor Position Delta Encoder To Position And Velocity DQ Current Control Sine Cosine Fixed Point LUT FOC Current Control DQ Current Control FOC Current Control Over Current Detector Voltage To PWM Compare FOC Encoder Current Loop Field-Oriented Control of Velocity Zynq HDL Specification Copyright 2015-20120 The MathWorks, Inc.  Field-Oriented Control of PMSM (FPGA Model)  Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC_Count_To_Current;ADC_Counts;ADC_Offset_PhA;ADC_Offset_PhB;ADC_Offsets;ADC_Phase_Currents;AND;AXI_ADC_Counts_phA;AXI_ADC_Counts_phA ;AXI_ADC_Counts_phB;AXI_ADC_Offset_PhA;AXI_ADC_Offset_PhB;AXI_Current_Command;AXI_Electrical_Position;AXI_Enable_Closed_Loop;AXI_Enable_Inverter;AXI_Encoder_Index_Found;AXI_Encoder_Offset;AXI_Overcurrent_Error;AXI_Phase_Current_A;AXI_Phase_Current_B;AXI_Phase_Voltage_A;AXI_Phase_Voltage_B;AXI_Phase_Voltage_C;AXI_Rotor_Position;AXI_Rotor_Velocity;Abs;Add;Bias;Clarke Transform;Compare;Constant;Cos;Count;Current;Current_Command;DQ_Current_Control;D_Command;D_Control;D_Current;D_Voltage;Data Type Conversion;Data_Type_Conversion;Data_Type_Convert;Delay;Demux;Detect_Change;Detect_Over_Current_Error;Detect_Rise;Electrical_Position;En_Inv;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Offset;Encoder_To_Position_And_Velocity;Error;FOC_Current_Control;FOC_Current_Control_Fixdt;FOC_Current_Control_Single;FOC_Velocity_Encoder;FPGA;Gain;IP_ADC_A_Count;IP_ADC_B_Count;IP_Encoder_A_Leads_B;IP_Encoder_Count;IP_Encoder_Count_Per_Revolution;IP_Encoder_Index_Found;IP_Inverter_Enable;IP_PWM_A_Compare;IP_PWM_B_Compare;IP_PWM_C_Compare;IP_PWM_Counter_Max;IP_PWM_Dead_Time_Count;Index_Found;Integral_Gain;Inverse Clarke Transform;Inverse Park Transform;Last_Valid_Position;Logical Operator;Logical_AND;Mechanical to Electrical Position;Motor_On;Mux;NOT;No_Change_Detected;No_Rise_Detected;Normalize_Position;Offset;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;P;PWM Reference Generator;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;Park Transform;Phase_Current;Phase_Currents;Phase_Voltage;Phase_Voltage_Command;Position_Delta;Product;Q_Command;Q_Control;Q_Current;Q_Voltage;Quadrature Decoder;Reference;Register;Reset;Rotor_Position;Rotor_Position_Valid;Rotor_Velocity;Sample_Time;Sat;Saturation;Scalar;Sin;Sine_Cosine;Sine_Cosine_LUT;Slope;Speed Measurement;SubSystem;Switch;Terminator;Tick_Per_Sec;Trigonometric Function;Voltage;Voltage_To_PWM_Compare;enableOverCurrentDetect;error;overCurrentDurationTicks;overCurrentLimit;phaseCurrentA;phaseCurrentB

BLOCKTYPE:
Abs;Clarke Transform;Constant;DataTypeConversion;Delay;Demux;Detect Change;Gain;Inport;InportShadow;Inverse Clarke Transform;Inverse Park Transform;Logic;Mechanical to Electrical Position;Mux;Outport;PID 1dof;PWM Modulation;Park Transform;Product;Quadrature Decoder;RelationalOperator;S-Function;Saturate;Sine and Cosine;Speed Measurement;Sum;Switch;Terminator;Trigonometry


MODELNAME: soc_trenz_proc
PATH: toolbox/shared/hdlmotorcontrol/socMotorControl/soc_trenz_proc.slx
BLOCKTYPE_FREQUENCY: 2;1;1;28;1;12;19;3;5;2;9;2;100;4;7;1;1;1;3;2;95;6;9;9;8;2;1;1;5;18;12;1;1;6;1;2
CHECKSUM: AD5F0D3991A9DAE589399A870AEA0C64
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset;Stateflow
PRODUCT_BASECODE: HD;MT;HW
ANNOTATION:
Enum Data Type Conversion ADC Calibration Count To Limit Negate Zero To Two Pi Wrap Neg Pi To Pi Once Encoder Calibration Calibrate Encoder Offset Mod Two Pi Once Electrical Velocity To Position Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Detect Change Set Acceleration Ramp Velocity Rotor Velocity To Volts Open Loop Velocity Control Open Loop Velocity Control Disabled Velocity Control Velocity Control Copyright 2023 The MathWorks, Inc.  Field-Oriented Control of PMSM (Processor Model)

BLOCK:
 Demux ; SFunction ; Terminator ; calibrateEncoder; closedLoop; enableInverter; openLoop;A;ABC;ADCCaFlag;ADCCounts;ADCOffsetPhA;ADCOffsetPhB;ADCOffsets;ADC_Calibration;ADC_Counts_Ph_A;ADC_Counts_Ph_B;ADC_Offset_PhA;ADC_Offset_PhB;AND_Neg;AND_Pos;AXI4LiteRead;AXI4LiteWrite;AXI4Lite_ADC_Counts_phA_rd;AXI4Lite_ADC_Counts_phB_rd;AXI4Lite_Read_AXI_Electrical_Position_rd;AXI4Lite_Read_AXI_Encoder_Index_Found_rd;AXI4Lite_Read_AXI_Overcurrent_Error_rd;AXI4Lite_Read_AXI_Phase_Current_A_rd;AXI4Lite_Read_AXI_Phase_Current_B_rd;AXI4Lite_Read_AXI_Rotor_Position_rd;AXI4Lite_Read_AXI_Rotor_Velocity_rd;AXI4Reset;AXI4ResetModelSource;AXI4_ADC_Counts_phA;AXI4_ADC_Counts_phB;AXI_ADC_Counts_phA_rd;AXI_ADC_Counts_phB_rd;AXI_ADC_Offset_PhA;AXI_ADC_Offset_PhA_wr;AXI_ADC_Offset_PhB;AXI_ADC_Offset_PhB_wr;AXI_Current_Command;AXI_Current_Command_wr;AXI_Electrical_Position;AXI_Electrical_Position_rd;AXI_Enable_Closed_Loop;AXI_Enable_Closed_Loop_wr;AXI_Enable_Inverter;AXI_Enable_Inverter_wr;AXI_Encoder_Index_Found;AXI_Encoder_Index_Found_rd;AXI_Encoder_Offset;AXI_Encoder_Offset_wr;AXI_Interface;AXI_Overcurrent_Error;AXI_Overcurrent_Error_rd;AXI_Phase_Current_A;AXI_Phase_Current_A_rd;AXI_Phase_Current_B;AXI_Phase_Current_B_rd;AXI_Phase_Voltage_A;AXI_Phase_Voltage_A_wr;AXI_Phase_Voltage_B;AXI_Phase_Voltage_B_wr;AXI_Phase_Voltage_C;AXI_Phase_Voltage_C_wr;AXI_Rotor_Position;AXI_Rotor_Position_rd;AXI_Rotor_Velocity;AXI_Rotor_Velocity_rd;Abs;Acceleration;Add;Alpha;At_Limit;Beta;Bus Creator;Calibrate_Encoder_Offset;Constant;Continue_Count;Cos_Coefficient;Count_To_Limit;Current;Current_Fixed_Point;D;Data Type Conversion;Data_Type_Int;Delay;Demux;Detect_Change;Difference;Direct_Voltage;Duration;EP;EV;Electrical_Velocity;Electrical_Velocity_To_Position;EnCalibration;Enable;Encoder_Calibration;Enum_Data_Type;Enum_Data_Type_Conversion;Error;Flag;Frequency_To_Voltage;From;Gain;Goto;Greater_Or_Equal;Greater_Than;In;Input_Range;Int32_Data_Type;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Latch_Target;Less_Than;Limit;Logical_OR;MATLAB Function;Max_Abs_Error;Merge;Mod_Two_Pi_Once;Mod_X_Two_Pi;Mode_Scheduler;Model Header;Mux;NOT;Neg_Pi;Negate_Zero_To_Two_Pi;Not_Equal;Not_Equal_Zero;Number_Of_Pole_Pairs;OR;Offset_Fixed_Point;Open_Loop_Velocity_Control;Out;Output_Range;PI;Phase Voltage;Phase_Voltage;Phase_Voltage_Amplitude;Position;Position_At_Zero_Count;Position_At_Zero_Count_Valid;Position_Single;Position_Valid;Product;Proportional_Gain;Q;Q_Current_Command;RV;Ramp_Velocity;Reference;Register Read;Register Write;Reset;Reset_Count;Rotor_Position;Rotor_Velocity;Rotor_Velocity_To_Volts;Sample_Frequency;Sample_Time;Samples;Saturate_Magnitude;Saturate_Output;Select_Source;Set_Acceleration;Signal_Builder_Experiments;Sin_Coefficient;Sine_Cosine;StandBy;Stop_Count;SubSystem;Subtract;Sum;Switch;Switch_Dir;Switch_Stop;System Terminate;System_Input;Terminator;Two_Pi;Unary_Minus;V;V_Current;V_Target;Velocity_Command;Velocity_Control;Velocity_Measured;Velocity_Single;Voltage_Bias;Voltage_Fixed_Point;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Y;Zero;Zero_During_Calibration;adcCalibration;adcCalibrationStatus;commandType;encoderIndexFound;encoderOffsetFound;error;mode;motorOn

BLOCKTYPE:
Abs;BusCreator;Compare To Zero;Constant;Convert to enumerated data type;DataTypeConversion;Delay;Demux;EnablePort;From;Gain;Goto;Inport;InportShadow;Logic;Merge;Model Header;Model Source;MultiPortSwitch;Mux;Outport;Product;Register Read;Register Write;RelationalOperator;S-Function;Saturation Dynamic;SignalEditor;SignalSpecification;Sum;Switch;System Start;System Terminate;Terminator;Trigonometry;UnaryMinus


MODELNAME: soc_trenz_top
PATH: toolbox/shared/hdlmotorcontrol/socMotorControl/soc_trenz_top.slx
BLOCKTYPE_FREQUENCY: 1;2;3;14;3;1;11;2;2;1;2;3;9;3;1;1;1;19;1;1;1;2;2;3;2;3;21;6;1;4;1;1;10;1;1;1;7;7;1;1;4;5;1;5;1;3
CHECKSUM: 1DEED6F3167BB956EE368F22CCB89B4D
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: soc_trenz_fpga.slx___Model_Block___soc_trenz_proc.slx___Model_Block___
ANNOTATION:
PWM Peripheral And Inverter Scaling Delays Inverter Motor and Load  Field-Oriented Control of PMSM (SoC Model)  Testbench  FPGA  Copyright 2023 The MathWorks, Inc.  AXI Interface  Plant  Processor 

BLOCK:
<pwmCompare>;A;ADC_Transducer_Volt_At_Zero_Ampere;Add;Add Offset;Average-Value Inverter;B;Bias;Bus Creator;Bus Selector;Bus_Creator;Bus_Selector;C;Command_Mode;Constant;Control Switch;Controlled_Voltage_Source;Controller;Count;Count_At_Zero_Transducer_Volt;Current Sensor (Three-Phase);Data Type Conversion;Delay;Demux;Duty;Duty_abc;Electrical_Reference;En;From;Gain;Get Current Sense Voltage;Get_PU;Get_PU ;Get_QEP_Counts;Goto;IIR Filter;Iabc;Ideal Rotational Motion Sensor;Ideal Torque Source;Ideal_Switch;IndexOffset in PU;Info;Input_Source;Inverter;InverterEnable;Line Voltage Sensor (Three-Phase);Load;Load_Profile (Torque);Load_Trq;Low-Pass Filter (Discrete or Continuous);MCB;Manual_Switch;Mechanical Rotational Reference;Mod;Model;Motor Velocity Control;MotorSpeed;Motor_And_Load;Motor_On_Switch;Mux;No_load_during_Standby;No_load_load_selctor;Noload;Normalize [-0.5 to 0.5];Out;PMSM;PS-Simulink Converter;PU;PWM_Count_to_Duty;PWM_Peripheral_And_Inverter;Phase Splitter;PhaseCurr;Plant ;Plant Selection;R ;RT;Radio Button;Rate Transition;Rate_Transition;Reference;Register Channel;Saturate at ADC Vref;Selector;Sensor_Measurements;Sim_fb;Simscape;Simulink-PS Converter;Simulink_To_PS;Sine_Wave;Slope;Solver Configuration;SubSystem;Subsystem;Sum;Surface Mount PMSM;Switch;Switch to closed loop ;System_Input;T_load;Task Manager;Terminator;Theta;Tm;Vabc;Volts_Per_PWM_Count;Wrap;in;measVI;out;rad;~

BLOCKTYPE:
Average Value Inverter;BusCreator;BusSelector;Constant;Controlled Voltage Source;Current Sensor (Three-Phase);DataTypeConversion;Delay;Demux;Electrical Reference;Enumerated Constant;From;Gain;Goto;IIR Filter;Ideal Rotational Motion Sensor;Ideal Torque Source;Inport;KnobBlock;Line Voltage Sensor (Three-Phase);Low-Pass Filter (Discrete or Continuous);ManualSwitch;Math;Mechanical Rotational Reference;ModelReference;Mux;Outport;PMIOPort;PMSM;PS-Simulink Converter;Phase Splitter;RadioButtonGroup;RateTransition;Register Channel;RockerSwitchBlock;Saturate;Selector;Simulink-PS Converter;Sine Wave;Solver Configuration;Step;Sum;Surface Mount PMSM;Switch;Task Manager;Terminator

PRODUCT:
DSP System Toolbox;Embedded Coder;Motor Control Blockset;Simscape;Simscape Electrical;Simulink;SoC Blockset


MODELNAME: soc_trenz_top_sw_exmode
PATH: toolbox/shared/hdlmotorcontrol/socMotorControl/soc_trenz_top_sw_exmode.slx
ANNOTATION: Testbench Field-Oriented Control of PMSM (SoC Software Model) Copyright 2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 3;2;9;9;1;2;1;4;1;1;1
CHECKSUM: DDF56D152641B88E09B9FB1F5B96B4E9
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset;SoC Blockset
PRODUCT_BASECODE: HD;MT;HW
EXTERNALFILE_REFERENCE: soc_trenz_proc.slx___Model_Block___
BLOCK:
Command_Mode;Constant;Control Switch;IODataSink_Register;IODataSource_Register;Input_Source;Manual_Switch;Model;Motor Velocity Control;Motor_On_Switch;Out;Reference;Sine_Wave;SubSystem;System_Input;Task Manager

BLOCKTYPE:
Constant;Enumerated Constant;IO Data Sink;IO Data Source;KnobBlock;ManualSwitch;ModelReference;Outport;RockerSwitchBlock;Sine Wave;Task Manager


MODELNAME: priv_zynqRadioHWSWReceiveSkeleton
PATH: toolbox/shared/sdr/sdrz/sdrz/priv_zynqRadioHWSWReceiveSkeleton.slx
BLOCKTYPE: Inport;Outport;SignalSpecification
BLOCKTYPE_FREQUENCY: 1;4;1
CHECKSUM: F096152332191F654E9933D3071565D2
PRODUCT: Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: USRPEMBED;XILINX_BLOCKSET
ANNOTATION:
SDR Receiver to ARM Algorithm ARM Interface to HW User Logic  Add receive algorithm here  Write to HW user logic here  Read from HW user logic here  Sample rate should reflect the expected rate of frames arriving at the ARM from the FPGA. When there is no downsampling in the receive DUT, this will be equal to SamplesPerFrame/BasebandSampleRate.

BLOCK:
ARM Frame Rate;DUTInterfaceBlock;DUTInterfaceIn;DUTInterfaceOut;Receive Block;SubSystem;data;data valid;overflow


MODELNAME: priv_zynqRadioHWSWTransmitReceiveSkeleton
PATH: toolbox/shared/sdr/sdrz/sdrz/priv_zynqRadioHWSWTransmitReceiveSkeleton.slx
BLOCKTYPE: Inport;Outport;SignalSpecification
BLOCKTYPE_FREQUENCY: 2;6;1
CHECKSUM: 7A91FA929A807D39A9D0B85BBCC861D2
PRODUCT: Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: USRPEMBED;XILINX_BLOCKSET
ANNOTATION:
 Add transmit algorithm here SDR Receiver to ARM Algorithm ARM Algorithm to SDR Transmitter ARM Interface to HW User Logic  Add receive algorithm here  Write to HW user logic here  Read from HW user logic here  Sample rate should reflect the expected rate of frames arriving at the ARM from the FPGA. When there is no downsampling in the receive DUT, this will be equal to SamplesPerFrame/BasebandSampleRate.

BLOCK:
ARM Frame Rate;DUTInterfaceBlock;DUTInterfaceIn;DUTInterfaceOut;Receive Block;SubSystem;Transmit Block;data;data valid;overflow;underflow


MODELNAME: priv_zynqRadioHWSWTransmitSkeleton
PATH: toolbox/shared/sdr/sdrz/sdrz/priv_zynqRadioHWSWTransmitSkeleton.slx
BLOCK: DUTInterfaceBlock;DUTInterfaceIn;DUTInterfaceOut;SubSystem;Transmit Block;data;overflow;underflow
BLOCKTYPE: Inport;Outport
BLOCKTYPE_FREQUENCY: 2;3
CHECKSUM: CAFAB92F85AF92C0B63BB3D1357B62B3
PRODUCT: Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: USRPEMBED;XILINX_BLOCKSET
ANNOTATION:
 Add transmit algorithm here ARM Algorithm to SDR Transmitter ARM Interface to HW User Logic  Write to HW user logic here  Read from HW user logic here


MODELNAME: zynqRadioHWSW5GNRMIBRecoveryAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSW5GNRMIBRecoveryAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 4;16;2;5;1;2;12;12;16;3;1;5;2;1;1;1;41;1;1;4;1;1;47;2;2;2;2;1;22;2;3
CHECKSUM: 89D367B08349DADA31C37795DC71D28D
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
12 Bit ADC output is prepended with zeros to 16 bits in receiver chain Input from Cell Search Controller Divide by 16 to model 12 bit ADC prepending to 16 bit. RF Front End timing offset in samples @ 61.44 Msps modulo 1228800 (20 ms) 0: 15 kHz 1: 30 kHz 0: 4 1: 8 Zynq Radio 5G NR MIB Recovery Hardware Model Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;5G MIB Recovery HDL;AXI4 Stream Ready;AXI4S_Tready_In;Add;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Cast;Cast To Boolean;Compare To Constant;Complex to Real-Imag;Constant;Custom Packetisation;DDC;Data Type Conversion;Delay;Demodulation Mode;Demux;Detect Decrease;Detection State;Enable;Gain;HDL Counter;Info;Kssb;Lmax;Log Grid;Log PSS Reports;MATLAB Function;MIB Recovery;Manual Switch;Multiport Switch;Mux;NCellID;OR;PSS Report Valid Count;Parse MIB;Polar Decoding Chain;Real-Imag to Complex;Received Signal;Reference;Report Serializer;RxDataI_In;RxDataQ_In;RxValid_In;SSB Decoding;SSB Detection;Search Mode;Signal Frequrency Offset;Signal Valid;Start Pulse;Sub-carrier Spacing;SubSystem;Tapped Delay;Terminator;Timing Offset;To Workspace;Unit Delay Enabled Synchronous;Valid SSB Grid Count;bch State;bchStatus;cellBarred;convert bus;dataAxiStream;dataIn;dataOut;detectionStatus;dmrsTypeAPos;enableAxiStream;frequencyOffset;gridData;gridValid;gridformat;hrf;in;inputConversion;intraFreqResel;mode;out;pbch State;pbchPayload;pbchStatus;pssCorrelation;pssCorrelationStrength;pssFrequencyOffset;pssNCellID;pssReport;pssReportValid;pssSignalThreshold;pssThreshold;pssTimingOffset;pssValid;report;reportFormat;reportOut;reportValid;reset;rxData;rxDataI;rxDataQ;scsCommon;sfn;sib1Config;ssbDecodeValidOut;ssbGrid;ssbGridValid;ssbIndex;ssbIndex3LSb;ssbReportLSBs;ssbReportMSBs;ssbReportValid;sssCorr;sssCorrelation;sssThresh;sssThreshold;start;status;subcarrierSpacing;timingOffset;unpack complex;validIn;validOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Detect Decrease;Display;EnablePort;Gain;HDL Counter;Info;Inport;Logic;ManualSwitch;ModelReference;MultiPortSwitch;Mux;Outport;RealImagToComplex;S-Function;Signal From Workspace;Sum;Tapped Delay Line;Terminator;ToWorkspace;Unit Delay Enabled Synchronous

PRODUCT:
DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices

EXTERNALFILE_REFERENCE:
nrhdlDDCFR1Core___Model_Block___nrhdlPolarDecodingChainCore___Model_Block___nrhdlSSBDecodingCore___Model_Block___nrhdlSSBDetectionFR1Core___Model_Block___


MODELNAME: zynqRadioHWSW5GNRMIBRecoveryAD9361AD9364SL_hostUDPReceive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSW5GNRMIBRecoveryAD9361AD9364SL_hostUDPReceive.slx
BLOCKTYPE_FREQUENCY: 1;2;12;1;4;8;1;7;5;7;17;1;1;2;1;31;2;1;22;1;2;14;8;5
CHECKSUM: 997625E1A28DDC5B7A9A63DC0BCDA67D
PRODUCT: MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
convert to Hz Interprets first entry in PSS Report table. In demodulation mode only one entry is returned and this is when the model is triggered to stop. convert to Hz convert to Hz Stop Logic  Zynq Radio 5G NR MIB Recovery Host UDP Receive Model Copyright 2020-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Add Constant;Bit Concat;Bit Slice;Cast To Boolean;Cast To Double;Cell ID;Compare To Zero;Constant;Data Type Conversion;Disable;Display Cell Information;Divide;Divide by K to convert Threshold to Energy;Enable;Gain;Interpret Final PSS Report;Interpret SSS Report;Kssb;Log;Log Grid;Multiport Switch;NR-RSSI;NR-RSSI (dBm);PSS SNR;PSS SNR (dB);PSS_Correlation;PSS_FrequencyOffset;PSS_Threshold;PSS_TimingOffset;PSS_nCellID;Parse MIB;Process & Log MIB Report;Process & Log PSS Reports;Process & Log SSS Report;Process & Log Signal Quality Report;Reference;SS-RSRP;SS-RSRP (dBm);SS-RSRQ;SS-RSRQ (dB);SS-SINR;SS-SINR (dB);SSS SNR (dB);SSS_SNR_DB;SelectedPSSReport_CorrelationStrength;SelectedPSSReport_FrequencyOffset;SelectedPSSReport_PSSID;SelectedPSSReport_TimingOffset;SelectedPSSReport_pssThreshold;Selector;Stop Simulation;Stop after successful MIB recovery;SubSystem;Subtract;Terminator;To Workspace;UDP Receive Grid;UDP Receive MIB Reports;UDP Receive PSS Reports;UDP Receive SSS Reports;UDP Receive Signal Quality Report;cellBarred;cellID;dmrsTypeAPos;gridformat;hrf;iSSB;intraFreqResel;measurementsReport;mibBits;pbchPayload;reportFormat;scsCommon;selectedParameters_CorrelationStrength;selectedParameters_FrequencyOffset;selectedParameters_SubCarrierSpacing;sfn;sib1Config;sssCorrelation;sssReport;sssThreshold

BLOCKTYPE:
Bias;Bit Concat;Bit Slice;Compare To Zero;Constant;DataTypeConversion;Demux;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;Math;MultiPortSwitch;Outport;Product;S-Function;Selector;Stop;Sum;Terminator;ToWorkspace;UDP Receive


MODELNAME: zynqRadioHWSW5GNRMIBRecoveryAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSW5GNRMIBRecoveryAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 8;7;1;1;3;16;6;2;1;3;3;30;7;3;2;5;23;3;17;1;57;1;1;1;68;2;2;3;4;1;1;10;5;2;1;1
CHECKSUM: 38C01EA57D9F45D018C27206EEEE5680
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Generated by HDL Workflow Advisor on 01-Sep-2020 12:19:50 AXI Stream to Software SW Send to Host Data Logging SW Restart Select Hardware Board Target Open host model  Double click the block to open the host model.  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required SDR Receiver to ARM Zynq Radio 5G NR MIB Recovery Software Interface Model Alternate Receiver block- select the correct block for your hardware SW Signal Quality Measurements Copyright 2020-2023 The MathWorks, Inc. SW Control Logic HW Core

BLOCK:
 Demux ; SFunction ; Terminator ;5G MIB Recovery HDL;AD936x Receiver;AXI4 Read;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_NCellID;AXI4SlaveRead_bchStatus;AXI4SlaveRead_detectionStatus;AXI4SlaveRead_pbchPayload;AXI4SlaveRead_pbchStatus;AXI4SlaveRead_ssbIndex;AXI4SlaveRead_sssCorr;AXI4SlaveRead_sssThresh;AXI4SlaveWrite;AXI4SlaveWrite_Lmax;AXI4SlaveWrite_NCellID;AXI4SlaveWrite_frequencyOffset;AXI4SlaveWrite_mode;AXI4SlaveWrite_start;AXI4SlaveWrite_subcarrierSpacing;AXI4SlaveWrite_timingOffset;Add Constant;Algorithm Scope;Bit Concat;Bit Slice;Bus Selector;Cast;Cast To Boolean;Cast To Double;Cell Search Controller;Center Frequency;Compare To Constant;Complex to Real-Imag;Constant;Data Converter;Data Type Conversion;DataTypeConversion;Delay;Detect Increase;Enable;FMCOMMS5 Receiver;From;Gain;Goto;Info;Kssb;Lmax;MATLAB Function;MIB Recovery;MIB Report;MIB scope;Multiport Switch;NCellID;Parse MIB;Rate Transition;Real-Imag to Complex;Reference;Report Scope;SSB Data In;SSB Data Out;SSB Measurements Scope;SSS Report;Selected Hardware Board Target;SelectedPSSReport;SelectedParams;Signal Quality Measurements;Signal Quality Report;Start/Restart Pulse Generator;SubSystem;Subsystem;Terminator;UDP Send;UDP send MIB report;UDP send PSS report;UDP send SSS report;UDP send Signal Quality Measurements;UDP send grid;Unit Delay Enabled Synchronous;Vector Concatenate;bchStatus;cellBarred;cellID;cellid;centreFrequency;dataIn;dataOut;decodeStatus;detectionStatus;dmrsTypeAPos;fOffset;frequencyOffset;gridData;gridValid;hrf;hwMode;hwStart;hwStatus;intraFreqResel;mibReportValid;mibReportVector;minChanBW;mode;nCellID;numPSSout;pbchPayload;pbchStatus;permittedSCS;permittedssbPatterns;reportVector;reportVectorValid;report_data;restart;scsCommon;searchControl;selectedParams;selectedReport;setupFreqDependantParams;sfn;sib1Config;sib1En;sigQualMeasurements;sigQualReportVector;signalQualityMeasurements;ssbData;ssbGrid;ssbGridValid;ssbIndex;ssbPattern;sssCorr;sssReportValid;sssReportVector;sssThresh;start;subcarrierSpacing;sw_data;tOffset;timingOffset;unpack complex;unpack report

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Bias;Bit Concat;Bit Slice;BusSelector;Compare To Constant;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Increase;EnablePort;From;Gain;Goto;Info;Inport;MATLABSystem;Model Source;MultiPortSwitch;Outport;RateTransition;RealImagToComplex;S-Function;Scope;Signal From Workspace;System Start;Terminator;UDP Send;Unit Delay Enabled Synchronous;comm.SDRRxAD936x;matlabshared.libiio.axistream.read

PRODUCT:
DSP System Toolbox;Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 3;4;3;8;1;3;22;1;7;40;4;1;5;1;6;2;6;1;1;71;2;1;5;1;1;57;2;3;2;2;1;16;1;2;5
CHECKSUM: 77B4D8D4DDEDE282E9FAE9C427A70BDA
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
12 Bit ADC output is prepended with zeros to 16 bits in receiver chain Copyright 2020-2023 The MathWorks, Inc. RF Front End Zynq Radio 5G NR SIB1 Recovery Hardware Model 0: 5 1: 10 2: 40 Input from Cell Search Controller 0: Case A 1: Case B 2: Case C 0: 4 1: 8 timing offset in samples @ 61.44 Msps modulo 1228800 (20 ms) 0: 15 kHz 1: 30 kHz Divide by 16 to model 12 bit ADC prepending to 16 bit.

BLOCK:
 Demux ; SFunction ; Terminator ;5G SIB1 Recovery HDL;AND;AXI-Stream Manager;AXI4 Stream Ready;Add;BCH State;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Cast;Compare To Constant;Complex to Real-Imag;Constant;Counter;Custom Packetisation;DDC;Data Type Conversion;Delay;Demodulation Mode;Demux;Detect Decrease;Detection State;Display;Enable;From;Gain;Goto;HDL Counter;In Bus Element;Info;Lmax;Log Grids;MATLAB Function;Manual Switch;Multiport Switch;Mux;NCellID;OR;PBCH State;Polar Decoding Chain;RF Plant;Real-Imag to Complex;Reference;Report Serialiser;RxDataI_In;RxDataQ_In;RxValid_In;Rx_I;Rx_Q;SIB1 Demodulation;SIB1 Grid State;SIB1 Input setup;SIB1 Recovery;SSB Decoding;SSB Detection;SSB Report Interface;Search Mode;Signal Frequrency Offset;Signal From Workspace;Signal Valid;Start Pulse;Sub-carrier Spacing;SubSystem;Tapped Delay;Terminator;Timing Offset;To Workspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;axi-stream master;bchStatus;centerFrequency;convert bus;coreset0FrequencyOffset;coreset0RBs;coreset0Resources;dataAxiStream;dataIn;dataOut;detectionStatus;enableAxiStream;frequencyOffset;gridValid;in;inputConversion;master_tdata;master_tlast;master_tready;master_tvalid;mibRecovered;minChanBW;mode;out;pack complex;parsedMIB;pbchPayload;pbchStatus;pssReport;pssReportValid;pssValid;receiverParams;receiverStart;report;reportOut;reportValid;reportValidIn;reportValidOut;reset;rxData;rxDataI;rxDataIn;rxDataQ;rxValidIn;scsCommon;scsSSB;sib1DemodStatus;sib1En;sib1FrequencyOffset;sib1Grid;sib1GridParams;sib1GridValid;ssbDecodeValid;ssbGrid;ssbGridValid;ssbIndex3LSB;ssbIndex3Lsb;ssbPattern;ssbReport;ssbReportIn;ssbReportLSBs;ssbReportMSBs;ssbReportOut;ssbReportValid;sssCorr;sssCorrelation;sssThresh;sssThreshold;start;startSIB1Demod;status;tdata;timingOffset;tlast;tready;tvalid;unpack complex;validOut

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Constant;Counter;DataTypeConversion;Delay;Demux;Detect Decrease;Display;EnablePort;From;Gain;Goto;HDL Counter;Info;Inport;Logic;ManualSwitch;ModelReference;MultiPortSwitch;Mux;Outport;RealImagToComplex;S-Function;Signal From Workspace;Sum;Tapped Delay Line;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous

PRODUCT:
DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices

EXTERNALFILE_REFERENCE:
nrhdlDDCFR1Core___Model_Block___nrhdlPolarDecodingChainCore___Model_Block___nrhdlSIB1DemodulationFR1Core___Model_Block___nrhdlSSBDecodingCore___Model_Block___nrhdlSSBDetectionFR1Core___Model_Block___


MODELNAME: zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL_hostUDPReceive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL_hostUDPReceive.slx
BLOCKTYPE_FREQUENCY: 1;2;12;1;4;1;8;1;8;6;7;18;1;1;2;1;31;2;1;22;1;2;14;9;6
CHECKSUM: 8AFF9ADF432FF4218CF34236F1206E66
PRODUCT: DSP System Toolbox;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
convert to Hz Interprets first entry in PSS Report table. In demodulation mode only one entry is returned and this is when the model is triggered to stop. convert to Hz convert to Hz Stop Logic  Zynq Radio 5G NR SIB1 Recovery Host UDP Receive Model Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Add Constant;Bit Concat;Bit Slice;Cast To Boolean;Cast To Double;Cell ID;Compare To Zero;Constant;Counter;Data Type Conversion;Disable;Display Cell Information;Divide;Divide by K to convert Threshold to Energy;Enable;Gain;Interpret Final PSS Report;Interpret SSS Report;Kssb;Log;Log Grid;Multiport Switch;NR-RSSI;NR-RSSI (dBm);PSS SNR;PSS SNR (dB);PSS_Correlation;PSS_FrequencyOffset;PSS_Threshold;PSS_TimingOffset;PSS_nCellID;Parse MIB;Process & Log MIB Report;Process & Log PSS Reports;Process & Log SIB1 Report;Process & Log SSS Report;Process & Log Signal Quality Report;Reference;SIB1 Recovery Count;SS-RSRP;SS-RSRP (dBm);SS-RSRQ;SS-RSRQ (dB);SS-SINR;SS-SINR (dB);SSS SNR (dB);SSS_SNR_DB;SelectedPSSReport_CorrelationStrength;SelectedPSSReport_FrequencyOffset;SelectedPSSReport_PSSID;SelectedPSSReport_TimingOffset;SelectedPSSReport_pssThreshold;Selector;Stop Simulation;Stop after successful SIB1 recovery;SubSystem;Subtract;Terminator;To Workspace;UDP Receive Grid;UDP Receive MIB Reports;UDP Receive PSS Reports;UDP Receive SIB1 Reports;UDP Receive SSS Reports;UDP Receive Signal Quality Report;cellBarred;cellID;dmrsTypeAPos;gridformat;hrf;iSSB;intraFreqResel;measurementsReport;mibBits;pbchPayload;reportFormat;scsCommon;selectedParameters_CorrelationStrength;selectedParameters_FrequencyOffset;selectedParameters_SubCarrierSpacing;sfn;sib1Config;sssCorrelation;sssReport;sssThreshold

BLOCKTYPE:
Bias;Bit Concat;Bit Slice;Compare To Zero;Constant;Counter;DataTypeConversion;Demux;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;Math;MultiPortSwitch;Outport;Product;S-Function;Selector;Stop;Sum;Terminator;ToWorkspace;UDP Receive


MODELNAME: zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSW5GNRSIB1RecoveryAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 9;11;1;1;3;16;1;7;2;1;3;9;43;10;9;3;7;39;2;27;1;142;3;1;1;1;3;110;10;2;9;4;1;1;1;14;6;2;1;1
CHECKSUM: 9C3E8E6106599D471DBC318E1CB6FFAB
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Generated by HDL Workflow Advisor on 24-Feb-2023 12:23:40 Send to Host SW Process HW results HW Core SW Restart SW Control Logic Select Hardware Board Target Open host model  Double click the block to open the host model.  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required SDR Receiver to ARM Zynq Radio 5G NR SIB1 Recovery Software Interface Model Alternate Receiver block- select the correct block for your hardware Copyright 2020-2023 The MathWorks, Inc. SW Signal Quality Measurements

BLOCK:
 Demux ; SFunction ; Terminator ;5G SIB1 Recovery HDL;AD936x Receiver;AND;AXI4 Read;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_NCellID;AXI4SlaveRead_bchStatus;AXI4SlaveRead_detectionStatus;AXI4SlaveRead_pbchPayload;AXI4SlaveRead_pbchStatus;AXI4SlaveRead_sib1DemodStatus;AXI4SlaveRead_ssbIndex3LSB;AXI4SlaveRead_sssCorr;AXI4SlaveRead_sssThresh;AXI4SlaveWrite;AXI4SlaveWrite_Lmax;AXI4SlaveWrite_NCellID;AXI4SlaveWrite_centerFrequency;AXI4SlaveWrite_frequencyOffset;AXI4SlaveWrite_minChanBW;AXI4SlaveWrite_mode;AXI4SlaveWrite_scsSSB;AXI4SlaveWrite_sib1En;AXI4SlaveWrite_ssbPattern;AXI4SlaveWrite_start;AXI4SlaveWrite_timingOffset;Add Constant;Algorithm Scope;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Cast;Cast To Boolean;Cast To Double;Cell Search Controller;Center Frequency;Compare To Constant;Complex to Real-Imag;Constant;DMRSTypeAPosition;Data Converter;Data Type Conversion;DataTypeConversion;Delay;Detect Increase;Enable;Extract Grid;FMCOMMS5 Receiver;From;Gain;Goto;Grid Construction;In;Info;Lmax;MATLAB Function;MIB Report;Multiport Switch;NCellID;NFrame;NOT;NSlot;Out;PDCCH Processing;PDCCHConfigSIB;PDSCH Processing;Parse MIB;Rate Transition;Real-Imag to Complex;Reference;SIB1 Processing;SIB1 Recovery;SIB1 Scope;SIB1 Status Scope;SSB Data In;SSB Data Out;SSB Measurements Scope;SSS Report;Selected Hardware Board Target;SelectedPSSReport;SelectedParams;Selector;Signal Quality Measurements;Signal Quality Report;Start/Restart Pulse Generator;SubSystem;Subsystem;Terminator;UDP Send;UDP send MIB report;UDP send PSS report;UDP send SIB1 report;UDP send SSB grid;UDP send SSS report;UDP send Signal Quality Measurements;Unit Delay Enabled Synchronous;Unit conversion;Vector Concatenate;bchStatus;bufferGridData;cellID;cellid;centerFrequency;centreFrequency;constant;coresetNRB;dataIn;dataOut;dciCRC;dciDone;dciVector;dci_vector;decodeStatus;detectionStatus;enable;enablePDSCH;enablePhaseComp;fOffset;firstOrSecondSlot;frequencyOffset;gridConstruct;gridData;gridDataIn;gridDataOut;gridReady;gridValid;hwMode;hwStart;hwStatus;idxLookup;k_SSB;mibReportValid;mibReportVector;minChanBW;minChanBW_idx;minChanBw;minChannelBW;mode;nCellID;nSlot;numPSSout;parsedMIB;pbchPayload;pbchStatus;pdcchdone;pdschDone;pdschdone;permittedSCS;permittedssbPatterns;processingDone;reportVector;reportVectorValid;report_data;reset;resetHold;restart;rx2SlotGrid;scsCommon;scsSSB;scsSSB_idx;scs_common;scs_ssb;searchControl;selectedParams;selectedReport;setupFreqDependantParams;sib1Bits;sib1CRC;sib1DemodStatus;sib1En;sib1Grid;sib1GridDataOut;sib1GridStatus;sib1Gridvalid;sib1Valid;sib1bits;sigQualMeasurements;sigQualReportVector;signalQualityMeasurements;slowReset;ssbData;ssbGrid;ssbGridData;ssbGridValid;ssbIndex;ssbIndex3LSB;ssbPattern;ssbValid;sssCorr;sssReportValid;sssReportVector;sssThresh;start;subcarrierSpacing;sw_data;tOffset;timingOffset;unpack report;validIn;validOut

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Bias;Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Increase;EnablePort;From;Gain;Goto;Info;Inport;Logic;MATLABSystem;ManualSwitch;Model Source;MultiPortSwitch;Outport;RateTransition;RealImagToComplex;S-Function;Scope;Selector;Signal From Workspace;System Start;Terminator;UDP Send;Unit Delay Enabled Synchronous;comm.SDRRxAD936x;matlabshared.libiio.axistream.read

PRODUCT:
DSP System Toolbox;Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWADSBAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWADSBAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 2;2;2;1;1;1;12;4;26;2;1;2;3;5;1;3;4;1;36;6;1;2;1;27;1;2;1;2;3;2;1;4;2;1;9
CHECKSUM: 08102BAED5990F0867D5F32E5A80DC93
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
delay of the approximation is 4 clock clyces - delay valid signal to account for this sqrt(I^2+Q^2) can be approximated as |L|+0.4*|S|, where |L| is the absolute value of the larger of I or Q, and |S| is the absolute value of the smaller of I or Q. See |L|+0.4|S| Algorithm on page 238 in Digital Signal Processing in Communication Systems by Marvin Frerking.  Type Conversion from 12bit int16to 16bit_15 (0:1) ADS-B data is only present on the real channel, imaginary samples are all set to 0 Samples to Frames  HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364 Hardware Generation Model  Copyright 2016-2020 The MathWorks, Inc. Tx and Rx Hardware Algorithms Rx ARM Algorithm Simulate RF-card Bit-Shift

BLOCK:
; Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Abs;ActivateBP;Add;Bit Process;Bit Shift;Bit-Shift;CalcSyncCorr;Calculate Threshold;Compare To Constant;Compare To Zero;Complex Modulus;Complex to Real-Imag;Compute CRC and Frame validation;Constant;CurrentBit;Data Type Conversion;Delay;Delay Enable;Deserializer1D;Discrete FIR Filter;Enabled Delay;Falling Edge Detector;Frame Bit Out;From;Gain;General CRC Syndrome HDL Optimized;Goto;HDL Counter;HDLRxIpCore;HDLTxIpCore;HDL_ADSB;ImagIn;In;Info;Logical;Logical Operator;MATLAB Function;MagOut;MinMax;Multiport Selector;Out;PrepInputs;Product;Real-Imag to Complex;RealIn;Reference;Relational Operator;Reset;Rising Edge Detector;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_In;RxValid_Out;Scaling;Scope;Signal Specification;State Control;SubSystem;Subtract;Switch;SyncCorr;Tapped Delay;Terminator;Threshold;Threshold ;Timing Control;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxTransmitPeriod;TxValid_In;TxValid_Out;Valid Generation;ValidBit;ValidFrame;ValidOut;XOR;dataIn;dataLength;dataOut;dataReceived;dataValidIn;in;out;signal spec;validIn;validOout;validOut

BLOCKTYPE:
Abs;Bit Shift;Compare To Constant;Compare To Zero;Complex Modulus;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Deserializer1D;DiscreteFir;From;Gain;General CRC Syndrome Detector HDL Optimized;Goto;HDL Counter;Info;Inport;Logic;Lookup_n-D;MinMax;Multiport Selector;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Scope;SignalSpecification;StateControl;Sum;Switch;Tapped Delay Line;Terminator

PRODUCT:
Communications Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWADSBAD9361AD9364SL_UDP_HostPrintout
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWADSBAD9361AD9364SL_UDP_HostPrintout.slx
BLOCKTYPE: Demux;Info;Inport;S-Function;Terminator;UDP Receive
BLOCKTYPE_FREQUENCY: 1;1;2;1;1;1
CHECKSUM: F855017619A6056A3E499BFBC777A0BA
PRODUCT: MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Demux ; SFunction ; Terminator ;Info;MATLAB Function;Reference;SubSystem;UDP Receive;dataLength;dataReceived


MODELNAME: zynqRadioHWSWADSBAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWADSBAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 2;1;1;3;2;1;1;1;5;4;1;1;1;1
CHECKSUM: 69A7360B8E82342CE663B368F25583A5
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Generated by HDL Workflow Advisor on 01-Aug-2018 14:26:30 Alternate transmitter and Receiver blocks- select the correct block for your hardware Zynq Radio Software Interface Model SDR Receiver to ARM Algorithm ARM Algorithm to SDR Transmitter ARM Interface to HW User Logic Copyright 2016-2019 The MathWorks, Inc. Open host model  Double click the block to open the host model and display detected ADS-B information  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required Select Hardware Board Target

BLOCK:
AD936x Receiver;AD936x Transmitter;AXI4LiteRead;AXI4LiteWrite;AXI4Lite_Write_Threshold;AXI4Lite_Write_Threshold_DTC;AXI4Lite_Write_TxTransmitPeriod;AXI4Lite_Write_TxTransmitPeriod_DTC;AXI4Reset;AXI4ResetModelSource;Complex to Real-Imag;Constant;Decode & Display HWSW;Enable;FMCOMMS5 Receiver;FMCOMMS5 Transmitter;HDL_ADSB;In;Info;Reference;Scaling;Selected Hardware Board Target;SubSystem;Subsystem;Terminator;Threshold;Threshold ;TxTransmitPeriod;UDP Send

BLOCKTYPE:
AXI4-Interface Write;AXI4-Lite/AXI4 Interface;ComplexToRealImag;Constant;DataTypeConversion;EnablePort;Gain;Info;Inport;MATLABSystem;Model Source;System Start;Terminator;UDP Send

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWAXI4StreamAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWAXI4StreamAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 2;1;3;2;1;2;12;6;25;1;2;3;3;3;1;33;7;2;1;25;4;1;1;1;1;2;1;1;2;13;3
CHECKSUM: 8AA8AACE37EE112C24819035DB7C8953
PRODUCT: DSP System Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
SR AND - OR Latch Ignore any Backpressure exerted on DUT Generate new Valid signal Compute power of received signal Compute power of transmitted signal SR AND - OR Latch Select to transmit ramp or data stored in RAM Reset counter before and after loading new data Tx trigger  Tx RAM controller Dont apply backpressure to the RF Front End Shift left to prepare for 16-bit to 12-bit MSB interface at DAC Tx and Rx hardware algorithms Simulate model control Display simulation results Load Tx Data to RAM  HW/SW Co-Design AXI4-Stream Hardware Generation Model Copyright 2020 The MathWorks, Inc.

BLOCK:
AND;AXI4S_Data_In;AXI4S_Data_Out;AXI4S_Tready_In;AXI4S_Tready_Out;AXI4S_Valid_In;AXI4S_Valid_Out;AXIS_txData;AXIS_txWrite;Add;Bit Concat;Bit Shift;Bit Slice;Cast;Cast To Boolean;Compare To Constant;Complex to Real-Imag;Constant;Data Type Conversion;DataIn;Delay;Detect Change;Detect Increase;From;Goto;HDL Counter;HDL_DUT;In;Info;Max Tx Count;MaxTxCount;Multiport Switch;Mux;NOT;OR;Out;Product;Q;R;Real-Imag to Complex;Reference;Relational Operator;Rx;Rx1_Data_I_In;Rx1_Data_I_Out;Rx1_Data_Q_In;Rx1_Data_Q_Out;Rx2_Data_I_In;Rx2_Data_I_Out;Rx2_Data_Q_In;Rx2_Data_Q_Out;Rx_Data_In;Rx_Data_P;Rx_Tready_In;Rx_Valid_In;Rx_Valid_Out;S;SR-Latch;Scope;Serializer1D;Shift Arithmetic;Simple Dual Port RAM;Simulate 12-to-16bit ADC interface;Simulate 16-to-12bit DAC interface;Step;SubSystem;Terminator;Tx;Tx Data;Tx Select;Tx Start;Tx1_Data_I_In;Tx1_Data_I_Out;Tx1_Data_Q_In;Tx1_Data_Q_Out;Tx_Data_In;Tx_Data_Out;Tx_Data_P;Tx_Tready_Out;Tx_Valid_In;Tx_Valid_Out;Unit Delay;Valid_Out;Write Tx Data;maxTxCount;txSEL;txSel;txStart

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bit Slice;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Detect Change;Detect Increase;From;Goto;HDL Counter;Info;Inport;Logic;MultiPortSwitch;Mux;Outport;Product;RealImagToComplex;RelationalOperator;Scope;Serializer1D;Signal From Workspace;Simple Dual-port RAM;Step;Sum;Terminator;UnitDelay


MODELNAME: zynqRadioHWSWAXI4StreamAD9361AD9364SL_UDP_host_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWAXI4StreamAD9361AD9364SL_UDP_host_interface.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: Bit Slice;DataTypeConversion;EnablePort;Info;Inport;Outport;Scope;UDP Receive
BLOCKTYPE_FREQUENCY: 2;2;1;1;1;2;1;1
CHECKSUM: 4FF515246E979BAA5F0631B497593794
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Bit Slice;Cast;Data unpacking;DataIn;Enable;Info;Reference;Rx Power;SubSystem;Time Scope;Tx Power;UDP Receive


MODELNAME: zynqRadioHWSWAXI4StreamAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWAXI4StreamAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 3;1;10;3;2;1;1;10;1;2;2;1;1;1;1;3;1;1;1;1;1;1
CHECKSUM: CA39910C267529C2ED9F636A39484BAF
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Generated by HDL Workflow Advisor on 10-Dec-2020 10:55:47 Shift left to prepare for 16-bit to 12-bit MSB interface at DAC Loads selected waveform on initialization  2. Select data source Alternate Transmitter and Receiver blocks. Select the correct block for your hardware  Zynq-7000 IIO Radio Software Interface Model: zynqRadioHWSWAXI4StreamAD9361AD9364SL_interface SDR receiver configuration SDR transmitter configuration ARM Interface to HW User Logic  Double click the block to open the host model. Open host model Copyright 2020 The MathWorks, Inc.  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required Select Hardware Board Target  1. Select waveform to load  3. Toggle switch to transmit waveform

BLOCK:
AD936x Receiver;AD936x Transmitter;AXI4-Stream IIO Read;AXI4-Stream IIO Write;AXI4Reset;AXI4ResetModelSource;AXI4SlaveWrite;AXI4SlaveWrite_maxTxCount;AXI4SlaveWrite_txSel;AXI4SlaveWrite_txStart;Chirp data;Constant;Data;DataTypeConversion;Detect Change;Enable;FMCOMMS5 Receiver;FMCOMMS5 Transmitter;HDL_DUT;Info;Internal ramp;MaxTxCount;Multiport Switch;OR;Reference;Sawtooth data;Selected Hardware Board Target;Send via UDP;Signal Select;Sinusoid data;Step;SubSystem;Subsystem;Switch;Terminator;Trigger;Triggered write;UDP Send;Waveform;Waveform from RAM;Write waveform to FPGA RAM;data;maxTxCount;txSel;txStart

BLOCKTYPE:
AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Constant;DataTypeConversion;Detect Change;EnablePort;Info;Inport;Logic;MATLABSystem;ManualSwitch;Model Source;MultiPortSwitch;Step;System Start;Terminator;TriggerPort;UDP Send;comm.SDRRxFMCOMMS5;comm.SDRTxFMCOMMS5;matlabshared.libiio.axistream.read;matlabshared.libiio.axistream.write

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Signal Processing Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWDPDPreprocessTestbench
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWDPDPreprocessTestbench.slx
BLOCKTYPE_FREQUENCY: 12;2;1;5;6;7;22;1;3;23;1;1;15;174;11;1;1;1;2;3;15;2;1;170;25;4;1;150;1;7;1;4;11;3;5;10;9;30;3;4;2
CHECKSUM: CAA90C9073052BACEEAEF94D5235BC91
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 Deep Learning hand shake logic with external memory Store abs^2 of input data Store abs of input data Store input data Store abs^3 of input data Store abs^4 of input data Range of x_f=[1,4)  DPD Preprocessing  DPD DUT - Preprocess with deep learning hand shake logic  Copyright 2023 The MathWorks, Inc.  DPD Preprocess DUT

BLOCK:
 Demux ; SFunction ; Terminator ; ackIn==;1-D Lookup Table;AND;AXI4S_Slave_FIFO;AXIM Write Conroller;AXIReadCtrlIn;AXIReadCtrlInDDR;AXIReadCtrlInDL;AXIReadCtrlOut;AXIReadCtrlOutDDR;AXIReadCtrlOutDL;AXIReadData;AXIReadDataDDR;AXIReadDataDL;AXIReadDataIn;AXIReadDataOut;AXIReadDataOutDDR;AXIReadDataOutValid;AXIReadDataValid;AXIReaddataDL;AXIReaddataOutDDR;AXIWrCtrlIn;AXIWrCtrlOut;AXIWrData;AXIWriteCtrlIn;AXIWriteCtrlInDDR;AXIWriteCtrlInDL;AXIWriteCtrlOut;AXIWriteCtrlOutDDR;AXIWriteCtrlOutDL;AXIWriteData;AXIWriteDataDDR;AXIWriteDataDL;AXIWriteDataOut;AXIWritedata;AckGen;Add;B;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;BusCreator;Compare To Constant;Compare To Zero;Complex to Real-Imag;Constant;DDR Memory;DDR Read Conroller;DDRData;DL Handshake Logic Ext Mem;DL IP Core;DL Regs;DLDone;DPD Preprocess Algorithm;DPD Preprocess DUT;DUTProcStart;DUTProcstart;Data Store Read;Data Store Write;Data Type Conversion;DataAvailable;Delay;Dual Port RAM;EdgeDetection;Enable;FIL Samples To Frame;FWFT FIFO;Float Typecast;FunctionEvaluation;G;Gain;HDL Counter;HDL FIFO;In;Info;Input Generation;Logical Operator;MATLAB Function;MagnitudeSquared;Multiply;Multiport Switch;NeuralNetwork;Out;PL DDR;Predict;Product;RAMStorage;RangeReconstruction;RangeReduction;Read;Read Control;Read Control DL;Read DL Registers;Read From DDR;Read Input Registers;Real-Imag to Complex;Reference;S;Shift Arithmetic;Signal From Workspace;Simple Dual Port RAM;SqrtEval;SqrtImplementation;SubSystem;Subtract;Switch;Terminator;To Workspace;Trigger DL Input Next;Trigger Input Next;Unit Delay;Unpack;Upsample;ValAddEnb;ValwrLenCnt;Verify Neural Network;Verify Preprocess DUT Output;WrFIFOReady;Write;Write Control;Write To DDR;abs;ack;ackIn;ackIn Posedge Detect;ackIn_d;ackIn_d1==;ackOut;afull;axiWrLen;axiWrLen!=;axiWrLen-1==cnt & axiWrLen!=0 ;axiWrLen==cnt+;axi_rd_add;axi_rd_addr;axi_rd_avalid;axi_rd_dready;axi_rd_len;axi_rd_rdy;axi_rd_ready;axi_rd_val;axi_wr_en;axi_wr_length;axim_ack;axim_rd_addr;axim_rd_aready;axim_rd_avalid;axim_rd_dready;axim_rd_dvalid;axim_rd_len;axim_wr_ack;axim_wr_addr;axim_wr_enb;axim_wr_len;axim_wr_ready;burstLen;burst_len;count_out;data;dataIn;dataInImag;dataInReal;dataOut;data_i;data_in;data_o;data_valid;datain;ddr_ack_d;ddr_read_done;ddr_wr_addr;ddr_wr_en;ddr_write_done;ddrframe;dl_regs;edgeDet;elementCalculator;empty_o;enable;exp_f;exp_fIn;exp_fOut;f;frame;full;if cnt < axiWrLen;inOut;inValid;inp;inpDelayed;inputAddr;inputData;inputDataR;inputNext ;inputOffAddr;inputSize;inputValid;leadingZeroDetector;num;offsetAddr;out;outValid;pack data;packedData;packedIn;packedInput;pass;passIn;passOut;pingPongMemory;pop;preprocessDUT;preprocessOut;preprocessValid;push;ram_addr;ram_rd_addr;ram_rd_data;ram_rd_val;ram_rd_valid;ram_wr_addr;ram_wr_enb;ram_wr_enb cond;rdLogic;rd_addr;rd_aready;rd_avalid;rd_control;rd_dout;rd_dvalid;rd_len;readInputStart;samplesToFrames;start;state_machine;u;vaidOut;valAddEnb;valid;validGenerator;validIn;validOut;valid_out;wasted_cycle_cnt;wrComplete;wrDone;wrEnb;wr_ack;wr_addr;wr_addr-;wr_addr_base;wr_complete;wr_data;wr_din;wr_done;wr_en;wr_enb;wr_len;wr_leng;wr_ready;wr_valid;x;x_f;y_f

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bit Slice;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;DataStoreRead;DataStoreWrite;DataTypeConversion;Delay;Demux;Dual-port RAM;EnablePort;FIL Samples To Frame;FloatTypecast;Gain;HDL Counter;HDL_FIFO;Info;Inport;Logic;Lookup_n-D;MultiPortSwitch;Outport;Predict;Product;RealImagToComplex;RelationalOperator;S-Function;Signal From Workspace;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;UnitDelay;Upsample

PRODUCT:
DSP System Toolbox;Deep Learning Toolbox;Fixed-Point Designer;Simulink;SoC Blockset Support Package for Xilinx Devices;Wireless HDL Toolbox


MODELNAME: zynqRadioHWSWDVBS2PLHeaderRecoveryAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWDVBS2PLHeaderRecoveryAD9361AD9364SL.slx
CHECKSUM: 652DBDCB3A71072F9D3ACD1B5D3A31B5
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: dvbs2hdlSyncPLHeaderRecoveryCore.slx___Model_Block___
ANNOTATION:
Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2)  Add Block is used to obtain integer index to Lookup Table  HDL AWGN Generator assumes input signal power is unity. As the Es value is maintained unity in the input waveform but not the signal power, EsNodB is directly connected to snrdB to generate noise to maintain proper EsNodB.  Fixed point precision loss warnings are supressed in Mask Init Callback Unused ports  TxDataI_In, TxDataQ_In, and TxValid_In are nonfunctional ports. These ports are terminated inside the subsystem. Received Signal  Zynq Radio DVB-S2 PL Header Recovery Hardware Model Copyright 2021 The MathWorks, Inc.  All the constellations are displayed during simulation. Status Signals to Monitor Outside FPGA  The terminated outports are connected to the scope in the software model to view the constellation based on the outputConstellation inport. Constellation View for Software Interface Model  nframesSynced value resets when the rstDisplay inport is true. Input frequency offset and phase offset for the channel inside the model.  CFO range: -740e3 to 740e3 CPO range: -180 to 180 degrees  enbCCFO port enables the coarse CFO estimation. Setting this to low will disable the CFO estimation and reset it.  enbFCPO port enables the fine CPO estimation.  rstDisplay port resets the nframesSynced display.  EsNodB range: 10 to 30 dB  RxDataI_In, RxDataQ_In, and RxValid_In are input signals received either from RF Front End or internal Tx-Rx loopback based on the status of overAir signal.  Set the MODCOD parameter value to feed the DVB-S2 PL Header Recovery HDL subsystem.  Set the Constellation To View parameter.  Set overAir to false to feed the txWaveform to Rx internally through the channel inside the model.  Set the enableNoise port to true or false. If enableNoise is true and overAir is false, the EsNodB value is set inside the model.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AWGN;Add;Bit Concat;Bit Shift;Bitwise Operator;Bus Selector;CFO;CPO;Channel;Compare To Constant;Complex to Real-Imag;ConcatandExtract;Conj;Constant;Constellation;Constellation Plots;Control Scope;DAC Output;DVB-S2 PL Header Recovery HDL;Data Type Conversion;Data Type Duplicate;Delay;Digital Automatic Gain Control;Discrete FIR Filter HDL Optimized;Display;Downsample;EnNoise;Enable;Error Detector;EsNodB;Extract Bits;From;FunctionEvaluation;Gain;Gaussian Noise With Given Variance;Goto;HDL AWGN Generator;HDL Counter;In;Info;Information Decoder;LUT Based Tx;Logical Operator;Loop Filter;Manual Switch;Multiport Switch;NCO HDL Optimized;Out;OverAir;PL Header Recovery;Product;RangeReconstruction;RangeReduction;Real-Imag to Complex;Ref;Reference;Repeat;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_In;RxValid_Out;Shift Arithmetic;SinCos;Sine HDL Optimized;Spectrum Analyzer;SqrtEval;SqrtImplementation;SubSystem;Subsystem;Subtract;Switch;TausURNG;TausUniformRandGen;Terminator;Tx-LUT_Channel_Rx;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxSymData;TxSymValid;TxValid_In;TxValid_Out;Unit Delay Enabled Synchronous;Unit Variance Gaussian Noise;Upsample;a;awgn;b;coarseFreqEst;consteData;consteSwitch;consteValid;constedata;constevalid;dB to Linear Scale Converter;dataIIn;dataIn;dataIout;dataOut;dataQIn;decodedFECFrame;decodedMODCOD;diagBus;e;enNoise;enableNoise;enb;enbCCFO;enbFCPO;endOfLUT;endOfPLSC;err;estVar;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;fecFrame;finalOut;fineFreqEst;freqEst;g;g1(16,15);gain;headerInfo;leadingZeroDetector;log;logImplementation;modcod;modcodIn;modcodOut;modcodidx;nEstCoarseFreq;nEstFineFreq;nEstFreq;nframesSynced;noiseVar;outputConstellation;overAir;pass;passIn;passOut;rst;rstCCFO;rstDisp;rstDisplay;rstFCPO;rxExtData;rxExtValid;rxIn;snrdb;sqrt(noisePow/2);switch;symbSyncOut;txDataOut;txLUT;txOut;txValidOut;u;u0(16,16);u0(48,48);u1(16,16);validIn;validOut;var;varOut;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bitwise Operator;BusSelector;Compare To Constant;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;DownSample;EnablePort;Extract Bits;From;Gain;Goto;HDL Counter;Info;Inport;Logic;Lookup_n-D;ManualSwitch;Math;ModelReference;MultiPortSwitch;NCO;Outport;Product;RealImagToComplex;Repeat;S-Function;Sine and Cosine HDL optimized block;SpectrumAnalyzer;Sum;Switch;Terminator;Unit Delay Enabled Synchronous;Upsample

BLOCKTYPE_FREQUENCY:
14;1;19;21;6;48;3;23;2;31;3;166;2;1;7;3;3;2;13;11;9;25;1;146;32;32;5;1;1;3;1;153;11;3;9;2;2;1;17;10;7;1;2

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWDVBS2PLHeaderRecoveryAD9361AD9364SL_HostUDPReceive
ANNOTATION: Copyright 2021 The MathWorks, Inc. Zynq Radio DVB-S2 PL Header Recovery Host UDP Receive Model
BLOCKTYPE_FREQUENCY: 2;1;16;1;8;1;3;3;7;3;2;1
CHECKSUM: B49CFE0C47E5FBE82C07E78F418B625F
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWDVBS2PLHeaderRecoveryAD9361AD9364SL_HostUDPReceive.slx

BLOCK:
Compare To Constant;Constellation Diagram;Control Scope;Data Type Conversion;Demux;Diagnostic Viewer;Display;Enable;Gain;In;Reference;SubSystem;To Workspace;UDP Receive;Unit Delay Enabled Synchronous;Visualize Constellation;coarseFrequency;coarsePLUSfineFrequency;decodedFECFrame;decodedMODCOD;estimatedVariance;fineFrequency;nframesSynced;u

BLOCKTYPE:
Compare To Constant;ConstellationDiagram;DataTypeConversion;Demux;Display;EnablePort;Gain;Inport;Outport;ToWorkspace;UDP Receive;Unit Delay Enabled Synchronous


MODELNAME: zynqRadioHWSWDVBS2PLHeaderRecoveryAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWDVBS2PLHeaderRecoveryAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 7;10;1;1;8;30;2;1;1;1;28;2;5;1;14;1;2;1;1
CHECKSUM: D3C4D31738C14D98D44F226B48A8EA96
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Open host model Select Hardware Board Target  Double-click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required.  Double-click the block to open the host model. Alternate transmitter and Receiver blocks- select the correct block for your hardware  Zynq Radio DVB-S2 PL Header Recovery Software Interface Model  Copyright 2021 The MathWorks, Inc.

BLOCK:
AD936x Receiver;AD936x Transmitter;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_decodedFECFrame;AXI4SlaveRead_decodedMODCOD;AXI4SlaveRead_estVar;AXI4SlaveRead_nEstCoarseFreq;AXI4SlaveRead_nEstFineFreq;AXI4SlaveRead_nEstFreq;AXI4SlaveRead_nframesSynced;AXI4SlaveWrite;AXI4SlaveWrite_CFO;AXI4SlaveWrite_CPO;AXI4SlaveWrite_EsNodB;AXI4SlaveWrite_enableNoise;AXI4SlaveWrite_enbCCFO;AXI4SlaveWrite_enbFCPO;AXI4SlaveWrite_modcodidx;AXI4SlaveWrite_outputConstellation;AXI4SlaveWrite_overAir;AXI4SlaveWrite_rstDisplay;CFO;CPO;Constant;DVB-S2 PL Header Recovery HDL;Data Type Conversion;DataTypeConversion;Display;Enable;EsNodB;FMCOMMS5 Receiver;FMCOMMS5 Transmitter;Gain;In;Info;Manual Switch;Reference;Selected Hardware Board Target;Send To Host Via UDP;SubSystem;UDP Receive Model;UDP Send;Vector Concatenate;consteDiag UDP Send;decodedFECFrame;decodedMODCOD;enableNoise;enbCCFO;enbFCPO;estVar;modcod;nEstCoarseFreq;nEstFineFreq;nEstFreq;nframesSynced;outputConstellation;overAir;rstDisplay;switch

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Concatenate;Constant;DataTypeConversion;Display;EnablePort;Gain;Info;Inport;MATLABSystem;ManualSwitch;Model Source;Outport;System Start;UDP Send;comm.SDRRxAD936x;comm.SDRTxAD936x

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWLTECellScannerAD9361AD9364SL_host_MIB_logger
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTECellScannerAD9361AD9364SL_host_MIB_logger.slx
BLOCKTYPE: Demux;EnablePort;Info;Inport;S-Function;Terminator;UDP Receive
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;1;1
CHECKSUM: F8517A91EF7DE15591A064196DA15A75
PRODUCT: MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Demux ; SFunction ; Terminator ;Display Cell Information;Display cell information;Enable;In;Info;Reference;SubSystem;UDP Receive;u


MODELNAME: zynqRadioHWSWLTECellScannerAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTECellScannerAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 12;2;1;1;2;25;2;3;1;6;6;1;31;1;1;40;3;1;1;1;7;1;1;1
CHECKSUM: 618E88874D84412E9B28F2AE96523648
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
UDP To Host This example doesnt use AXI-Stream output. Set all to outputs to zero. Generated by HDL Workflow Advisor on 20-Aug-2019 17:46:23 The cell scanner model should not be used with internal test data SDR Receiver to ARM Algorithm  LTE MIB Cell Scanner Select Hardware Board Target  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required Alternate Receiver block - select the correct block for your hardware  Double click the block to open the host model and display detected MIB information Copyright 2017-2020 The MathWorks, Inc. Open cell scanner host model

BLOCK:
 Demux ; SFunction ; Terminator ;AD936x Receiver;AXI4LiteRead;AXI4LiteWrite;AXI4Lite_Read_CellRefIP;AXI4Lite_Read_CellRefIP_DTC;AXI4Lite_Read_NCellID;AXI4Lite_Read_NCellID_DTC;AXI4Lite_Read_NDLRB;AXI4Lite_Read_NDLRB_DTC;AXI4Lite_Read_NFrame;AXI4Lite_Read_NFrame_DTC;AXI4Lite_Read_Ng;AXI4Lite_Read_Ng_DTC;AXI4Lite_Read_PHICH;AXI4Lite_Read_PHICH_DTC;AXI4Lite_Read_TDDMode;AXI4Lite_Read_TDDMode_DTC;AXI4Lite_Read_cellDetected;AXI4Lite_Read_cellDetected_DTC;AXI4Lite_Read_cellSearchDone;AXI4Lite_Read_cellSearchDone_DTC;AXI4Lite_Read_freqEst;AXI4Lite_Read_freqEst_DTC;AXI4Lite_Read_mibDetected;AXI4Lite_Read_mibDetected_DTC;AXI4Lite_Read_mibError;AXI4Lite_Read_mibError_DTC;AXI4Lite_Write_externalDataSel;AXI4Lite_Write_externalDataSel_DTC;AXI4Lite_Write_start;AXI4Lite_Write_start_DTC;AXI4Reset;AXI4ResetModelSource;Add;CellID;CellRefIP;CellRefP;Center Freq;Coarse Frequency Search Controller;Concat and Send to Host;Data Type Conversion;Delay;Enable;FMCOMMS5 Receiver;From;Goto;In;Info;LTE Cell Scanner and Coarse Frequency Search Controller;LTE Scan Controller;LTE_MIB_HDL;MIBDetected;NCellID;NDLRB;NFrame;Ng;Number of MIB retries;Out;PHICH;Reference;Select external data;Selected Hardware Board Target;Send every N clock ticks;Signal Specification;SubSystem;Subsystem;TDDMode;Terminator;UDP Send;Vector Concatenate;cellDetected;cellSearchDone;coarseFreq;coarseFreqDone;coarseModeDone;coarseModeStart;coarseStart;enable;externalDataSel;fc;fineOffsetEst_in;freqEst;frequency estimate;hostPacket;maxFreq;mibDetected;mibError;minFreq;numMIBRetries;sendPacket;start;startIn;startOut

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Concatenate;Constant;DataTypeConversion;Delay;Demux;EnablePort;From;Goto;Info;Inport;MATLABSystem;Model Source;Outport;S-Function;SignalSpecification;Sum;System Start;Terminator;UDP Send;Update center frequency;comm.SDRRxAD936x

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWLTEMIBDetectorAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTEMIBDetectorAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 1;1;1;3;1;1;11;9;19;4;2;14;1;9;1;4;2;1;59;6;1;5;2;66;1;13;4;1;1;1;2;12;1;1
CHECKSUM: 12CDBD382F9A55E3F4598FC624717AE2
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
In the software interface model, this block will be replaced with a UDP send block, and the functionality contained in this subsystem will be performed on the host. DECODING INDEXING GRID Start pulse offset, in samples @ 1.92 Msps This example doesnt use Rx data channel. Set all to outputs to zero. Rx Hardware Algorithm Copyright 2017-2020 The MathWorks, Inc. LTE MIB Recovery Using Analog Devices AD9361/AD9364 Hardware Generation Model Rx Software Algorithm To simulate ARM behaviour, downsamplers and repeat blocks are added to run it at 1KHz

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;Bus Creator;CIC Interpolation;CellRefIP;CellRefIP_out;CellRefP;CellRefP_in;Channel Equalization;Coarse Frequency Search Controller;Compare To Constant;Complex to Real-Imag;Concat and Send to Host;Constant;ControlSignals;Data Type Conversion;DataOut;Delay;Detect Rise Positive;Downlink Sync Demod;Downsample;EdgeDetect;FrameCounter;From;Front_End_FIR_Decimation;Gain;Goto;HDL LTE MIB Recovery;I_In;Info;Internal Restart Controller;LTE_MIB_HDL;Logical Operator;MATLAB Function;MIB Decoder;MIBDetected;Multiport Switch;NCellID;NCellID_in;NCellIO_out;NDLRB;NDLRB_in;NDLRB_out;NFrame;NFrame_in;NFrame_out;NcellID;Ng;Ng_in;Ng_out;Nsubframe;OFDMdata;OR;PBCH Decoder;PBCH Indexing;PHICH;PHICH_in;PHICH_out;PSSDetected;PrepInputs;PulseResync;Q_In;Rate change to 1KHz;Real-Imag to Complex;Reference;Repeat;Reset and Coarse Frequency Search Controller;Resource Grid Memory;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxDataValid_In;RxDataValid_Out;SampleCounter;Shift Arithmetic;Signal From Workspace ;Signal Specification;StartOut;StimulusSelector;SubSystem;Switch;TDDMode;TDDMode_in;TDDMode_out;Terminator;TestStimulusGenerator;Trigger;Upsample;Vector Concatenate;cellDetected;cellDetected_in;cellDetected_out;cellSearchDone;cellSearchDone_in;cellSearchDone_out;coarseDone;coarseFreq;coarseModeStart;coarseStart;dataIn;dataOut;dataSel;enable;externalDataSel;externalDataSel_in;externalDataSel_out;fineFreqOffset;fineOffset;freqEst;freqEst_in;freqEst_out;freqs;mibDetected;mibDetected_in;mibDetected_out;mibError;mibError_in;mibError_out;pulseIn;pulseOut;restart;restart controller;restartTimeout;start;startIn;startOut;startSel;triggerIn;u;validIn

BLOCKTYPE:
ArithShift;BusCreator;CIC Interpolation;Compare To Constant;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;DownSample;FIR Decimation;From;Gain;Goto;HDL Counter;Info;Inport;Logic;Lookup_n-D;ModelReference;MultiPortSwitch;Outport;RealImagToComplex;Repeat;S-Function;Scope;Signal From Workspace;SignalSpecification;Switch;Terminator;TriggerPort;Upsample

PRODUCT:
DSP System Toolbox;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices;Wireless HDL Toolbox

EXTERNALFILE_REFERENCE:
ltehdlChannelEqualizer___Model_Block___ltehdlDownlinkSyncDemod___Model_Block___ltehdlPBCHDecoder___Model_Block___ltehdlPBCHIndexing___Model_Block___ltehdlResourceGrid___Model_Block___


MODELNAME: zynqRadioHWSWLTEMIBDetectorAD9361AD9364SL_UDP_Receive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTEMIBDetectorAD9361AD9364SL_UDP_Receive.slx
BLOCKTYPE: Demux;EnablePort;Info;Inport;S-Function;Terminator;UDP Receive
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;1;1
CHECKSUM: 723693D4B0B025AAC312F3FC3FB8C4A1
PRODUCT: MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Demux ; SFunction ; Terminator ;Display Cell Information;Enable;In;Info;MATLAB Function;Reference;SubSystem;UDP Receive;u


MODELNAME: zynqRadioHWSWLTEMIBDetectorAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTEMIBDetectorAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 12;2;1;1;5;21;2;3;4;4;1;27;1;1;2;35;3;1;1;1;7;1;1;1
CHECKSUM: AD847449741317F733CC879A2B418450
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
UDP To Host This example doesnt use AXI-Stream output. Set all to outputs to zero. Generated by HDL Workflow Advisor on 20-Aug-2019 17:46:23  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required SDR Receiver to ARM Algorithm  Double click the block to open the host model and display detected MIB information Alternate Receiver block - select the correct block for your hardware Select Hardware Board Target Open host model Copyright 2017-2020 The MathWorks, Inc.  LTE MIB Recovery

BLOCK:
 Demux ; SFunction ; Terminator ;AD936x Receiver;AXI4LiteRead;AXI4LiteWrite;AXI4Lite_Read_CellRefIP;AXI4Lite_Read_CellRefIP_DTC;AXI4Lite_Read_NCellID;AXI4Lite_Read_NCellID_DTC;AXI4Lite_Read_NDLRB;AXI4Lite_Read_NDLRB_DTC;AXI4Lite_Read_NFrame;AXI4Lite_Read_NFrame_DTC;AXI4Lite_Read_Ng;AXI4Lite_Read_Ng_DTC;AXI4Lite_Read_PHICH;AXI4Lite_Read_PHICH_DTC;AXI4Lite_Read_TDDMode;AXI4Lite_Read_TDDMode_DTC;AXI4Lite_Read_cellDetected;AXI4Lite_Read_cellDetected_DTC;AXI4Lite_Read_cellSearchDone;AXI4Lite_Read_cellSearchDone_DTC;AXI4Lite_Read_freqEst;AXI4Lite_Read_freqEst_DTC;AXI4Lite_Read_mibDetected;AXI4Lite_Read_mibDetected_DTC;AXI4Lite_Read_mibError;AXI4Lite_Read_mibError_DTC;AXI4Lite_Write_externalDataSel;AXI4Lite_Write_externalDataSel_DTC;AXI4Lite_Write_start;AXI4Lite_Write_start_DTC;AXI4Reset;AXI4ResetModelSource;Add;CellRefIP;CellRefP_in;Center Frequency;Coarse Frequency Search Controller;Concat and Send to Host;Constant;Data Type Conversion;Delay;FMCOMMS5 Receiver;From;Goto;In;Info;Internal Restart Controller;LTE_MIB_HDL;MIBDetected;Multiport Switch;NCellID;NCellID_in;NDLRB;NDLRB_in;NFrame;NFrame_in;Ng;Ng_in;Out;PHICH;PHICH_in;Reference;Reset and Coarse Frequency Search Controller;Select external data;Selected Hardware Board Target;Signal Specification;SubSystem;Subsystem;TDDMode;TDDMode_in;Terminator;Trigger;UDP Send;Vector Concatenate;cellDetected;cellSearchDone;coarseDone;coarseFreq;coarseModeStart;coarseStart;enable;externalDataSel;fineFreqOffset;fineOffset;freqEst;freqs;mibDetected;mibError;restart controller;restartTimeout;start;startIn;startOut

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Concatenate;Constant;DataTypeConversion;Delay;Demux;From;Goto;Info;Inport;MATLABSystem;Model Source;MultiPortSwitch;Outport;S-Function;SignalSpecification;Sum;System Start;Terminator;TriggerPort;UDP Send;comm.SDRRxAD936x

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWLTESIB1DetectorAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTESIB1DetectorAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 1;1;3;2;7;1;1;1;9;12;50;7;1;2;8;26;1;1;66;1;36;7;1;1;123;15;12;1;1;110;1;1;24;7;1;2;5;1;1;1;16;1
CHECKSUM: 45911BF7F16C8331C461247090D5C314
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
In the software interface model, this block will be replaced with a UDP send block, and the functionality contained in this subsystem will be performed on the host. allow PDCCH decode to finish before moving on allow for nFrame calc output after MIB detected Assume smallest BW until MIB is recovered GRID DECODING INDEXING CONTROL MSB in word is newest sample 33 rows = 32 bits in TDL + current input bit (needed to form last word at correct time...) 32-word FIFO Tapped Delay Line and concatenate Count for word (to 32) Valid Bit Counter This example doesnt use AXI-Stream output. Set all to outputs to zero.  SIB1 Bits available here Software Algorithm to run on ARM Rx Hardware Algorithm  LTE SIB1 Recovery Using Analog Devices AD9361/AD9364 Hardware Generation Model Copyright 2019 The MathWorks, Inc. To simulate ARM behaviour, downsamplers and repeat blocks are added to run it at 1KHz

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Bit Concat;Bit Slice;BitCounter;BitPacking;BitPacking_32bit;Bus Creator;Bus Selector;CFI;CFIDecoder;CONTROL;CellID;CellRefIP;CellRefIP_out;CellRefP;CellRefP_in;Channel Equalization;Compare To Constant;Compare To Zero;Complex to Real-Imag;Concat and Send to Host;Constant;DCI_Resource_Allocation;Data Type Conversion;DataOut;Delay;Deserializer1D;Detect Fall Nonpositive;Detect Rise Positive;Downlink Sync Demod;Downsample;EdgeDetect;En;Enable;FIFO_comp;FROM_SW_DCIALLOC;From;Front_End_FIR_Decimation;Gain;Goto;HDL Counter;HDL FIFO;HDL LTE SIB;HDL MIB + SIB1 Decoder;Info;LTE_SIB_HDL;Logical Operator;MATLAB Function;MIBDecoder;Multiport Selector;Multiport Switch;NCellID;NCellID_in;NCellIO_out;NDLRB;NDLRB1_out;NDLRB_in;NDLRB_out;NFrame;NFrame1_out;NFrame_in;NFrame_out;NOT;NcellID;Ng;Ng_in;Ng_out;Nsubframe;OFDMdata;PBCH Indexing;PCFICH Indexing;PDCCH Indexing;PDCCHDecodeSearch;PDSCH Indexing;PDSCHDecode;PHICH;PHICH_in;PHICH_out;PrepInputs;PulseResync;RV;Rate Transition;Rate change to 1KHz;Real-Imag to Complex;Reference;Repeat;Resource Grid Memory;Rising Edge Detector;RstFrame;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxDataValid_In;RxDataValid_Out;SIBDetected;SIB_Bit_Packing;STATE;Signal From Workspace ;Signal Specification;StartOut;State Control;Stop ;SubSystem;Subsystem;Switch;TDDMode;TO_SW_DCIALLOC;Tapped Delay;TappedDelayEnabled;Terminator;Trigger;Unpack SIB Bits;Valid;ValidGen;VecCounter;Vector Concatenate;XOR;bitIn;bit_in;calcDone;cellDetected;cellRefP;cellRefP_valid;cellSearchDone;cellSearchFail;cfiOut_in;cfiValid;cfi_out;cfi_valid;clearOutput;dataIn;dataOut;dciBits;dciBits_out;dciDetected;dciDetected_out;dciError;dciFormat;dciFormat_out;dciSize;dciSize_out;decoderState;decoderStateControl;detectEdges;duplexMode;duplexmode_out;enable;enablePBCH;enablePCFICH;enablePDCCH;enablePDSCH;frameCount;gridWrDone;gridWriteDone;hestRdy;hestReady;in;last_Word;mi;mibDetected;mibError;mib_detected;mib_error;nBits;nFrame;nFrameMIB;nFrameOut;nFrame_mib;nSubFrame;nSubframe;nWords;negEdge;numWords;out;pbch_addr;pcfich_addr;pdcch_addr;pdsch_addr;posEdge;prbCalcDone;pulseIn;pulseOut;rbset;rbsize;rd_addr_bus;read_selector;restart;restart controller;restartTimeout;resttartTimeout;sib1Bits;sib1BitsValid;sib1Done;sib1Error;sib1_done;sib1_error;sibBits;sibBitsLen_in;sibBits_out;sibData;sibLen;sibLength;sibLength_out;sibValid;sibValidIn;sibValid_out;sibWordCnt;sibWords;sibWords_out;start;startIn;state;stateViewer;state_in;stopSimulation;trblklen;triggerIn;u;valid;validIn;validOut;vecValidIn;wordOut;word_out;writeSubframe

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Deserializer1D;Detect Fall Nonpositive;Detect Rise Positive;DownSample;EnablePort;FIR Decimation;From;Gain;Goto;HDL Counter;HDL_FIFO;Info;Inport;Logic;ModelReference;MultiPortSwitch;Multiport Selector;Outport;RateTransition;RealImagToComplex;Repeat;S-Function;Signal From Workspace;SignalSpecification;StateControl;Stop;Switch;Tapped Delay Line;Terminator;TriggerPort

PRODUCT:
DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices;Wireless HDL Toolbox

EXTERNALFILE_REFERENCE:
ltehdlChannelEqualizer___Model_Block___ltehdlDCIResourceAllocation___Model_Block___ltehdlDownlinkSyncDemod___Model_Block___ltehdlPBCHDecoder___Model_Block___ltehdlPBCHIndexing___Model_Block___ltehdlPCFICHDecoder___Model_Block___ltehdlPCFICHIndexing___Model_Block___ltehdlPDCCHDecoder___Model_Block___ltehdlPDCCHIndexing___Model_Block___ltehdlPDSCHDecoder___Model_Block___ltehdlPDSCHIndexing___Model_Block___ltehdlResourceGrid___Model_Block___


MODELNAME: zynqRadioHWSWLTESIB1DetectorAD9361AD9364SL_UDP_Receive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTESIB1DetectorAD9361AD9364SL_UDP_Receive.slx
BLOCKTYPE: Demux;EnablePort;Info;Inport;S-Function;Terminator;UDP Receive
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;1;1
CHECKSUM: 2273FCC6C36FD3D7BFB981B7E4B70116
PRODUCT: MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Demux ; SFunction ; Terminator ;Display Cell Information;Enable;Info;MATLAB Function;Reference;SubSystem;UDP Receive;cellVector;u


MODELNAME: zynqRadioHWSWLTESIB1DetectorAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWLTESIB1DetectorAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 19;7;1;1;1;2;35;7;4;2;1;52;1;1;61;4;2;1;13;1;1;1
CHECKSUM: 291D4C0C1DC4FA2D65F5E1D3022594B3
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Generated by HDL Workflow Advisor on 23-Jun-2020 12:20:14 This example doesnt use AXI-Stream output. Set all to outputs to zero. SDR Receiver to ARM Algorithm LTE SIB1 Recovery Using Analog Devices AD9361/AD9364 Software Interface Model Copyright 2019-2020 The MathWorks, Inc. Open host model  Double click the block to open the host model and display detected SIB1 information  SIB1 Bits available here  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required Select Hardware Board Target Alternative Receiver block - Select the correct block for your hardware

BLOCK:
 Demux ; SFunction ; Terminator ;AD936x Receiver;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_CFI;AXI4SlaveRead_CellRefIP;AXI4SlaveRead_NCellID;AXI4SlaveRead_NDLRB;AXI4SlaveRead_NFrame;AXI4SlaveRead_Ng;AXI4SlaveRead_PHICH;AXI4SlaveRead_STATE;AXI4SlaveRead_dciBits;AXI4SlaveRead_dciDetected;AXI4SlaveRead_dciFormat;AXI4SlaveRead_dciSize;AXI4SlaveRead_duplexMode;AXI4SlaveRead_sib1Bits;AXI4SlaveRead_sibLength;AXI4SlaveRead_sibValid;AXI4SlaveRead_sibWords;AXI4SlaveWrite;AXI4SlaveWrite_RV;AXI4SlaveWrite_calcDone;AXI4SlaveWrite_rbset;AXI4SlaveWrite_rbsize;AXI4SlaveWrite_start;AXI4SlaveWrite_trblklen;AllocationType;CFI;CellRefIP;CellRefP_in;Center Frequency;Compare To Constant;Concat and Send to Host;Constant;DCI Format;DCIBits;DCIFormat;DCILen;DCIResourceAllocation;DCIbits;Data Type Conversion;DataTypeConversion;Delay;Detect Rise Positive;FMCOMMS5 Receiver;Gap_out;Info;LTE_SIB_HDL;MATLAB Function;NCellID;NCellID_in;NDLRB;NDLRB_in;NFrame;NFrame_in;Ng;Ng_in;PHICH;PHICH_in;RIV;RIV_out;RV;RV_out;Reference;SIBDetected;STATE;Selected Hardware Board Target;Signal Specification;Start;SubSystem;Subsystem;Terminator;Trigger;UDP Send;Unpack SIB Bits;Vector Concatenate;aType_out;calcDone;cfiOut_in;clear;dciBits;dciDetected;dciFormat;dciResourceAlloc;dciSize;done;duplexMode;enable;formatType;gapBool;hdllteDCI;nBits;numWords;rbSet;rb_cols;rb_rows;rbset;rbsize;reset;restartController;restartTimeout;sib1Bits;sibBits;sibBitsLen_in;sibLength;sibValid;sibWords;start;state_wire;trblkLen;trblklen;trblklen_out;validIn;validOut;validOut_out

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Compare To Constant;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Rise Positive;Info;Inport;MATLABSystem;Model Source;Outport;S-Function;SignalSpecification;System Start;Terminator;TriggerPort;UDP Send;comm.SDRRxFMCOMMS5

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWOFDMAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWOFDMAD9361AD9364SL.slx
BLOCKTYPE_FREQUENCY: 14;1;20;21;1;4;1;3;29;2;29;171;2;12;4;2;6;6;6;9;1;100;10;11;7;2;1;93;9;3;1;2;1;2;1;14;11;8;1;2;1
CHECKSUM: 6326BF0E85EE7B0FFBDD64E46B03790C
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: whdlOFDMRx___Model_Block___whdlOFDMTx.slx___Model_Block___
ANNOTATION:
NO HDL Block NO HDL Block Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2)  Add Block is used to obtain integer index to Lookup Table If packetValid is true, OFDM Tx accepts input payload data and outputs proper waveform. If packetValid is false, OFDM Tx doesnt accept input data and outputs random signal. NO HDL Block  Generate Status Signals to monitor Outside FPGA OFDM Transmit and Receive Status Signal Generator Constellation View for SW interface model  channel will be applied only if enableInternalLoopback is true Status Signals to monitor outside FPGA Display Control Rx Control Channel Control Tx Control Zynq Radio OFDM Hardware Model Copyright 2020 The MathWorks, Inc.  CFO Range -7400 to 7400 Hz   snr Range 0 to 63 dB  Enable/disable Channel Equalization and CPE Correction  Reset the Display Blocks and switch between header and data constellation  code rate: 0 =&gt; 1/2 1 =&gt; 2/3 2 =&gt; 3/4 3 =&gt; 5/6  packetValid Enable/disable valid data transmission  This outport is connected to scope in SW model to view constellation based on headerView inport  Display blocks will reset when displayReset inport is true  Both constellations can be seen in simulation connected inside the model Received Signal from RF Front End or internal Tx-Rx loopback based on enableInternalLoopback signal Unused ports  Nonfunctional ports. They are terminated inside the subsystem.  Reset the Receiver

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AWGN Generator;Add;Apply CFO;BER;Bit Concat;Bit Shift;Bitwise Operator;Bus Creator;Bus Selector;CFO;CPECtrl;Capture Data Bits;Channel Control;Compare To Constant;Complex to Real-Imag;ConcatandExtract;Constant;Constellation Formation;Control Scope;DAC Output;Data Constellation Diagram;Data Type Conversion;Delay;Denormalized by subCarrierSpacing;Diagnostic Decoder;Display;Enable;EstimatedCFO;Extract Bits;Falling Edge Detector;From;FunctionEvaluation;Gain;Gaussian Noise With Given Variance;Goto;HDL Counter;Header Constellation Diagram;In;Info;Logical Operator;MT;Manual Switch;NCO HDL Optimized;Normalized by fs;OFDM HDL;OFDM Rx;OFDM Tx;OFDMTx;OFDMTx Channel OFDMRx;Out;Prepare Inputs;Prepare Outputs;Product;RangeReconstruction;RangeReduction;Real-Imag to Complex;Reference;Relational Operator;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_In;RxValid_Out;Select Payload Data;Send Payload Data;Shift Arithmetic;Signal Specification;SinCos;Sine HDL Optimized;SqrtEval;SqrtImplementation;SubSystem;Subsystem;Subtract;Switch;TausURNG;TausUniformRandGen;Terminator;To Spectrum Analyzer;To Workspace;Tx Filtered Spectrum Analyzer;Tx Filtered Spectrum Analyzer_CCDF;Tx Filtered Spectrum Analyzer_Convert;Tx Filtered Spectrum Analyzer_PAPR;Tx Filtered Spectrum Analyzer_RelPwr;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxValid_In;TxValid_Out;Unit Delay Enabled Synchronous;Unit Variance Gaussian Noise;Visualize Data Constellation;Visualize Header Constellation;White Gaussian Noise Generator;a;awgn;b;bitCount;bitErrors;chEqCtrl;codeRate;codeRateIndex;dB to Linear Scale Converter;dPoints;dValid;data constellation points;dataIIn;dataIn;dataIout;dataOut;dataPoints;dataQIn;dataValid;decodedCodeRate;decodedModType;decodedRate;diagBus;displayReset;e;enableCPECorrec;enableChanEqui;enableInternalLoopback;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;freq;freqOffsetEstimate;g;g1(16,15);hPoints;hValid;hView;header constellation points;headerCaptred;headerPoints;headerValid;headerView;impairmentControl;in;initial reset;insertCFO;internalFeedback;leadingZeroDetector;log;logImplementation;modType;modTypeIndex;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived;nfreq;noise;noiseVar;nxtBit;out;packetValid;pass;passIn;passOut;ready;reset;resetRx;resetcounter;rst;rxData;rxDataOut;rxValid;rxValidOut;snrdB;sqrt(noisePow/2);txData;txDataOut;txValid;txValidOut;txvalid;u;u0(16,16);u0(48,48);u1(16,16);userBits;userBitsValid;validIn;validOut;whdlOFDMRx Model;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bitwise Operator;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Display;EnablePort;Extract Bits;From;Gain;Goto;HDL Counter;Info;Inport;Logic;Lookup_n-D;ManualSwitch;ModelReference;NCO;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;SignalSpecification;Sine and Cosine HDL optimized block;SpectrumAnalyzer;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Synchronous;dsp.simulink.PowerMeter

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWOFDMAD9361AD9364SL_hostUDPReceive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWOFDMAD9361AD9364SL_hostUDPReceive.slx
ANNOTATION: Zynq Radio Host UDP Receive Model Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;7;10;2;1;3;20;10;10;2
CHECKSUM: EDA07EE585235B55E96665B27D393CC9
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Denormalization ;Constellation Diagram;Control Scope;Data Type Conversion;Display;Enable;EstimatedCFO;In;Reference;Selector;Status Signals;StatusSignals;SubSystem;To Workspace;UDP Receive Constellation;UDP Receive Status;Visualize Constellation;decodedCodeRate;decodedModType;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived

BLOCKTYPE:
ConstellationDiagram;DataTypeConversion;Display;EnablePort;Gain;Inport;Outport;Selector;ToWorkspace;UDP Receive


MODELNAME: zynqRadioHWSWOFDMAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWOFDMAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 10;11;1;15;26;3;1;1;1;1;36;4;2;7;1;22;1;2;1;1
CHECKSUM: 33B413775FC7C02C38BC47F7430C5962
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Status Signal Generator  Generate Status Signals to monitor Outside FPGA Generated by HDL Workflow Advisor on 19-Jan-2023 16:57:40 OFDM Transmit and Receive Zynq Radio OFDM Software Interface Model ARM Interface to HW User Logic ARM Algorithm to SDR Transmitter SDR Receiver to ARM Algorithm Rx Control Display Control  CFO Range -subcarrierSpacing/2 to subcarrierSpacing/2 Hz   snr Range 0 to 63 dB  Enable/disable Channel Equalization and CPE Correction Channel Control  code rate: 0 =&gt; 1/2 1 =&gt; 2/3 2 =&gt; 3/4 3 =&gt; 5/6  Reset Display Blocks and switch between header and data constellation Tx Control  Enable/disable valid frame transmission Copyright 2020 The MathWorks, Inc. Receive Signal from RF Front End or internal Tx-Rx loopback based on enableInternalLoopback is true. channel will be applied only if enableInternalLoopback is true. Unused ports  Nonfunctional ports. They are terminated inside the subsystem. Alternate transmitter and Receiver blocks- select the correct block for your hardware  Double click the block to switch between the Xilinx Zynq-7000 and Xilinx Zynq UltraScale+ MPSoC hardware board targets as required Select Hardware Board Target Open host model  Double click the block to open the host model.

BLOCK:
AD936x Receiver;AD936x Transmitter;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_EstimatedCFO;AXI4SlaveRead_decodedCodeRate;AXI4SlaveRead_decodedModType;AXI4SlaveRead_nDataCRCFail;AXI4SlaveRead_nDataCRCPass;AXI4SlaveRead_nFramesSynced;AXI4SlaveRead_nHeaderCRCFail;AXI4SlaveRead_nHeaderCRCPass;AXI4SlaveRead_nbitErrors;AXI4SlaveRead_nbitReceived;AXI4SlaveWrite;AXI4SlaveWrite_codeRate;AXI4SlaveWrite_displayReset;AXI4SlaveWrite_enableCPECorrec;AXI4SlaveWrite_enableChanEqui;AXI4SlaveWrite_enableInternalLoopback;AXI4SlaveWrite_headerView;AXI4SlaveWrite_insertCFO;AXI4SlaveWrite_modType;AXI4SlaveWrite_packetValid;AXI4SlaveWrite_resetRx;AXI4SlaveWrite_snrdB;CFO;Constant;Data Type Conversion;DataTypeConversion;Decode Status Signals;Delay;Display;Enable;EstimatedCFO;FMCOMMS5 Receiver;FMCOMMS5 Transmitter;In;Info;Logical Operator;Manual Switch;Normalization;OFDM HDL;Out;Reference;Selected Hardware Board Target;SubSystem;UDP Receive Model;UDP Send;UDP Visualize Constellation;Vector Concatenate;codeRate;decodedCodeRate;decodedModType;displayReset;enableCPECorrec;enableChanEqui;enableInternalLoopback;headerView;initial reset;insertCFO;modType;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived;packetValid;resetRx;snrdB

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;Concatenate;Constant;DataTypeConversion;Delay;Display;EnablePort;Gain;Info;Inport;Logic;MATLABSystem;ManualSwitch;Model Source;Outport;System Start;UDP Send;comm.SDRRxAD936x;comm.SDRTxAD936x


MODELNAME: zynqRadioHWSWQPSKAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWQPSKAD9361AD9364SL.slx
CHECKSUM: 72FC23326A7659A6392677C51583A462
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 The burst data sent from the processing system will be stored in the RAM in the memory channel of SDR IIO radio. The data stored will be poped out as a stream data.   This subsystem does an equivalent operation to simulate the input and output behaviour of the memory channel of the SDR IIO radio.  Fixed point precision loss warnings are supressed in Mask Init Callback fixed point precision loss warning supressed for this subsystem store the value in the Reg before reset  Let Z be the complex Phase Ambiguity estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z))  Set this value to zero to disable phase ambiguity correction peak picker This subsystem generates variables required for QPSKRxVerification for validation Proportional-Plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence  HDL Data Scrambler Polynomial: x^7+x^4+1 Initial state: [1 0 1 1 1 0 1]  The Preamble is padded with zeros in the LUT such that the length is the 2^nextpow2(length(Preamble)) for efficient resource mapping to RAM  HDL Data Scrambler Polynomial: x^7+x^4+1 Initial state: [1 0 1 1 1 0 1] 2^32-1 will be treated as NaN in double when converted to double  Set rstCS port to true to reset the carrier synchronizer (CS) in the QPSK receiver Copyright 2016-2023 The MathWorks, Inc.  HW/SW Co-design QPSK Transmitter and Receiver Using Analog Devices AD9361/ AD9364 Hardware Generation Model 

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AXI4S_Data_Out;AXI4S_Tready_In;AXI4S_Valid_Out;Add;Assertion;Automatic Gain Control;Average Estimates;BER;BIT_XOR;Bit Packetizer;Bit Shift;Bits to Char;Burst to Stream Conversion Equivalent;Bus Creator;Bus Selector;CFO;CFO step change detector;CPO;Capture Data Bits;Carrier Synchronizer;Coarse Frequency Compensator;Coarse Frequency Estimator;Compare To Constant;Complex to Magnitude-Angle;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Conj;Constant;Constellation Diagram;Correlation Time Scope;Correlator;DAC equivalent;Data Bits FIFO;Data Type Conversion;Data Type Duplicate;Delay;Delta;Demux;Direct Digital Synthesis;Direct Lookup Table (n-D);Discrete FIR Filter;Display;Divide by ;E;Enable;End Generator;Error Detector;External Message;Extract Bits;Extract Frequency;FIFO;Frame Counter;Frequency and Time Synchronizer;From;Function Impl;GTED;Gain;Gardner TED;Goto;H;HDL Counter;HDL Data Descrambler;HDL Data Scrambler;HDL_QPSK;In;Info;InputGen;Integ Reg;IntegOut;IntegValid;Integer Delay;Integrator;Interpolation Control;Interpolation Filter;K;L;LUT;LUTAddr;Logical Operator;Loop Filter;MATLAB Function;Magnitude Squared;Magnitude Squared and Moving Sum;Manual Switch;Math Function;Multiport Switch;Mux;NCO;NCO HDL Optimized;No HDL;Null;Out;Packet Controller;Peak Search;Phase Ambiguity Corrector;Phase Ambiguity Estimation and Correction;Phase Ambiguity Estimator;Phase Error Detector;PhaseError;Pop Counter;Preamble;Preamble Bits Generator;Preamble Bits Store;Preamble Detector;Prepare Inputs;Prepare Outputs;Product;Push Counter;QPSK Demodulator;QPSK Demodulator Baseband;QPSK Modulator;QPSK Modulator Baseband;QPSK Receiver Constellation ;QPSK Receiver Constellations ;QPSK Receiver Eye Diagram;QPSK Rx;QPSK Tx;QPSK Tx Channel QPSK Rx;RAM Frame Status Indicator;RRC Filter;RRC Receive Filter;RRC Transmit Filter;Raise Power to ;Rate Handle;Real-Imag to Complex;Reciprocal;Ref;Reference;Relational Operator;Reset Generator;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxIIn;RxQIn;RxVIn;RxValid_In;RxValid_Out;Send Payload Data;Serializer;Serializer1D;Signal Specification;Simple Dual Port RAM;State Register;Store Reg;SubSystem;Subsystem;Sum;Switch;Symbol Counter;Symbol Synchronizer;SyncPulse;Terminator;ThresholdLimiter;Timing Adjust;To Workspace;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxValid_In;TxValid_Out;Underflow;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Validate Input Push Pop;activeFrame;actualPreamble;avgEst;bitCount;bitErrors;bitReceived;bits;bitsCtrl;bitsOut;bitsValid;burstDataIn;captureASCII;channel;char;charOut;charValid;coarseFreq;corr;count;ctrlOut;data;dataEnd;dataIIn;dataIOut;dataIn;dataOut;dataQIn;dataQOut;dataReady;dataStart;datain;dir;displayReset;divide by ;done;e;empty;enb;enbExt;endIn;endOut;err;estOut;estimate;estimatedCoarseCFO;estin;expOut;extMsgActive;externalDataActive;externalMsg;externalMsgValid;externalRst;frameNumber;full;fullRAM;functionValues;gain;in;initial reset;insertCFO;insertCPO;internalRst;interpolant;manualRst;mu;nSynced;ncount;normCoarseFreqEst;normFreqEst;normFreqOut;normalisedFreq;normalisedPhase;normalizedFreqEst;numEntries;numOfFramesSynced;nxtBit;out;overAir;overAirDataIn;overAirValidIn;packetBits;phaseInc;pop;popEmpty;popEmptyDiag;popEmptyFIFO;preamble;preambleBits;printData;push;pushFull;pushFullDiag;pushFullFIFO;rd;reset;resetcounter;rst;rstCS;rxBus;rxCtrlOut;rxDataOut;rxDiagBus;sample discard controller;sampleCount;sampleCountValid;scaled;start;startIn;startOut;streamDataIOut;streamDataQOut;strobe;success;switch;syncPulse;syncPulseIn;syncPulseOut;threshold;thresholdExceeded;timing Reference;timing Reference Long;timingOffset;timingOffsetValid;txDataOut;txDiagBus;txValidOut;u;userBits;userBitsValid;v;valid;valid pop;valid push;validIn;validOut;validPop;wr;x;y

BLOCKTYPE:
ArithShift;Assertion;Bit Shift;BusCreator;BusSelector;Compare To Constant;Complex to Magnitude-Angle;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;EnablePort;Extract Bits;EyeDiagramBlock;From;Gain;Goto;HDL Counter;Info;Inport;Logic;LookupNDDirect;Lookup_n-D;ManualSwitch;Math;MultiPortSwitch;Mux;NCO;Outport;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;RealImagToComplex;RelationalOperator;S-Function;Scope;Serializer1D;SignalSpecification;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous

BLOCKTYPE_FREQUENCY:
1;2;1;3;2;31;2;8;26;3;47;2;354;11;3;5;8;12;1;3;11;3;27;1;221;53;4;2;4;8;4;1;3;171;19;1;1;3;4;10;1;2;1;2;25;13;20;7;25;18

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWQPSKAD9361AD9364SL_hostUDPReceive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWQPSKAD9361AD9364SL_hostUDPReceive.slx
BLOCKTYPE_FREQUENCY: 4;1;1;6;2;4;3;1;1;4;4;1;1;1;1;1;3
CHECKSUM: 38D342C62E98FE4238CFEB75019AAC39
PRODUCT: Communications Toolbox;Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 HW/SW Co-design QPSK Transmitter and Receiver Using Analog Devices AD9361/ AD9364 Host UDP Receive Model  Copyright 2016-2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Bit Errors;Bits Received;Compare To Constant;Constant;Constellation Diagram;Data Type Conversion;Demux;Enable;Estimated Coarse CFO;Gain;In;Info;MATLAB Function;Number of Frames Synchronized;Reference;Serializer1D;SubSystem;Subsystem;Switch;UDP Receive;bitErrors;bitsReceived;captureASCII;estCoarseFreq;nSynced;packetBits;printData;u

BLOCKTYPE:
Compare To Constant;Constant;ConstellationDiagram;DataTypeConversion;Demux;Display;EnablePort;Gain;Info;Inport;Outport;S-Function;Serializer1D;Switch;Terminator;ToWorkspace;UDP Receive


MODELNAME: zynqRadioHWSWQPSKAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWQPSKAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 4;6;1;7;14;1;3;2;1;20;2;2;4;9;1;3;1;1;1
CHECKSUM: 576759678F1C20EB15D5CC9838DCD5DE
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
2^32-1 will be treated as NaN in double in UDP Receive Model ARM Interface to HW User Logic SDR Receiver to ARM Algorithm ARM Algorithm to SDR Transmitter  HW/SW Co-design QPSK Transmitter and Receiver Using Analog Devices AD9361/ AD9364 Software Interface Model  Copyright 2016-2022 The MathWorks, Inc. Alternate transmitter and Receiver blocks- select the correct block for your hardware  Double-click the block to switch between the Xilinx Zynq-7000 Based IIO Radio and Xilinx Zynq UltraScale+ MPSoC ZCU102 IIO Radio hardware board targets as required Select Hardware Board Target  Double-click the block to open the host model. Open host model

BLOCK:
AD936x Receiver;AD936x Transmitter;AXI4-Stream IIO Read;AXI4SlaveRead;AXI4SlaveRead_bitErrors;AXI4SlaveRead_bitReceived;AXI4SlaveRead_estimatedCoarseCFO;AXI4SlaveRead_numOfFramesSynced;AXI4SlaveWrite;AXI4SlaveWrite_displayReset;AXI4SlaveWrite_externalDataActive;AXI4SlaveWrite_insertCFO;AXI4SlaveWrite_insertCPO;AXI4SlaveWrite_overAir;AXI4SlaveWrite_rstCS;CFO;CPO;Constant;Data Type Conversion;DataTypeConversion;Delay;Display;Enable;External Message;FMCOMMS5 Receiver;FMCOMMS5 Transmitter;HDL_QPSK;In;Info;Logical Operator;Manual Switch;Reference;Selected Hardware Board Target;SubSystem;Switch;UDP Receive Model;UDP Send;UDP Send ;Vector Concatenate;bitErrors;bitReceived;displayReset;enbExt;estimatedCoarseCFO;externalDataActive;initial reset;insertCFO;insertCPO;numFramesSynced;numOfFramesSynced;overAir;packetBits;rstCS

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;Concatenate;Constant;DataTypeConversion;Delay;Display;EnablePort;Info;Inport;Logic;MATLABSystem;ManualSwitch;Outport;Switch;UDP Send;comm.SDRRxAD936x;comm.SDRTxAD936x;matlabshared.libiio.axistream.read

PRODUCT:
Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: zynqRadioHWSWWLANAD9361AD9364SL
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWWLANAD9361AD9364SL.slx
CHECKSUM: ED1345578F313C9A84CC803767F57394
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
NO HDL Block NO HDL Block 1/(numSCs*modOrder*codeRate) numSCs*modOrder*codeRate numSCs*modOrder Calculating PSDU len for VHT frame using initial 25bits of VHT SigB Dectecting CRC on first 19 bits Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Accumulated delay for reset to match both Deinterleaver outputs choose output based on block size Deinterleaver for Non-HT frame with block size 48  Deinterleaver for HT/VHT frame with block size 52  poly: 1 0 0 1 0 0 0 Selecting BPSK and 1/2 rate coding for VHT Signal B field  decoderInpLen = ceil((psduLen+22)/(numSCs*modOrder*codeRate))*(numSCs*modOrder) codeRate modSel numSCs*modOrder 1/(numSCs*modOrder*codeRate) Delay data constellation and valid to match latency of symbol demodulator, deinterleaver and decoder  Sample MCS, Frame format, PSDU length with respect to Descrambler Start Out for display  Output the data symbols corresponding to the decoded PSDU length value  Appriopriate delays to match detected frame format arrival Choose L-Data from symbol 6  Choose bits from 25 to end for VHT Sig parameters Choose bits from 25 to 65 for CRC detection Threshold chose as half of used subcarriers in signal fields Delays to match arrival of MCS Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW  Choose L-SIG, HT-SIG and VHT-SIG based on format detected Choose BPSK   choose L Sig For QBPSK Choose QBPSK  Storing OFDM symbol 6 and 7 until frame format detection is completed  Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) reference pilots are stored in LUT for 4 symbols pilots for 4 symbols are stored to avoid modulo operation  Counter for pilot Subcarriers for 4 Symbols  delay the adder output till the end of Symbol delay value = Maximum Used subcarrier- Last pilot Subcarrier position  add the pilots; reset the pilots for every Symbol Multiply the Equalizer Output with reference pilots  Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output  Choose polarity 1 for VHT Sig B Choose ZStart based on Format detected selecting Data field for equalization Delay by 1 OFDM Symbol time Selecting 9th symbol i.e., HT/VHT LTF after OFDM demod  Sending chan est as 1 when valid is low to channel equalizer Select VHTSigB symbol for frame format 2 Selecting only VHT data for frame format 2 Delay by 1.4 times OFDM symbol length to match frame format detected  Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) reference pilots are stored in LUT for 4 symbols pilots for 4 symbols are stored to avoid modulo operation  Counter for pilot Subcarriers for 4 Symbols  delay the adder output till the end of Symbol delay value = Maximum Used subcarrier- Last pilot Subcarrier position  add the pilots; reset the pilots for every Symbol Multiply the Equalizer Output with reference pilots  Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers (65 for 20Mhz)   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output   Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output  Choose polarity 1 for L-SIG selecting from L-SIG field to L-Data for equalization Delay by 1 OFDM Symbol time Sending chan est as 1 when valid is low to channel equalizer Selecting LLTF 1 and 2 for channel estimation  NonHTScSelector Non-HT scaling factor Select Non-HT frame format used subcarriers HT/VHT scaling factor Searching peak in LSTF region Upsample by 8 is used for Resource Sharing in the Discrete FIR filter  delayLen=filterUpsampleFactor-1  Latency = (coeffLen/filterUpsampleFactor)+filterUpsampleFactor+9 1/(numSCs*modOrder*codeRate) numSCs*modOrder*codeRate numSCs*modOrder Calculating PSDU len for VHT frame using initial 25bits of VHT SigB Dectecting CRC on first 19 bits Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW Accumulated delay for reset to match both Deinterleaver outputs choose output based on block size Deinterleaver for Non-HT frame with block size 48  Deinterleaver for HT/VHT frame with block size 52  poly: 1 0 0 1 0 0 0 Selecting BPSK and 1/2 rate coding for VHT Signal B field  decoderInpLen = ceil((psduLen+22)/(numSCs*modOrder*codeRate))*(numSCs*modOrder) codeRate modSel numSCs*modOrder 1/(numSCs*modOrder*codeRate) Appriopriate delays to match detected frame format arrival Choose L-Data from symbol 6  Calculate the Rx time from L-sig bits for VHT frame format Compute the number of OFDM data symbols for VHT frame format Choose bits from 25 to end for VHT Sig parameters Choose bits from 25 to 65 for CRC detection Threshold chose as half of used subcarriers in signal fields Delays to match arrival of MCS Compute read address Compute read address  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Give null output if valid is LOW  Choose L-SIG, HT-SIG and VHT-SIG based on format detected Choose BPSK   choose L Sig For QBPSK Choose QBPSK  Storing OFDM symbol 6 and 7 until frame format detection is completed  Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) reference pilots are stored in LUT for 4 symbols pilots for 4 symbols are stored to avoid modulo operation  Counter for pilot Subcarriers for 4 Symbols  delay the adder output till the end of Symbol delay value = Maximum Used subcarrier- Last pilot Subcarrier position  add the pilots; reset the pilots for every Symbol Multiply the Equalizer Output with reference pilots  Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output  Choose polarity 1 for VHT Sig B Choose ZStart based on Format detected selecting Data field for equalization Delay by 1 OFDM Symbol time Selecting 9th symbol i.e., HT/VHT LTF after OFDM demod  Sending chan est as 1 when valid is low to channel equalizer Select VHTSigB symbol for frame format 2 Selecting only VHT data for frame format 2 Delay by 1.4 times OFDM symbol length to match frame format detected HT/VHT scaling factor  Let Z be the complex CPE estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) reference pilots are stored in LUT for 4 symbols pilots for 4 symbols are stored to avoid modulo operation  Counter for pilot Subcarriers for 4 Symbols  delay the adder output till the end of Symbol delay value = Maximum Used subcarrier- Last pilot Subcarrier position  add the pilots; reset the pilots for every Symbol Multiply the Equalizer Output with reference pilots  Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers (65 for 20Mhz)   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output   Pilot Subcarriers are stored in LUT. Note that subcarriers positions other than pilots subcarriers positions are stored with Max Value outside the range of Subcarriers   Count Used Subcarriers and generate pulse at the end of the Symbol  Pilot Subcarriers are selected by comparing with counter value and LUT output  Choose polarity 1 for L-SIG selecting from L-SIG field to L-Data for equalization Delay by 1 OFDM Symbol time Sending chan est as 1 when valid is low to channel equalizer Selecting LLTF 1 and 2 for channel estimation  Non-HT scaling factor Select Non-HT frame format used subcarriers Searching peak in LSTF region Upsample by 8 for 20MHz and 4 for 40MHz is used for Resource Sharing in the Discrete FIR filter  delayLen=filterUpsampleFactor-1  Latency = (coeffLen/filterUpsampleFactor)+filterUpsampleFactor+9  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Inputs are sampled only when counter reach zero  LUT Index is selected based on Frame Format and MCS  Inputs are sampled only when counter reach zero  LUT Index is selected based on Frame Format and MCS   1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  Generate Status Signals to monitor Outside FPGA WLAN Transmit and Receive Status Signal Generator Constellation View for SW Interface Model Status Signals to Monitor Outside FPGA Tx Control Zynq Radio WLAN Hardware Model Copyright 2023 The MathWorks, Inc.  The output ports RxDataI_Out, RxDataQ_Out, and RxValid_Out are connected to scope in the software model to view constellation based on the headerView inport.  In simulation, both the header and data constellations can be seen through the scopes connected inside the model. Received Signal from RF Front End Unused Ports Display Control  Double-click the Switch block to toggle between header and data constellations.  MCS: {0,1,2,3} =&gt; Non-HT {0,1,2} =&gt; HT-MF {0,1,2} =&gt; VHT  For out-of-range MCS values, 3 is applied for Non-HT, 2 is applied for HT-MF and VHT.  The input ports TxDataI_In, TxDataQ_In, and TxValid_In are non-functional and are terminated inside the subsystem.  If Higher MCS Support if enabled MCS: {0,1,2,3,5,6,7} =&gt; Non-HT {0,1,2,3,5,6,7} =&gt; HT-MF {0,1,2,3,5,6,7} =&gt; VHT

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;2-D Lookup Table;<valid>;AND;Abs;Add;Add Constant;Bit Clear;Bit Set;Bit Shift;Bus Creator;Bus Selector;C;CPECorrector;CPEEstimator;CRCCheck;CRCCheckAndBitInterpretation;ChannelEqualizator;ChannelEqualizer;ChannelEstimator;Coarse CFO Correction;Coarse CFO Estimation;Coarse CFO Estimation and Correction;Coarse Time Sync;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Conjugate;Constant;Constellation Formation;Control Scope;DAC Output;DTConverter;DTadjust;Data Constellation Diagram;Data Symbols;Data Type Conversion;DataRecovery;DataSubCarrierSelector;DataTypeSameAsInput;DataValid;DeInterleaver_HT;DeInterleaver_NonHT;Decoder;Deinterleaver;Deinterleaver Block;Delay;Depuncturer;DepuncturerCtrlGen;Descrambler;Diagnostic Decoder;Direct Lookup Table (n-D);Discrete FIR Filter;Discrete FIR Filter HDL Optimized;Display;Downsample;Enable;Enabled Delay;EqValidIn;Extract Bits;Fine CFO Correction;Fine CFO Estimation;Fine CFO Estimation and Correction;Fine Time Sync;FormatIdentification;Frame Format ;FrameFormatController;FrameFormatDetectionAndSignalRecovery;Freq;From;Function Impl;Gain;General CRC Generator HDL Optimized;General CRC Syndrome Detector HDL Optimized;Generate Base Read Address;Generate Current Frame Status;Generate Forced End;Generate Output Control Signals;Generate Read Address;Generate Ready;Generate Write Address;Goto;HDL Counter;HTCRCStatus;HTDataIn;HTRst;HTScSelector;HTSigBitRecover;HTSigCRCCheck;HTValid;HT_VHTCPEEstAndCorrection;HT_VHTChannelEstAndEqualize;HT_VHTchanEst;HT_VHTchanEstValid;Handle Input Control Signals;Header Constellation Diagram;Higher MCS Support;In;Info;Initial Seed;Inport;LSTF_start;LSigBitRecover;LUT;LUTAddr;LUTSelect;Logical Operator;MATLAB Function;MCS;MagnitudeSquared;Manual Switch;Math Function;MovingSum;Multiport Switch;NCO;NCO HDL Optimized;NOT;NonHTCPEEstAndCorrection;NonHTChannelEstAndEqualize;NonHTDataIn;NonHTDataSelector;NonHTRst;NonHTScSelector;NonHTValid;OFDM Channel Estimator;OFDM Demodulator;OFDM Equalizer;OFDMDemodParamsCalculator;OFDMDemodulation;OR;Out;Outport;PSDULen;PSDULenNonHT;PSDULength;PilotSubCarrierSelector;PolarityGenerator;Prepare Inputs;Prepare Outputs;Product;RAM;Read Address of Deinterleaver;Read Address of Interleaver;Read Logic;Real-Imag to Complex;Reciprocal;RefPilotsOut;Reference;RefrenceSignalGen;Relational Operator;Repeat;Rx Filter;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_In;RxValid_Out;Sample Control Bus Creator;Sample Control Bus Selector;Shift Arithmetic;SignalBitRecovery;SignalFieldController;Simple Dual Port RAM;Stage;Stage 2 16QAM ;Stage 2 64QAM;Stage 2 BPSK;Stage 2 QPSK;State Control;Store Block Lengths;SubSystem;Subtract;Sum;Switch;SymbEndInd;SymbStart;Symbol Counter;Symbol Demodulator;SymbolDemodulator;SymbolEndInd;Synchronous Enabled 16 Sample Delay ;Synchronous Enabled Unit Delay;Terminator;To Workspace;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxValid_In;TxValid_Out;Tx_LUT_Selection;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;VHT SignalB CRC Check;VHTSigB;VHTSigBCRCStatus;VHTSigBMCS;VHTSigBitRecover;VHTSigCRCCheck ;VHTSigCRCStatus;ValidController;Visualize Data Constellation;Visualize Header Constellation;Viterbi Decoder;ViterbiDecoder;WLAN HDL;WLANHDLReceiver;WLANTimeAndFrequencySynchronization;WLAN_Rx;WLAN_Rx_HighMCS;WLAN_Tx;WLAN_Tx_HighMCS;WLAN_Tx_Rx;Write Logic;advPop;averageSigFieldsFor40MHz;averageVhtSigBbits;averager;averaging unit;avgCorr;baseAddr;bit;blockCount;blockDataCount;blockLen;blockValid;bps;chanEst;chanEstLen;chanEstVal;chanEstValid;codeRate;codeRateIn;codeRateOut;colCounter;complexConj;complexConjugate;considerFirstPeak;corrFilter;corrIn;corrOut;corrValid;corrValidIn;correlator;count;countEnb;countRst;countVal;countValue;counterRst;cpLen;ctrl;ctrlGen;ctrlIn;ctrlOut;currentAddr;dPoints;dValid;data constellation points;dataBits;dataConst;dataConstValid;dataConstellation;dataConstellationPoints;dataConstellationValid;dataIIn;dataIn;dataOut;dataQIn;dataSCValid;dataScValidOut;dataSelector ;dataValid;decodedMCS;decoderInpLen;delayedCorrelation;descramblerStart;diagBus;diagBusControl;displaySampCount;en;enable;enb;end;endIn;endOut;endReady;energy;energyCalculator;energyIn;energyOut;estimate;extractLTFs;failCheck;fftLen;fifoCount;fifoData;forcedEnd;format;formatDetected;formatIn;formatOut;frameFormat;frameFormatIn;frameFormatMapping;frameFormatOut;frameOn;freq;freqIn;freqOff;freqOffset;freqOut;freqValidIn;freqValidOut;frequencyOffset;functionValues;hPoints;hValid;hView;header constellation points;headerConst;headerConstellation;headerConstellationValid;headerView;in;interpretVHTSigB;isQBPSK;lgSc;llr;load;loadH;loadIn;lstfStart;lstfStartIn;lstfStartOut;lstf_start;magnitudeSquared;mapmodSelTobps;maxPeak;maxPeakSearcher;maxPeakVal;maxPeakValue;modSel;modSelIn;modSelOut;numOFDMSymbVHT;numOFDMSymbolCalVHT;numSCS;numSCSFlag;numSCSOut;numSCs;numSCsConverter;numSCsIn;numSCsOut;numSTS;numSymb;numValidSampForDisplay;out;packetDetected;packetOut;peakDetection;peakDetector;peakIn;peakOut;peakSearcher;pilotScValid;pilotScValidOut;polarity;pop;psduLen;psduLenOut;psduLength;puncVec;puncVecSelector;push;rateMapping;rdAddr;rd_dout;readStart;ready;readyCounter;reset;resetOut;rgSc;rowCounter;rst;rstIn;rstOut;rxBits;rxData;rxDataOut;rxTimeVHT;rxValid;rxValidOut;sample counter;sampleAndHold;sampleDataForDisplay;sampleIn;sampleParallel;searchStartOfFrame;signBit;signalCRCStatus;signalParity;signalParityStatus;start;startIn;startOut;storingSignalFields;streamSynchrnizer;switch;symbCount;symbNum;symbNum ;symbNumOut;symbRst;symbol counter;symbolDemodulator;symbolRst;syncEn;syncOut;syncStart;thresholdValid;trigger;txData;txDataOut;txValid;txValidOut;txvalid;u;updatedPsduLen;valid;validData;validForEqualization;validIn;validOut;vhtCRCRefBit;vhtCRCRefBitValid;vhtCRCRefBitVld;vhtCRCRefBits;vhtCRCRefBitsVld;vhtCRCVld;vhtRotation;vhtSigB;vhtSigBBitVld;vhtSigBDecoding;vhtSigBVld;vhtSigCRCBit;vhtSigCRCVld;vitInputLen;vitInputLenCalc;vitOut;wrAddr;wrValid;wr_din;x;y

BLOCKTYPE:
Abs;ArithShift;Bias;Bit Clear;Bit Set;Bit Shift;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Complex to Magnitude-Angle;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;Delay;Demux;Depuncturer;Discrete FIR Filter;Display;DownSample;EnablePort;Extract Bits;From;Gain;General CRC Generator HDL Optimized;General CRC Syndrome Detector HDL Optimized;Goto;HDL Counter;HDL_FIFO;Info;Inport;Logic;LookupNDDirect;Lookup_n-D;MATLABSystem;ManualSwitch;Math;MultiPortSwitch;NCO;OFDM Channel Estimator;OFDM Demodulator;OFDM Equalizer;Outport;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;Sample Control Bus Creator;Simple Dual-port RAM;StateControl;Sum;Switch;Symbol Demodulator;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;Viterbi Decoder

BLOCKTYPE_FREQUENCY:
4;41;2;2;2;3;6;3;253;26;8;13;462;2;84;2415;79;2;4;7;23;2;12;79;52;2;2;79;276;18;1;1789;761;42;40;2;1;14;40;4;4;2;4;1517;102;7;201;31;79;12;32;4;223;201;4;140;4;4;116;18;4

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices;Wireless HDL Toolbox


MODELNAME: zynqRadioHWSWWLANAD9361AD9364SL_UDP_Receive
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWWLANAD9361AD9364SL_UDP_Receive.slx
ANNOTATION: Zynq Radio Host UDP Receive Model Copyright 2022 The MathWorks, Inc.
BLOCKTYPE: ConstellationDiagram;DataTypeConversion;Display;EnablePort;Inport;Outport;Selector;UDP Receive
BLOCKTYPE_FREQUENCY: 1;2;7;2;3;14;7;2
CHECKSUM: 241CEA296BAAD379C739C324CBAEB533
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Constellation Diagram;Control Scope;Data Type Conversion;Display;Enable;In;Reference;Selector;Status Signals;SubSystem;UDP Receive Constellation;UDP Receive Status;Visualize Constellation;decodedMCS;frameFormat;freqOffset;packetDetected;psduLen;signalCRCStatus;signalParityStatus;statusSignals


MODELNAME: zynqRadioHWSWWLANAD9361AD9364SL_interface
PATH: toolbox/shared/sdr/sdrz/sdrzdemos/zynqRadioHWSWWLANAD9361AD9364SL_interface.slx
BLOCKTYPE_FREQUENCY: 7;3;1;1;5;17;1;1;1;14;1;1;14;1;2;1;1
CHECKSUM: 0B2F23F920D95D57C3C001AD7DB03199
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Status Signal Generator Generated by HDL Workflow Advisor on 21-Jan-2022 23:17:21  Generate Status Signals to monitor Outside FPGA WLAN Transmit and Receive  For out-of-range MCS values, 3 is applied for Non-HT, 2 is applied for HT-MF and VHT. ARM Algorithm to SDR Transmitter SDR Receiver to ARM Algorithm ARM Interface to HW User Logic Zynq Radio WLAN Software Interface Model Unused Ports  The input port data is non-functional and terminated inside the subsystem. Tx Control  MCS: {0,1,2,3} =&gt; Non-HT {0,1,2} =&gt; HT-MF {0,1,2} =&gt; VHT Display Control  Double-click the Switch block to toggle between header and data constellations. Copyright 2023 The MathWorks, Inc. Open host model  Double-click the block to open the host model.  MCS: {0,1,2,3,5,6,7} =&gt; Non-HT {0,1,2,3,5,6,7} =&gt; HT-MF {0,1,2,3,5,6,7} =&gt; VHT  If Higher MCS Support if enabled Tx Control

BLOCK:
AD936x Receiver;AD936x Transmitter;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_decodedMCS;AXI4SlaveRead_frameFormatOut;AXI4SlaveRead_freqOffset;AXI4SlaveRead_packetDetected;AXI4SlaveRead_psduLen;AXI4SlaveRead_signalCRCStatus;AXI4SlaveRead_signalParityStatus;AXI4SlaveWrite;AXI4SlaveWrite_MCS;AXI4SlaveWrite_frameFormat;AXI4SlaveWrite_headerView;Constant;Data Type Conversion;DataTypeConversion;Decode Status Signals;Display;Enable;In;Info;MCS;Manual Switch;Reference;SubSystem;UDP Receive Model;UDP Send;UDP Visualize Constellation;Vector Concatenate;WLAN HDL;decodedMCS;frameFormat;frameFormatOut;freqOffset;headerView;packetDetected;psduLen;signalCRCStatus;signalParityStatus

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Concatenate;Constant;DataTypeConversion;Display;EnablePort;Info;Inport;ManualSwitch;Model Source;Outport;System Start;UDP Send;comm.SDRRxAD936x;comm.SDRTxAD936x


MODELNAME: usrpe3xxHWSWADSBSL
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWADSBSL.slx
BLOCKTYPE_FREQUENCY: 2;2;2;1;1;1;12;2;26;2;1;2;3;3;1;3;4;1;36;6;1;2;1;27;1;2;1;2;3;2;1;4;2;1;9
CHECKSUM: 3FD8E92FA0EBE30B847ADF024451AAB8
PRODUCT_BASECODE: USRPEMBED
ANNOTATION:
delay of the approximation is 4 clock clyces - delay valid signal to account for this sqrt(I^2+Q^2) can be approximated as |L|+0.4*|S|, where |L| is the absolute value of the larger of I or Q, and |S| is the absolute value of the smaller of I or Q. See |L|+0.4|S| Algorithm on page 238 in Digital Signal Processing in Communication Systems by Marvin Frerking.  Type Conversion from 12bit int16to 16bit_15 (0:1) Samples to Frames  Target an ADS-B Airplane Tracker Using USRP(R) E3xx and HW/SW Co-Design Workflow  Copyright 2016-2019 The MathWorks, Inc. Tx and Rx Hardware Algorithms Simulate RF-card Bit-Shift Rx ARM Algorithm

BLOCK:
; Demux ; SFunction ; Terminator ;1-D Lookup Table;AND;Abs;ActivateBP;Add;Bit Process;Bit Shift;Bit-Shift;CalcSyncCorr;Calculate Threshold;Compare To Constant;Compare To Zero;Complex Modulus;Complex to Real-Imag;Compute CRC and Frame validation;Constant;CurrentBit;Data Type Conversion;Delay;Delay Enable;Deserializer1D;Discrete FIR Filter;Enabled Delay;Falling Edge Detector;Frame Bit Out;From;Gain;General CRC Syndrome HDL Optimized;Goto;HDL Counter;HDLRxIpCore;HDLTxIpCore;HDL_ADSB;ImagIn;In;Info;Logical;Logical Operator;MATLAB Function;MagOut;MinMax;Multiport Selector;Out;PrepInputs;Product;Real-Imag to Complex;RealIn;Reference;Relational Operator;Reset;Rising Edge Detector;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_In;RxValid_Out;Scaling;Scope;Signal Specification;State Control;SubSystem;Subtract;Switch;SyncCorr;Tapped Delay;Terminator;Threshold;Threshold ;Timing Control;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxTransmitPeriod;TxValid_In;TxValid_Out;Valid Generation;ValidBit;ValidFrame;ValidOut;XOR;dataIn;dataLength;dataOut;dataReceived;dataValidIn;in;out;signal spec;validIn;validOout;validOut

BLOCKTYPE:
Abs;Bit Shift;Compare To Constant;Compare To Zero;Complex Modulus;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;Deserializer1D;DiscreteFir;From;Gain;General CRC Syndrome Detector HDL Optimized;Goto;HDL Counter;Info;Inport;Logic;Lookup_n-D;MinMax;Multiport Selector;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Scope;SignalSpecification;StateControl;Sum;Switch;Tapped Delay Line;Terminator

PRODUCT:
Communications Toolbox;Communications Toolbox Support Package for USRP Embedded Series Radio;DSP System Toolbox;Fixed-Point Designer;MATLAB;Simulink


