# MODELS

MODELNAME: usrpe3xxHWSWADSBSL_interface
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWADSBSL_interface.slx
BLOCKTYPE_FREQUENCY: 2;1;1;3;2;1;1;1;5;1;1;1;1;1;1
CHECKSUM: 8AD9E196D8BE74B452C332D987D80A77
PRODUCT_BASECODE: USRPEMBED
ANNOTATION:
Generated by HDL Workflow Advisor on 01-Aug-2018 14:26:30 USRP(R) E3xx Software Interface Model: usrpe3xxHWSWADBSL SDR Receiver to ARM Algorithm ARM Algorithm to SDR Transmitter ARM Interface to HW User Logic Copyright 2016-2019 The MathWorks, Inc.  Double click the block to open the host model and display detected ADS-B information Open host model

BLOCK:
AXI4LiteRead;AXI4LiteWrite;AXI4Lite_Write_Threshold;AXI4Lite_Write_Threshold_DTC;AXI4Lite_Write_TxTransmitPeriod;AXI4Lite_Write_TxTransmitPeriod_DTC;AXI4Reset;AXI4ResetModelSource;Complex to Real-Imag;Constant;Decode & Display HWSW;E3xx Receiver;E3xx Transmitter;Enable;HDL_ADSB;In;Info;Reference;Scaling;SubSystem;Subsystem;Terminator;Threshold;Threshold ;TxTransmitPeriod;UDP Send

BLOCKTYPE:
AXI4-Interface Write;AXI4-Lite/AXI4 Interface;ComplexToRealImag;Constant;DataTypeConversion;EnablePort;Gain;Info;Inport;Model Source;System Start;Terminator;UDP Send;comm.SDRRxE3xx;comm.SDRTxE3xx

PRODUCT:
Communications Toolbox Support Package for USRP Embedded Series Radio;Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Simulink


MODELNAME: usrpe3xxHWSWAXI4StreamSL
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWAXI4StreamSL.slx
BLOCKTYPE_FREQUENCY: 2;1;3;2;1;2;12;6;25;1;2;3;3;3;1;33;7;2;1;25;4;1;1;1;1;2;1;1;2;13;3
CHECKSUM: BF118286C59806148B1D66F14394D3A5
PRODUCT: Communications Toolbox Support Package for USRP Embedded Series Radio;DSP System Toolbox;Simulink
PRODUCT_BASECODE: USRPEMBED
ANNOTATION:
SR AND - OR Latch Ignore any Backpressure exerted on DUT Generate new Valid signal Compute power of received signal Compute power of transmitted signal SR AND - OR Latch Select to transmit ramp or data stored in RAM Reset counter before and after loading new data Tx trigger  Tx RAM controller Dont apply backpressure to the RF Front End Shift left to prepare for 16-bit to 12-bit MSB interface at DAC Load Tx Data to RAM  HW/SW Co-Design AXI4-Stream Hardware Generation Model Display simulation results Tx and Rx hardware algorithms Copyright 2020 The MathWorks, Inc. Simulate model control

BLOCK:
AND;AXI4S_Data_In;AXI4S_Data_Out;AXI4S_Tready_In;AXI4S_Tready_Out;AXI4S_Valid_In;AXI4S_Valid_Out;AXIS_txData;AXIS_txWrite;Add;Bit Concat;Bit Shift;Bit Slice;Cast;Cast To Boolean;Compare To Constant;Complex to Real-Imag;Constant;Data Type Conversion;DataIn;Delay;Detect Change;Detect Increase;From;Goto;HDL Counter;HDL_DUT;In;Info;Max Tx Count;MaxTxCount;Multiport Switch;Mux;NOT;OR;Out;Product;Q;R;Real-Imag to Complex;Reference;Relational Operator;Rx;Rx1_Data_I_In;Rx1_Data_I_Out;Rx1_Data_Q_In;Rx1_Data_Q_Out;Rx2_Data_I_In;Rx2_Data_I_Out;Rx2_Data_Q_In;Rx2_Data_Q_Out;Rx_Data_In;Rx_Data_P;Rx_Tready_In;Rx_Valid_In;Rx_Valid_Out;S;SR-Latch;Scope;Serializer1D;Shift Arithmetic;Simple Dual Port RAM;Simulate 12-to-16bit ADC interface;Simulate 16-to-12bit DAC interface;Step;SubSystem;Terminator;Tx;Tx Data;Tx Select;Tx Start;Tx1_Data_I_In;Tx1_Data_I_Out;Tx1_Data_Q_In;Tx1_Data_Q_Out;Tx_Data_In;Tx_Data_Out;Tx_Data_P;Tx_Tready_Out;Tx_Valid_In;Tx_Valid_Out;Unit Delay;Valid_Out;Write Tx Data;maxTxCount;txSEL;txSel;txStart

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bit Slice;Compare To Constant;ComplexToRealImag;Constant;DataTypeConversion;Delay;Detect Change;Detect Increase;From;Goto;HDL Counter;Info;Inport;Logic;MultiPortSwitch;Mux;Outport;Product;RealImagToComplex;RelationalOperator;Scope;Serializer1D;Signal From Workspace;Simple Dual-port RAM;Step;Sum;Terminator;UnitDelay


MODELNAME: usrpe3xxHWSWAXI4StreamSL_interface
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWAXI4StreamSL_interface.slx
BLOCKTYPE_FREQUENCY: 3;1;10;3;2;1;1;10;1;2;1;1;1;1;3;1;1;1;1;1;1
CHECKSUM: FADB0EEC93C6EA4A98EA0B8FA76F996A
PRODUCT_BASECODE: USRPEMBED
ANNOTATION:
Generated by HDL Workflow Advisor on 10-Dec-2020 10:55:47 Shift left to prepare for 16-bit to 12-bit MSB interface at DAC Loads selected waveform on initialization Zynq-7000 IIO Radio Software Interface Model: usrpe3xxHWSWAXI4StreamSL_interface SDR Receiver to ARM Algorithm ARM Algorithm to SDR Transmitter  Double click the block to open the host model. Open host model ARM Interface to HW User Logic  2. Select data source  1. Select waveform to load  3. Toggle switch to transmit waveform Copyright 2020 The MathWorks, Inc.

BLOCK:
AXI4-Stream IIO Read;AXI4-Stream IIO Write;AXI4Reset;AXI4ResetModelSource;AXI4SlaveWrite;AXI4SlaveWrite_maxTxCount;AXI4SlaveWrite_txSel;AXI4SlaveWrite_txStart;Chirp data;Constant;Data;DataTypeConversion;Detect Change;E3xx Receiver;E3xx Transmitter;Enable;HDL_DUT;Info;Internal ramp;MaxTxCount;Multiport Switch;OR;Reference;Sawtooth data;Send via UDP;Signal Select;Sinusoid data;Step;SubSystem;Subsystem;Switch;Terminator;Trigger;Triggered write;UDP Send;Waveform;Waveform from RAM;Write waveform to FPGA RAM;data;maxTxCount;txSel;txStart

BLOCKTYPE:
AXI4-Interface Write;AXI4-Lite/AXI4 Interface;Constant;DataTypeConversion;Detect Change;EnablePort;Info;Inport;Logic;ManualSwitch;Model Source;MultiPortSwitch;Step;System Start;Terminator;TriggerPort;UDP Send;comm.SDRRxE3xx;comm.SDRTxE3xx;matlabshared.libiio.axistream.read;matlabshared.libiio.axistream.write

PRODUCT:
Communications Toolbox Support Package for USRP Embedded Series Radio;Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Signal Processing Toolbox;Simulink


MODELNAME: usrpe3xxHWSWQPSKSL
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWQPSKSL.slx
CHECKSUM: 659623E4CC160B2D9BBF328F8846CAE0
PRODUCT_BASECODE: USRPEMBED
ANNOTATION:
 The burst data sent from the processing system will be stored in the RAM in the memory channel of SDR IIO radio. The data stored will be poped out as a stream data.   This subsystem does an equivalent operation to simulate the input and output behaviour of the memory channel of the SDR IIO radio.  Fixed point precision loss warnings are supressed in Mask Init Callback fixed point precision loss warning supressed for this subsystem store the value in the Reg before reset  Let Z be the complex Phase Ambiguity estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z))  Set this value to zero to disable phase ambiguity correction peak picker This subsystem generates variables required for QPSKRxVerification for validation Proportional-Plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence  HDL Data Scrambler Polynomial: x^7+x^4+1 Initial state: [1 0 1 1 1 0 1]  The Preamble is padded with zeros in the LUT such that the length is the 2^nextpow2(length(Preamble)) for efficient resource mapping to RAM  HDL Data Scrambler Polynomial: x^7+x^4+1 Initial state: [1 0 1 1 1 0 1] 2^32-1 will be treated as NaN in double when converted to double  HW/SW Co-design QPSK Transmitter and Receiver Using E3xx Hardware Generation Model  Copyright 2016-2023 The MathWorks, Inc.  Set rstCS port to true to reset the carrier synchronizer (CS) in the QPSK receiver

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AXI4S_Data_Out;AXI4S_Tready_In;AXI4S_Valid_Out;Add;Assertion;Automatic Gain Control;Average Estimates;BER;BIT_XOR;Bit Packetizer;Bit Shift;Bits to Char;Burst to Stream Conversion Equivalent;Bus Creator;Bus Selector;CFO;CFO step change detector;CPO;Capture Data Bits;Carrier Synchronizer;Coarse Frequency Compensator;Coarse Frequency Estimator;Compare To Constant;Complex to Magnitude-Angle;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Conj;Constant;Constellation Diagram;Correlation Time Scope;Correlator;DAC equivalent;Data Bits FIFO;Data Type Conversion;Data Type Duplicate;Delay;Delta;Demux;Direct Digital Synthesis;Direct Lookup Table (n-D);Discrete FIR Filter;Display;Divide by ;E;Enable;End Generator;Error Detector;External Message;Extract Bits;Extract Frequency;FIFO;Frame Counter;Frequency and Time Synchronizer;From;Function Impl;GTED;Gain;Gardner TED;Goto;H;HDL Counter;HDL Data Descrambler;HDL Data Scrambler;HDL_QPSK;In;Info;InputGen;Integ Reg;IntegOut;IntegValid;Integer Delay;Integrator;Interpolation Control;Interpolation Filter;K;L;LUT;LUTAddr;Logical Operator;Loop Filter;MATLAB Function;Magnitude Squared;Magnitude Squared and Moving Sum;Manual Switch;Math Function;Multiport Switch;Mux;NCO;NCO HDL Optimized;No HDL;Null;Out;Packet Controller;Peak Search;Phase Ambiguity Corrector;Phase Ambiguity Estimation and Correction;Phase Ambiguity Estimator;Phase Error Detector;PhaseError;Pop Counter;Preamble;Preamble Bits Generator;Preamble Bits Store;Preamble Detector;Prepare Inputs;Prepare Outputs;Product;Push Counter;QPSK Demodulator;QPSK Demodulator Baseband;QPSK Modulator;QPSK Modulator Baseband;QPSK Receiver Constellation ;QPSK Receiver Constellations ;QPSK Receiver Eye Diagram;QPSK Rx;QPSK Tx;QPSK Tx Channel QPSK Rx;RAM Frame Status Indicator;RRC Filter;RRC Receive Filter;RRC Transmit Filter;Raise Power to ;Rate Handle;Real-Imag to Complex;Reciprocal;Ref;Reference;Relational Operator;Reset Generator;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxIIn;RxQIn;RxVIn;RxValid_In;RxValid_Out;Send Payload Data;Serializer;Serializer1D;Signal Specification;Simple Dual Port RAM;State Register;Store Reg;SubSystem;Subsystem;Sum;Switch;Symbol Counter;Symbol Synchronizer;SyncPulse;Terminator;ThresholdLimiter;Timing Adjust;To Workspace;TxDataI_In;TxDataI_Out;TxDataQ_In;TxDataQ_Out;TxValid_In;TxValid_Out;Underflow;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Validate Input Push Pop;activeFrame;actualPreamble;avgEst;bitCount;bitErrors;bitReceived;bits;bitsCtrl;bitsOut;bitsValid;burstDataIn;captureASCII;channel;char;charOut;charValid;coarseFreq;corr;count;ctrlOut;data;dataEnd;dataIIn;dataIOut;dataIn;dataOut;dataQIn;dataQOut;dataReady;dataStart;datain;dir;displayReset;divide by ;done;e;empty;enb;enbExt;endIn;endOut;err;estOut;estimate;estimatedCoarseCFO;estin;expOut;extMsgActive;externalDataActive;externalMsg;externalMsgValid;externalRst;frameNumber;full;fullRAM;functionValues;gain;in;initial reset;insertCFO;insertCPO;internalRst;interpolant;manualRst;mu;nSynced;ncount;normCoarseFreqEst;normFreqEst;normFreqOut;normalisedFreq;normalisedPhase;normalizedFreqEst;numEntries;numOfFramesSynced;nxtBit;out;overAir;overAirDataIn;overAirValidIn;packetBits;phaseInc;pop;popEmpty;popEmptyDiag;popEmptyFIFO;preamble;preambleBits;printData;push;pushFull;pushFullDiag;pushFullFIFO;rd;reset;resetcounter;rst;rstCS;rxBus;rxCtrlOut;rxDataOut;rxDiagBus;sample discard controller;sampleCount;sampleCountValid;scaled;start;startIn;startOut;streamDataIOut;streamDataQOut;strobe;success;switch;syncPulse;syncPulseIn;syncPulseOut;threshold;thresholdExceeded;timing Reference;timing Reference Long;timingOffset;timingOffsetValid;txDataOut;txDiagBus;txValidOut;u;userBits;userBitsValid;v;valid;valid pop;valid push;validIn;validOut;validPop;wr;x;y

BLOCKTYPE:
ArithShift;Assertion;Bit Shift;BusCreator;BusSelector;Compare To Constant;Complex to Magnitude-Angle;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;EnablePort;Extract Bits;EyeDiagramBlock;From;Gain;Goto;HDL Counter;Info;Inport;Logic;LookupNDDirect;Lookup_n-D;ManualSwitch;Math;MultiPortSwitch;Mux;NCO;Outport;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;RealImagToComplex;RelationalOperator;S-Function;Scope;Serializer1D;SignalSpecification;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous

BLOCKTYPE_FREQUENCY:
1;2;1;3;2;31;2;8;26;3;47;2;354;11;3;5;8;12;1;3;11;3;27;1;221;53;4;2;4;8;4;1;3;171;19;1;1;3;4;10;1;2;1;2;25;13;20;7;25;18

PRODUCT:
Communications Toolbox;Communications Toolbox Support Package for USRP Embedded Series Radio;DSP HDL Toolbox;Fixed-Point Designer;HDL Coder;MATLAB;Simulink


MODELNAME: usrpe3xxHWSWQPSKSL_hostUDPReceive
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWQPSKSL_hostUDPReceive.slx
ANNOTATION: Copyright 2016-2022 The MathWorks, Inc. USRP(R) E3xx Host UDP Receive Model: usrpe3xxHWSWQPSKSL
BLOCKTYPE_FREQUENCY: 4;1;1;6;2;4;3;1;1;4;4;1;1;1;1;1;3
CHECKSUM: 1E6A4DF7CCAF59EC5F99864CB7E7D0E5
PRODUCT_BASECODE: USRPEMBED
BLOCK:
 Demux ; SFunction ; Terminator ;Bit Errors;Bits Received;Compare To Constant;Constant;Constellation Diagram;Data Type Conversion;Demux;Enable;Estimated Coarse CFO;Gain;In;Info;MATLAB Function;Number of Frames Synced;Reference;Serializer1D;SubSystem;Subsystem;Switch;UDP Receive;bitErrors;bitsReceived;captureASCII;estCoarseFreq;nSynced;packetBits;printData;u

BLOCKTYPE:
Compare To Constant;Constant;ConstellationDiagram;DataTypeConversion;Demux;Display;EnablePort;Gain;Info;Inport;Outport;S-Function;Serializer1D;Switch;Terminator;ToWorkspace;UDP Receive

PRODUCT:
Communications Toolbox;Communications Toolbox Support Package for USRP Embedded Series Radio;Embedded Coder;Simulink


MODELNAME: usrpe3xxHWSWQPSKSL_interface
PATH: toolbox/shared/sdr/sdrz/usrpe3xxdemos/usrpe3xxHWSWQPSKSL_interface.slx
BLOCKTYPE_FREQUENCY: 4;6;1;7;14;1;3;2;1;20;2;4;1;9;1;1;3;1;1;1
CHECKSUM: 412551F9BEF9823BE31A22873FFE34C4
PRODUCT_BASECODE: USRPEMBED
ANNOTATION:
2^32-1 will be treated as NaN in double in UDP Receive Model ARM Interface to HW User Logic Copyright 2016-2022 The MathWorks, Inc. SDR Receiver to ARM Algorithm ARM Algorithm to SDR Transmitter USRP(R) E3xx Software Interface Model: usrpe3xxHWSWQPSKSL  Double click the block to open the host model. Open host model

BLOCK:
AXI4-Stream IIO Read;AXI4Reset;AXI4ResetModelSource;AXI4SlaveRead;AXI4SlaveRead_bitErrors;AXI4SlaveRead_bitReceived;AXI4SlaveRead_estimatedCoarseCFO;AXI4SlaveRead_numOfFramesSynced;AXI4SlaveWrite;AXI4SlaveWrite_displayReset;AXI4SlaveWrite_externalDataActive;AXI4SlaveWrite_insertCFO;AXI4SlaveWrite_insertCPO;AXI4SlaveWrite_overAir;AXI4SlaveWrite_rstCS;CFO;CPO;Constant;Data Type Conversion;DataTypeConversion;Delay;Display;E3xx Receiver;E3xx Transmitter;Enable;External Message;HDL_QPSK;In;Info;Logical Operator;Manual Switch;Reference;SubSystem;Subsystem;Switch;UDP Send;UDP Send ;Vector Concatenate;bitErrors;bitReceived;displayReset;enbExt;estimatedCoarseCFO;externalDataActive;initial reset;insertCFO;insertCPO;numFramesSynced;numOfFramesSynced;overAir;packetBits;rstCS

BLOCKTYPE:
AXI4-Interface Read;AXI4-Interface Write;Concatenate;Constant;DataTypeConversion;Delay;Display;EnablePort;Info;Inport;Logic;ManualSwitch;Model Source;Outport;Switch;System Start;UDP Send;comm.SDRRxE3xx;comm.SDRTxE3xx;matlabshared.libiio.axistream.read

PRODUCT:
Communications Toolbox Support Package for USRP Embedded Series Radio;Embedded Coder;Embedded Coder Support Package for Xilinx Zynq Platform;Fixed-Point Designer;MATLAB;Simulink


MODELNAME: CameraSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/CameraSensorExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2018 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;9;4;8;2;5;2;3;2;1;1;2;3;2;4;4;2;4;2;1;2
CHECKSUM: 52EC7F2AB2BD362F05FBB86500C86089
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Acc;Bicycle Model - Force Input;Brake;Bus Selector;Constant;Cont LPF;Decel;Gain;Gear;Knob;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Camera;Simulation 3D Config;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;Video Viewer;X;X_Out;Y;Y_Out;deg_Out;psi;xdot

BLOCKTYPE:
BusSelector;Constant;Gain;Inport;KnobBlock;Outport;Product;Saturate;SignalSpecification;Simulation 3D Camera;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral;VideoViewer


MODELNAME: DLCReferenceApplicationGetSet
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/DLCReferenceApplicationGetSet.slx
CHECKSUM: EE0D5B5316D88902C9319B3C3B6F62E4
PRODUCT: MATLAB;Simscape Electrical;Simulink;Stateflow;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
ANNOTATION:
 1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Determine if next gear will be higher or lower than current gear  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching.  1) Add Subsystem or Model blocks as valid variant choices. 2) You cannot connect blocks at this level. At simulation, connectivity is automatically determined, based on the active variant and port name matching. Vehicle Response Driver Commands Copyright 2018-2019 The MathWorks, Inc.

BLOCK:
 Demux ; Driver; Gear; SFunction ;1-D Lookup Table;10ms Function-Call Generator;3D Engine;3D Engine Disabled;<Accel>;<Kappa>;Abs;Acc to Torque Request;AccCmd;Accel;AccelGround;Acceleration Cmd;Active Differential Control;Add;AllParts;Alpha;AxlTrq;Bang Bang ABS;Bang-bang controller;Beta;Body;Body Ptich;Body Roll;Body Yaw;Body, Suspension, Wheels;BodyX;BodyY;BodyZ;Brake;Brake Cmd;Brake Controller;Brake Pressure Control;BrakeGround;BrkCmd;BrkPrs;BrkPrsCmd;Bus Creator;Bus Selector;Bus to Vector;Calculate Downshift Threshold;Calculate Upshift Threshold;CgXYZ;CgXYZdot;Cgaxyz;Cgxyzdot;Chassis;Cntrl;Compare To Constant;ConcatOut;Constant;Cont LPF;Controller;Controllers;Current Gear;Data Type Conversion;Dead Zone;Debounce;Demux;Detect Increase;DiffPrsCmd;Disabled;Display;DownReq;Driveline;Driveline Ideal Fixed Gear;Driver;Driver - No Clutch;Driver Commands;ECU;Enabled;Eng;EngSpd;EngTrq;EngTrq ;EngTrqCmd;Engine;Engine Tach [rpm];Entered Gate;Env;Environment;First Order Hold;Friction;From;Gain;Gear;GearCmd;GearGround;GearReq;GeomXYZ;GeomXYZdot;Gnd;Goto;Ground;Ground Feedback;Handwheel Angle [deg];ISO 15037-1:;Ideal Mapped Engine;InertAng;InertXYZ;InertXdotYdotZdot;Integrator;Kappa;Lane;Lane Change;Lane Change Reference Generator;Lateral Acceleration [g];Linear Predictive Driver;Logical Operator;Longitudinal Driver;Max;Mux;Neutral;Neutral Select;No Control;Omega;Open Loop;Open Loop Constant Radius;Operator;Paddles;Part Rotation Concatenation;Part Translation Concatenation;PartConcatenation;PassVeh14DOF;PassVeh7DOF;Passenger Vehicle;Passenger Vehicle Ray Trace Set;Predictive Driver;Pref;Product;Prop Shaft Speed LPF;PropShftSpd;PrpSpd;Rate Transition;Rear Diff Controller;RefXYZ;Reference;Relational Operator;Reshape;Rev Limiter Control;Saturation;Scale;ScaleOut;Selector;Signal Copy;Signal Specification;Simulation 3D Config;Simulation 3D Message Get;Simulation 3D Message Set;Simulation 3D Vehicle;SpdThr;Speed [mph];Stair Generator;Steer;Steer vs Ay;Steer, Velocity, Lat Accel;SteerCmd;SteerGround;SteerHWCmd;Steering;Steering, Transmission, Driveline and Brakes;StrWhlTrq;SubSystem;Subsystem;Subtract;Sum;Switch;TCM;TCM Shift Controller;Terminator;Transmission Controller;Trq Cmd;TrqCmd;TrqCmdRevLimited;Unary Minus;Unit Conversion;UpReq;Vector Concatenate;VehFdbk;VehRef;VehSpdFdbk;Vehicle XY Plotter;Visualization;Wheel Angle Limit * Steer Ratio;WheelFrontLeft;WheelFrontLeft Pitch;WheelFrontLeft Roll;WheelFrontLeft Yaw;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRight Pitch;WheelFrontRight Roll;WheelFrontRight Yaw;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeft Pitch;WheelRearLeft Roll;WheelRearLeft Yaw;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRight Ptich;WheelRearRight Roll;WheelRearRight Yaw;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels;WhlAng;Wind;WindXYZ;XWheel;YWheel;YawRate;Zend Select;angles;calc;calc_down;calc_up;down_th;dzWheel;f;function;gear;in_;kappa;mu;out_;pedal;pqr;prop speed to vehicle speed;speed;up_th;xdot

BLOCKTYPE:
3D Engine;Abs;BusCreator;BusSelector;BusToVector;CircularGaugeBlock;Compare To Constant;Concatenate;Constant;DataTypeConversion;DeadZone;Demux;Detect Increase;DiscreteTransferFcn;DiscretizedDiscreteTransferFcn;Display;Double Lane Change Source;FirstOrderHold;From;Function-Call Generator;Gain;Goto;Ground;ISO 15037-1:2006;Inport;Integrator;LampBlock;LinearGaugeBlock;Logic;Longitudinal Driver;Lookup_n-D;MinMax;ModelReference;Mux;Outport;Predictive Driver;Product;RateTransition;RelationalOperator;Reshape;S-Function;Saturate;Scope;Selector;SemiCircularGaugeBlock;Sign;SignalConversion;SignalSpecification;Simulation 3D Message Get;Simulation 3D Message Set;Simulation 3D Scene Configuration;Simulation 3D Vehicle;Stair Generator;Sum;Switch;Terminator;TriggerPort;UnaryMinus;UnitConversion;UnitDelay;Vehicle Terrain Sensor;Vehicle XY Plotter;XY scope.

BLOCKTYPE_FREQUENCY:
1;5;22;33;4;3;3;25;32;17;4;19;1;2;1;2;1;3;6;1;9;5;11;1;180;3;2;3;4;1;6;2;5;5;80;1;3;14;5;2;2;6;3;3;3;1;3;26;1;1;1;1;1;8;5;27;5;3;22;2;1;2;1

EXTERNALFILE_REFERENCE:
Driveline___Model_Block___PassVeh14DOF___Model_Block___PassVeh7DOF___Model_Block___SiMappedEngineV___Model_Block___


MODELNAME: DepthSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/DepthSensorExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2018 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;9;5;8;2;5;2;4;2;1;1;2;3;2;4;4;2;4;2;1;3
CHECKSUM: 480EDB27DDCFE58D14595D73AE4E3BD3
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Acc;Bicycle Model - Force Input;Brake;Bus Selector;Constant;Cont LPF;Decel;Gain;Gear;Knob;Multiply;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Config;Simulation 3D Depth Sensor;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;Video Viewer;X;X_Out;Y;Y_Out;deg_Out;psi;xdot

BLOCKTYPE:
BusSelector;Constant;Gain;Inport;KnobBlock;Outport;Product;Saturate;SignalSpecification;Simulation 3D Depth Sensor;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral;VideoViewer


MODELNAME: FisheyeCameraExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/FisheyeCameraExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2018 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;9;4;8;2;5;2;3;2;1;1;2;3;2;4;4;2;4;2;1;2
CHECKSUM: 96A506AA85343E208297CDDBD03C271F
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Acc;Bicycle Model - Force Input;Brake;Bus Selector;Constant;Cont LPF;Decel;Gain;Gear;Knob;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Config;Simulation 3D Fisheye Camera;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;Video Viewer;X;X_Out;Y;Y_Out;deg_Out;psi;xdot

BLOCKTYPE:
BusSelector;Constant;Gain;Inport;KnobBlock;Outport;Product;Saturate;SignalSpecification;Simulation 3D Fisheye Camera;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral;VideoViewer


MODELNAME: GroundTruthSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/GroundTruthSensorExample.slx
BLOCKTYPE_FREQUENCY: 4;2;2;2;1;1;1;1;1
CHECKSUM: 72F49ED88DCC5FD61506FDF5A33E3F47
PRODUCT: Computer Vision Toolbox;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Constant;Display;Out;PID Controller;Reference;Simulation 3D Camera;Simulation 3D Scenario Reader;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;To Video Display

BLOCKTYPE:
Constant;Display;MATLABSystem;Outport;PID 1dof;Simulation 3D Camera;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;To Video Display


MODELNAME: IdealCameraSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/IdealCameraSensorExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2018 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;2;9;4;8;2;5;2;3;2;2;3;2;4;4;2;4;2;1;2
CHECKSUM: 7AFD959EBC2D878BD33DC90AF3FC34A0
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Acc;Bicycle Model - Force Input;Brake;Bus Selector;Constant;Cont LPF;Decel;Gain;Gear;Knob;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Camera Get;Simulation 3D Config;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;Video Viewer;X;X_Out;Y;Y_Out;deg_Out;psi;xdot

BLOCKTYPE:
3D Scene Camera;3D Sim Scene Setup;BusSelector;Constant;Gain;Inport;KnobBlock;Outport;Product;Saturate;SignalSpecification;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral;VideoViewer


MODELNAME: LidarSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/LidarSensorExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2019 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;9;2;4;9;2;5;2;2;3;2;1;1;2;3;2;4;5;2;4;2;1
CHECKSUM: 006EB47928F1175A51E2D6207F64F730
PRODUCT: MATLAB;Simulink;UAV Toolbox;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
 Demux ; SFunction ; Terminator ;Acc;Bicycle Model - Force Input;Brake;Bus Selector;Constant;Cont LPF;Decel;DisplayPointCloud;Gain;Gear;Knob;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Config;Simulation 3D Lidar;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;X;X_Out;Y;Y_Out;deg_Out;pointCloud;psi;xdot

BLOCKTYPE:
BusSelector;Constant;Demux;Gain;Inport;KnobBlock;Outport;Product;S-Function;Saturate;SignalSpecification;Simulation 3D Lidar;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral


MODELNAME: ProbabilisticRadarSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/ProbabilisticRadarSensorExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2019 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;9;4;8;2;6;2;3;2;1;1;2;1;3;2;4;4;2;4;2;1
CHECKSUM: FEF2CEFA2C9CAF6EABA00B08C6B17ADE
PRODUCT: Simulink;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Acc;Bicycle Model - Force Input;Brake;Bus Selector;Constant;Cont LPF;Decel;Gain;Gear;Knob;Out;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Config;Simulation 3D Probabilistic Radar;Simulation 3D Probabilistic Radar Config;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;X;X_Out;Y;Y_Out;deg_Out;psi;xdot

BLOCKTYPE:
BusSelector;Constant;Gain;Inport;KnobBlock;Outport;Product;Saturate;SignalSpecification;Simulation 3D Probabilistic Radar;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;Simulation3DProbabilisticRadarConfig;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral


MODELNAME: RadarSensorExample_MCity
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/RadarSensorExample_MCity.slx
BLOCKTYPE_FREQUENCY: 19;46;3;5;65;2;3;2;23;5;4;1;1;1;2;3;3
CHECKSUM: A699A11E761E360564D93B3452798F66
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
ANNOTATION:
Displays Controller  3D Write Dynamics and Controls Stub  3D Read  Copyright 2017-2018 The MathWorks, Inc.

BLOCK:
 Multiport Switch;AllParts;Body;BodyP;BodyR;BodyX;BodyY;BodyZ;Brake;BrakeCmd;BrakeIn;Car X;Car Y;ConcatOut;Constant;Controller and Display;Diff;Display;Gain;Idx;MATLAB System;Manual Switch;Out;PartConcatenation;Plant;Reference;Rotate;RotateOut;Rotation;Scale;ScaleOut;Scene Config;Simulation 3D Actor Transform Get;StatEn;SteerCmd;SteerIn;Steering;Steering gain;SubSystem;Subsystem;Switch;ThrCmd;Throttle;ThrottleIn;Translate;Translation;TranslationOut;VehDynamicsStub;VehRoateOut;VehRotOut;VehScaleOut;VehSclOut;VehSpd;VehTranslateOut;VehTrnsOut;VehYaw;Vehicle Actor Transform Set;Vehicle Speed;Vehicle Yaw;Vehicle Yaw gain;VehicleActorTransform;WheelFrontLeft;WheelFrontLeftP;WheelFrontLeftR;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRightP;WheelFrontRightR;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeftP;WheelRearLeftR;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRightP;WheelRearRightR;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels pitch;X;X gain;Xdyn;Y;Y gain;Yaw Gain;Ydyn;cos;sin

BLOCKTYPE:
Concatenate;Constant;Display;Gain;Inport;MATLABSystem;ManualSwitch;MultiPortSwitch;Outport;PID 1dof;Product;Simulation 3D Actor Transform Get;Simulation 3D Actor Transform Set;Simulation 3D Scene Configuration;Sum;Switch;Trigonometry


MODELNAME: RayTraceSensorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/RayTraceSensorExample.slx
BLOCKTYPE_FREQUENCY: 19;48;2;2;5;66;2;3;2;27;5;4;2;1;2;1;1;2;3;2;1;3
CHECKSUM: A363490CCBF937EF44CF050AC16890BA
PRODUCT: Computer Vision Toolbox;MATLAB;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
ANNOTATION:
Displays Controller  3D Write Dynamics and Controls Stub  3D Read  Copyright 2017-2018 The MathWorks, Inc.

BLOCK:
 Demux ; Multiport Switch; SFunction ; Terminator ;AllParts;Body;BodyP;BodyR;BodyX;BodyY;BodyZ;Brake;BrakeCmd;BrakeIn;CamRotOut;CamTrnsOut;Camera;Camera Relative Transform;CameraActorTransform;CameraRotation;CameraTranslation;Car X;Car Y;ConcatOut;Constant;Controller and Display;Diff;Display;Gain;HitPoints Display;Idx;MATLAB System;Manual Switch;Out;PartConcatenation;Plant;Reference;Rotate;RotateOut;Rotation;Scale;ScaleOut;Scene Config;Simulation 3D Actor Transform Get;StatEn;SteerCmd;SteerIn;Steering;Steering gain;SubSystem;Subsystem;Switch;ThrCmd;Throttle;ThrottleIn;To Video Display;Translate;Translation;TranslationOut;VehDynamicsStub;VehRoateOut;VehRotOut;VehScaleOut;VehSclOut;VehSpd;VehTranslateOut;VehTrnsOut;VehYaw;Vehicle Actor Transform Set;Vehicle Speed;Vehicle Yaw;Vehicle Yaw gain;VehicleActorTransform;WheelFrontLeft;WheelFrontLeftP;WheelFrontLeftR;WheelFrontLeftX;WheelFrontLeftY;WheelFrontLeftZ;WheelFrontRight;WheelFrontRightP;WheelFrontRightR;WheelFrontRightX;WheelFrontRightY;WheelFrontRightZ;WheelRearLeft;WheelRearLeftP;WheelRearLeftR;WheelRearLeftX;WheelRearLeftY;WheelRearLeftZ;WheelRearRight;WheelRearRightP;WheelRearRightR;WheelRearRightX;WheelRearRightY;WheelRearRightZ;Wheels pitch;X;X gain;Xdyn;Y;Y gain;Yaw Gain;Ydyn;cos;sin;u

BLOCKTYPE:
Concatenate;Constant;Demux;Display;Gain;Inport;MATLABSystem;ManualSwitch;MultiPortSwitch;Outport;PID 1dof;Product;S-Function;Simulation 3D Actor Transform Get;Simulation 3D Actor Transform Set;Simulation 3D Camera Get;Simulation 3D Scene Configuration;Sum;Switch;Terminator;To Video Display;Trigonometry


MODELNAME: SemanticSegmentationExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/SemanticSegmentationExample.slx
ANNOTATION: Trivial Braking Trivial Powertrain Copyright 2017-2019 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;9;2;4;9;2;6;2;2;3;2;1;1;2;3;2;4;5;2;4;2;1;2
CHECKSUM: 5E2DECD5EB69C1A39334105685E1EB96
PRODUCT: Computer Vision Toolbox;Simulink;Vehicle Dynamics Blockset;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
 Demux ; SFunction ; Terminator ;Acc;Bicycle Model - Force Input;Brake;Bus Selector;Class ID to labeled image;Constant;Cont LPF;Decel;Gain;Gear;Knob;Product;Reference;SAE to ISO;Saturation;Signal Specification;Simple Driveline;Simulation 3D Config;Simulation 3D Semantic Segmentation Sensor;Simulation 3D Vehicle with Ground Following;Simulation 3D Vehicle with Ground Following ;Slider;Steer;SubSystem;Subtract;Switch;Terminator;Throttle;Total Tractive Force;Trigonometric Function;Unary Minus;Unit Conversion;Video Viewer;X;X_Out;Y;Y_Out;classIDs;deg_Out;labeledImage;psi;xdot

BLOCKTYPE:
BusSelector;Constant;Demux;Gain;Inport;KnobBlock;Outport;Product;S-Function;Saturate;SignalSpecification;Simulation 3D Scene Configuration;Simulation 3D Semantic Segmentation Sensor;Simulation 3D Vehicle with Ground Following;SliderBlock;Sum;Switch;Terminator;Trigonometry;UnaryMinus;UnitConversion;Vehicle Body 3DOF Lateral;VideoViewer


MODELNAME: Sim3DVisionDetectionExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/Sim3DVisionDetectionExample.slx
ANNOTATION: Debugging Right cross Circular motion Ego vehicle Left cross
BLOCKTYPE_FREQUENCY: 7;8;7;3;2;5;4;1;4;2;3;1
CHECKSUM: 9C48D0A4784C421255F7CBF5A15D336F
PRODUCT: Automated Driving Toolbox;MATLAB;Simulink
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Add;Bus Selector;Constant;Cos;Display;Gain;MATLAB System;Ramp;Reference;Selector;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;Vision Detection Generator

BLOCKTYPE:
BusSelector;Constant;Display;Gain;MATLABSystem;Ramp;Selector;Simulation 3D Scene Configuration;Simulation 3D Vehicle with Ground Following;Sum;Trigonometry;visionDetectionGenerator


MODELNAME: Simulation3DGenericActorExample
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/Simulation3DGenericActorExample.slx
ANNOTATION: Copyright 2022 The MathWorks, Inc.
BLOCKTYPE: Assignment;Constant;MATLABSystem;PID 1dof;Scope;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;2;2;1;2;1
CHECKSUM: 039445D95FC69C137C833A10E569C0DB
PRODUCT: Automated Driving Toolbox;Simulink
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Assignment;Constant;PID Controller;Pyramid ;Pyramid 1 Translation;Pyramid 2 Rotation;Reference;Rotation;Simulation 3D Scene Configuration


MODELNAME: sim3d_Actor_ForEach_Example
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/ForEach/sim3d_Actor_ForEach_Example.slx
BLOCKTYPE: Bias;Constant;ForEach;Inport;Outport;Scope;Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;2;1;2;3;3;2;1
CHECKSUM: 8C927F6B22B055C78A774DFA4BAEAB12
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
For Each;For Each Subsystem;Instance;IsConstructed;IsSet;Out;Reference;Rotation;Simulation 3D Actor;Simulation 3D Scene Configuration;SubSystem;Transform;Translation


MODELNAME: sim3d_ForEach_Example
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/ForEach/sim3d_ForEach_Example.slx
BLOCKTYPE: ForEach;Inport;MATLABSystem;Outport;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;1;1;1;1
CHECKSUM: 25B53832538B06CBA94678FBA0B3A8B4
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
For Each;For Each Subsystem;In;MATLAB System;Out;Reference;Simulation 3D Scene Configuration;SubSystem


MODELNAME: Simulation3DActor_Example_1_Mesh_and_Texture_InitScript
BLOCK: Reference;Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE: Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;1
CHECKSUM: C701E5EC5BEE31D509D481EE3C4F0956
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
PATH:
toolbox/shared/sim3dblks/sim3dblksdemo/GettingStarted/Simulation3DActor_Example_1_Mesh_and_Texture_InitScript.slx


MODELNAME: Simulation3DActor_Example_2_Shape_InitScript
BLOCK: Reference;Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE: Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;1
CHECKSUM: D8CCC632FE4D1BE5874AF28F930F04FC
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
PATH:
toolbox/shared/sim3dblks/sim3dblksdemo/GettingStarted/Simulation3DActor_Example_2_Shape_InitScript.slx


MODELNAME: Simulation3DActor_Example_3_Animation_InitScript
BLOCK: Reference;Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE: Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;1
CHECKSUM: 348E97BE921606DC65F76F19ABA8F7FB
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
PATH:
toolbox/shared/sim3dblks/sim3dblksdemo/GettingStarted/Simulation3DActor_Example_3_Animation_InitScript.slx


MODELNAME: Simulation3DActor_Example_4_Cosimulation
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/GettingStarted/Simulation3DActor_Example_4_Cosimulation.slx
BLOCKTYPE_FREQUENCY: 1;3;1;1;1;1;3;1
CHECKSUM: 11BE9D9297E7B7D28D636866B4B3433C
PRODUCT: Computer Vision Toolbox;Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
BLOCK:
Assignment;Constant;Ramp;Reference;Simulation 3D Actor;Simulation 3D Camera Get;Simulation 3D Scene Configuration;Sum;To Video Display

BLOCKTYPE:
Assignment;Constant;Ramp;Simulation 3D Actor;Simulation 3D Camera Get;Simulation 3D Scene Configuration;Sum;To Video Display


MODELNAME: Simulation3DActor_Example_7_CAD_File_Import
BLOCK: Reference;Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE: Simulation 3D Actor;Simulation 3D Scene Configuration
BLOCKTYPE_FREQUENCY: 1;1
CHECKSUM: EB2E1572CB71B195160DD305615D0F75
PRODUCT: Simulink;Vehicle Dynamics Blockset
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
PATH:
toolbox/shared/sim3dblks/sim3dblksdemo/GettingStarted/Simulation3DActor_Example_7_CAD_File_Import.slx


MODELNAME: Smart4i_Example
PATH: toolbox/shared/sim3dblks/sim3dblksdemo/IAM_Smart4i_Example/Smart4i_Example.slx
BLOCKTYPE_FREQUENCY: 8;7;8;10;30;2;10;8;38;8;3;8;1;1;2;10;2;2
CHECKSUM: 1D6B38C5F4E602750B9FCB4DB2CA2E26
PRODUCT: MATLAB;Robotics System Toolbox;Simulink;Stateflow
PRODUCT_BASECODE: AE;DR;RO;VR;UV;VE
ANNOTATION:
Copyright 2022 The MathWorks, Inc. Copyright 2022 The MathWorks, Inc. Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Angles;Ball_Instance;Chart;Constant;Coordinate Transformation Conversion;Demux;Gain;Get Transform;ID;In;Interpreted MATLAB Function;Inverse Kinematics;L;MATLAB Function;Mux;Out;Prepare_World;R;Reference;Reshape;Robot;Shuttle;Shuttles;Simulation 3D Actor;Simulation 3D Scene Configuration;Stop Simulation;SubSystem;Subsystem;Unit Delay;XY-rotation;Z-location;attachBall;attachCup;ball_inst;cLoc;cupID;destroyCupPhys;detachBallPhys;detachCupPhys;f;findBallLoc;findCupLoc;id;r1_loc;r2_loc;stop;t;trans

BLOCKTYPE:
Constant;Demux;Gain;Get Transform;Inport;Inverse Kinematics;MATLABFcn;Mux;Outport;Reshape;S-Function;Simulation 3D Actor;Simulation 3D Scene Configuration;Stop;Terminator;TriggerPort;UnitDelay;robotics.slcore.internal.block.CoordinateTransformationConversion


MODELNAME: loop_open1
PATH: toolbox/shared/slcontrollib/signal_injection_plugin/m/showcase/loop_open1.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;1;1;2;1;1;1;3;3;9;1;1
CHECKSUM: 2CF2FD9D2A8EA47C2E2F676D4034689B
PRODUCT: Simulink;System Identification Toolbox
PRODUCT_BASECODE: ID
BLOCK:
AC;AD;BC;BD;CC;CD;Clock;Digital Clock;Gain;In;Loop Opening;Memory;Out;Ramp;Rate Transition;Reference;Scope;Signal Specification;SubSystem;Subsystem;Switch

BLOCKTYPE:
Clock;DigitalClock;Gain;Inport;LoopOpening;Memory;Outport;Ramp;RateTransition;Scope;SignalConversion;SignalSpecification;Switch


MODELNAME: ramp_signal_suite1
PATH: toolbox/shared/slcontrollib/signal_injection_plugin/m/showcase/ramp_signal_suite1.slx
BLOCKTYPE_FREQUENCY: 3;2;3;10;3;1;2;3;1;1;11;1
CHECKSUM: C990F9629D578E294FE325790CC29D7F
PRODUCT: Simulink;System Identification Toolbox
PRODUCT_BASECODE: ID
EXTERNALFILE_REFERENCE: gain1___Model_Block___
ANNOTATION:
Scalar virt Scalar non-virt Vector non-virt Vector virt Bus non-virt Bus virt Locked mask Bus expanded Scalar discrete Subsystem Normal model ref Copyright 2023 The MathWorks, Inc.

BLOCK:
Bus Selector;Data Type Conversion;Gain;In;Out;Ramp;Reference;Scope;SubSystem;bus_expanded;bus_nv;bus_v;dscalar_nv;masked;mr_normal;scalar_nv;scalar_v;subsys;to_bus;vec_nv;vec_v

BLOCKTYPE:
BusCreator;BusSelector;DataTypeConversion;Gain;Inport;ModelReference;Mux;Outport;Ramp;RateTransition;Scope;SignalConversion


MODELNAME: ramp_signal_suite_compile_time_views1
BLOCKTYPE_FREQUENCY: 14;6;1;6;4;1;6;1;13;17;3;18
CHECKSUM: C2CA927A2DD8400C13E64CF31511EB77
PRODUCT: Simulink;System Identification Toolbox
PRODUCT_BASECODE: ID
PATH:
toolbox/shared/slcontrollib/signal_injection_plugin/m/showcase/ramp_signal_suite_compile_time_views1.slx

ANNOTATION:
 NUMERIC NONE ADD REPLACE EDIT  VIRTUAL BUS REPLACE ADD NONE EDIT NONE  NON VIRTUAL BUS ADD REPLACE EDIT Copyright 2023 The MathWorks, Inc.

BLOCK:
Bus Creator;Bus Selector;Constant;From Workspace;In;Loop Opening;Out;Scope;Signal Conversion;Signal Copy;SubSystem;Sum;injection blocks;meas;pert;scalar_nv

BLOCKTYPE:
BusCreator;BusSelector;Constant;FromWorkspace;Gain;Inport;LoopOpening;Outport;Scope;SignalConversion;Sum;ToWorkspace


MODELNAME: GenericDesign
PATH: toolbox/shared/supportpackages/rfsoc_shared/app/+rfsocMdlGen/TemplateModel/GenericDesign.slx
BLOCKTYPE: Constant;DataTypeConversion;Inport;Outport;Terminator
BLOCKTYPE_FREQUENCY: 4;7;7;7;4
CHECKSUM: 4D9C5D6C7F0EDB7D155CEFAF6E6C5289
PRODUCT: Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET;HCZYNQ7000
DESCRIPTION:
Generic Design Template model for GenericDesign ADC/DAC inports/outports with master/slave DMA connection

BLOCK:
Constant;HDL_IP;SubSystem;Terminator;axi_mm2s_tdata;axi_mm2s_tdata_dtc;axi_mm2s_tready;axi_mm2s_tready_dtc;axi_mm2s_tvalid;axi_mm2s_tvalid_dtc;axi_s2mm_tdata;axi_s2mm_tdata_dtc;axi_s2mm_tready;axi_s2mm_tvalid;axi_s2mm_tvalid_dtc


MODELNAME: GenericDesign_AX4Master
BLOCKTYPE_FREQUENCY: 2;1;7;5;5;5;14;1;15;16;6;1;2;2;2;8;3;1;2;63;36;2;65;3;6;14;4;2;19;2;5
CHECKSUM: C6F118189284E39504D1D59CBD5B044D
PRODUCT: Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET;HCZYNQ7000
PATH:
toolbox/shared/supportpackages/rfsoc_shared/app/+rfsocMdlGen/TemplateModel/GenericDesign_AX4Master.slx

DESCRIPTION:
GenericDesign_AX4Master Template model for GenericDesign ADC/DAC inports/outports with master/slave DMA connection and AXI4 Master

ANNOTATION:
if pop=true check length axim_wr_m2s - DDR4 Write axim_rd_m2s - DDR4 Read axim_rd_m2s - DDR4 Read axim_wr_m2s - DDR4 Write

BLOCK:
 Demux ; SFunction ; Terminator ; ackIn==;<rd_avalid>;<rd_len>;<wr_addr>;<wr_valid>;AFULL;AckGen;Add;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Constant;DDR;DDR4 Model;Data Type Conversion;Delay;Detect Increase;Display;Enable;From;Goto;HDL FIFO;HDL_IP;Logical Operator;MATLAB Function;MATLAB System;Pop;Pulse Generator;Q;R;RdCmdQueue;Reference;S;Signal Conversion;SubSystem;Switch;Terminator;Unit Delay;ValAddEnb;ValwrLenCnt;Wr_control;ack;ackIn;ackIn Posedge Detect;ackIn_d;ackIn_d1==;ackOut;afull;axiWrLen;axiWrLen!=;axiWrLen-1==cnt & axiWrLen!=0 ;axiWrLen==cnt+;axi_addr;axi_mm2s_tdata;axi_mm2s_tdata_dtc;axi_mm2s_tready;axi_mm2s_tready_dtc;axi_mm2s_tvalid;axi_mm2s_tvalid_dtc;axi_rd_add;axi_rd_data;axi_rd_dready;axi_rd_len;axi_rd_m2s;axi_rd_ready;axi_rd_s2m;axi_rd_s2m ;axi_rd_val;axi_s2mm_tdata;axi_s2mm_tdata_dtc;axi_s2mm_tready;axi_s2mm_tvalid;axi_s2mm_tvalid_dtc;axi_wr_ack;axi_wr_add;axi_wr_data;axi_wr_en;axi_wr_enb;axi_wr_len;axi_wr_length;axi_wr_m2s;axi_wr_s2m;axi_wr_s2m ;axi_wr_val;axim_ack;axim_rd_addr;axim_rd_addr_FIFO;axim_rd_aready;axim_rd_aready_behavior;axim_rd_avalid;axim_rd_avalid_FIFO;axim_rd_data;axim_rd_dvalid;axim_rd_len;axim_rd_len_FIFO;axim_rd_m2s;axim_rd_s2m;axim_wr_data;axim_wr_m2s;axim_wr_s2m;cache_reg;data;data_i;data_o;data_valid;dataaddr_o;datalen_o;ddr_ack_d;ddr_rdy;ddr_ready;ddr_reday_d;ddr_wr_rdy;dtci;edgeDet;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;if cnt < axiWrLen;load_done;load_init_data;num;num_i;num_o;out_reg;pop_ctrl;pop_in;pop_o;push;ram_addr;ram_rd_addr;ram_rd_val;ram_wr_add;ram_wr_addr;ram_wr_data;ram_wr_enb;ram_wr_enb cond;rdDone;rdDonePulse;rdLogic;rd_ack;rd_ack_i;rd_control;rd_done;rd_rdy;rdy_out;sr_latch;tdata;tready;tvalid;valAddEnb;valid_in;wrEnb;wrLogic;wr_ack;wr_addr-;wr_done;wr_done_o;wr_enb;wr_len;wr_leng;wr_queue

BLOCKTYPE:
Bit Concat;Bit Shift;Bit Slice;BusCreator;BusSelector;Compare To Constant;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;DiscretePulseGenerator;Display;EnablePort;From;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MATLABSystem;Outport;RelationalOperator;S-Function;SignalConversion;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: mdl_ref
PATH: toolbox/shared/supportpackages/sdk/testmodels/mdl_ref.slx
BLOCKTYPE: Constant;Delay;Demux;Inport;Math;Outport;Product;Repeating Sequence Stair;S-Function;Sum;Terminator
BLOCKTYPE_FREQUENCY: 1;1;2;2;2;3;1;1;1;3;1
CHECKSUM: 1012439BD3388AB2B6AE9612D3D3475F
PRODUCT: MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: ECCORTEXA;ECCORTEXM;ECCORTEXR;IFX_AURIX_TC4x;INFINEON_AURIX;IFX_AURIX_TC3x;XILINX_BLOCKSET
BLOCK:
 Demux ; SFunction ; Terminator ;Compute SUM error;Constant;Cos;Delay;Demux;In;Math Function;Product;Reference;Repeating Sequence Stair;Sin;SubSystem;Sum;factorial;u;y


MODELNAME: msumdiff
PATH: toolbox/shared/supportpackages/sdk/testmodels/msumdiff.slx
ANNOTATION: Place PIL block here
BLOCKTYPE: DataTypeConversion;Inport;Outport;RandomNumber;Sum;ToWorkspace
BLOCKTYPE_FREQUENCY: 2;2;4;2;6;2
CHECKSUM: 25F0A08598F57D671A671C6E2D7D70D9
PRODUCT: Embedded Coder;MATLAB Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: ECCORTEXA;ECCORTEXM;ECCORTEXR;IFX_AURIX_TC4x;INFINEON_AURIX;IFX_AURIX_TC3x;XILINX_BLOCKSET
BLOCK:
Compute DIFF error;Compute SUM error;Compute_Sum_and_Diff;DIFF;Data Type Conversion;Diff;Random Number;Random Source ;SUM;Signal ;SubSystem;Sum;To Workspace;Vector 


MODELNAME: feedback_control
ANNOTATION: Copyright 2012-2017 The MathWorks, Inc.
BLOCK: Discrete PID Controller;Reference;u;y
BLOCKTYPE: Inport;Outport;PID 1dof
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: 10D0D7F8A76F7B141A4AF474B85ED053
PRODUCT: Embedded Coder;Simulink
PRODUCT_BASECODE: SL
PATH:
toolbox/simulink/project/templates/templatessrc/code_generation_example/controller/feedback_control.slx


MODELNAME: feedback_harness
ANNOTATION: Copyright 2012 The MathWorks, Inc.
BLOCK: Controller;Plant;RT;Reference;Scope;Sum
BLOCKTYPE: Constant;ModelReference;RateTransition;Scope;Sum
BLOCKTYPE_FREQUENCY: 1;2;2;1;1
CHECKSUM: A6CF063C052CF4E744749EED97CE54AB
PRODUCT: Simulink
PRODUCT_BASECODE: SL
EXTERNALFILE_REFERENCE: feedback_control___Model_Block___feedback_plant___Model_Block___
PATH:
toolbox/simulink/project/templates/templatessrc/code_generation_example/harnesses/feedback_harness.slx


MODELNAME: fxpdemo_probe
PATH: toolbox/simulink/sfuntemplates/fxpdemo_probe.slx
BLOCKTYPE: Demux;Display;Inport;Mux;Outport;S-Function
BLOCKTYPE_FREQUENCY: 14;28;16;13;41;15
CHECKSUM: D2BE2C397AB4A5EAC72850A057790138
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Fixed-Point S-Functions: Querying Properties This example shows several ways to use S-functions to probe signal properties. Use this model for simulation only; it does not support code generation.

ANNOTATION:
Fixed-Point S-functions: Querying Properties Double-click the S-function block and click Edit to see the source code Copyright 1990-2009 The MathWorks, Inc.

BLOCK:
Bias;BiasProbe;ContainWordLen;ContainWordLenProbe;Demux;Display;FXP_STORAGE_CHUNKARRAY;FXP_STORAGE_DOUBLE;FXP_STORAGE_INT;FXP_STORAGE_MULTIWORD;FXP_STORAGE_OTHER_SINGLE_WORD;FXP_STORAGE_SCALEDDOUBLE;FXP_STORAGE_SINGLE;FXP_STORAGE_UINT;FXP_STORAGE_UNKNOWN;FixedExponent;FixedExponentProbe;FracLength;FracLengthProbe;FracSlope;FracSlopeProbe;Input;IsFixedPoint;IsFixedPointProbe;IsFloatingPoint;IsFloatingProbe;IsFxpFltApiCompat;IsFxpFltApiCompatProbe;IsScalingPow;IsScalingPow2Probe;IsScalingTrivial;IsScalingTrivialProbe;IsSigned;IsSignedProbe;More Info;Mux;OutputValid;S-Function;StorageContainCatProbe;StorageContainSize;StorageContainSizeProbe;SubSystem;TotalSlopeProbe;TotalSlopeProbe ;WordLength;WordLengthProbe


MODELNAME: fxpdemo_sfun_user_U32BitRegion
PATH: toolbox/simulink/sfuntemplates/fxpdemo_sfun_user_U32BitRegion.slx
ANNOTATION: Fixed-Point S-Function: SetU32BitRegion and GetU32BitRegion Copyright 2007 The MathWorks, Inc.
BLOCKTYPE: DataTypeConversion;Inport;Outport;Repeating Sequence Interpolated;S-Function;Scope;Sum
BLOCKTYPE_FREQUENCY: 16;8;8;8;8;1;8
CHECKSUM: 3BB03564E44048E9FAA35DFA5CDBCCA0
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
FXPMoveU32BitRegion;Gateway Out;Input;Output;Reference;Repeating Sequence Interpolated;S-Function;Scope;SubSystem;Sum


MODELNAME: fxpdemo_sfun_user_asr
PATH: toolbox/simulink/sfuntemplates/fxpdemo_sfun_user_asr.slx
ANNOTATION: Copyright 1990-2005 The MathWorks Inc. Fixed-Point S-Functions: Arithmetic Shift
BLOCKTYPE: DataTypeConversion;Mux;Outport;Repeating Sequence Interpolated;S-Function;Scope;User ASR
BLOCKTYPE_FREQUENCY: 14;7;7;7;7;1;7
CHECKSUM: F6F1AFA4736B4884EE1DF9C6F301C2E3
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Fixed-Point S-Functions: Arithmetic Shift This example shows a custom C language S-function written to perform an arithmetic shift. This operation is available in Simulink(R) with the Shift Arithmetic block, which can be used for comparison with this S-function example. To see the source code for the S-function, use the right-click context menu to select Look under mask. When the dialog box appears, press the Edit button. 

BLOCK:
Gateway Out;More Info;Mux;Out;Reference;Repeating Sequence Interpolated;Scope;SubSystem;User Written Fixed Point Arithmetic Shift Right


MODELNAME: fxpdemo_sfun_user_const
PATH: toolbox/simulink/sfuntemplates/fxpdemo_sfun_user_const.slx
ANNOTATION: Copyright 1990-2005 The MathWorks Inc. Fixed-Point S-Functions: Fixed-Point Source
BLOCKTYPE: DataTypeConversion;Display;Outport;S-Function
BLOCKTYPE_FREQUENCY: 17;17;43;17
CHECKSUM: C373FE203A6CBAB2230BA31F0EBD53D7
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Fixed-Point S-Functions: Fixed-Point Source This example shows a custom C language S-function written to generate a constant value. This operation is available in Simulink(R) with the Constant block, which can be used for comparison with this S-function example. To see the source code for the S-function, use the right-click context menu to select Look Under Mask. When the dialog box appears, press the Edit button. 

BLOCK:
Data Type Override Set to Scaled Doubles for this subsystem;Data Type Override Set to True Doubles;Data Type Override Set to True Singles;Display;Gateway Out;More Info;Out;S-Function;SubSystem;Subsystem


MODELNAME: fxpdemo_sfun_user_const_rtw
PATH: toolbox/simulink/sfuntemplates/fxpdemo_sfun_user_const_rtw.slx
BLOCKTYPE: DataTypeConversion;Display;Outport;S-Function
BLOCKTYPE_FREQUENCY: 14;14;36;14
CHECKSUM: B381848941AFA11E06E786803DF381AA
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
Data Type Override Set to Scaled Doubles for this subsystem;Data Type Override Set to True Doubles;Data Type Override Set to True Singles;Display;Gateway Out;Out;S-Function;SubSystem;Subsystem


MODELNAME: fxpdemo_sfun_user_dtprop
PATH: toolbox/simulink/sfuntemplates/fxpdemo_sfun_user_dtprop.slx
ANNOTATION: Copyright 1990-2005 The MathWorks Inc. Fixed-Point S-Functions: Data Type Propagation
BLOCKTYPE: DataTypeConversion;Mux;Outport;Repeating Sequence Interpolated;S-Function;Scope;Sum
BLOCKTYPE_FREQUENCY: 6;2;2;4;2;2;4
CHECKSUM: 2676521EC8C25BAA0DE947DD2D65E5EF
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Fixed-Point S-Functions: Data Type Propagation This model shows how to propagate fixed-point data types in fixed-point S-Functions. It exercises a custom C language S-function written to enforce data types across multiple signals. This operation is available in Simulink(R) with the Data Type Propagation block, which can be used for comparison with this S-function example. To see the source code for the S-function, use the right-click context menu to select Block Parameters. When the dialog box appears, press the Edit button.

BLOCK:
Add;DTProp Third Input has Data Type Need for Ideal Sum of First Two Inputs;Gateway Out;In;More Info;Mux;Out;Reference;Scope;SubSystem


MODELNAME: fxpdemo_sfun_user_prodsum
PATH: toolbox/simulink/sfuntemplates/fxpdemo_sfun_user_prodsum.slx
ANNOTATION: Copyright 1990-2005 The MathWorks Inc. Fixed-Point S-Functions: Product and Sum
BLOCKTYPE_FREQUENCY: 2;3;2;3;1;2;1;2;2
CHECKSUM: F6C64A77DD9D192FD3BDC6053AAF5A4B
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Fixed-Point S-Functions: Product and Sum This model shows how to exercise a custom C language S-function written to compute a fixed-point product and sum operation. To see the source code for the S-function, use the right-click context menu to select Block Parameters. When the dialog box appears, press the Edit button. 

BLOCK:
Constant;Gateway Out;More Info;Mux;Out;Reference;Repeating Sequence Stair;S-Function;Scope;Signal Specification;SubSystem;Tapped Delay

BLOCKTYPE:
Constant;DataTypeConversion;Mux;Outport;Repeating Sequence Stair;S-Function;Scope;SignalSpecification;Tapped Delay Line


MODELNAME: msfcndemo_fi
PATH: toolbox/simulink/sfuntemplates/msfcndemo_fi.slx
BLOCK: Constant;Elementwise Multiplication of Complex Fixed-Point Data;Out;Real-Imag to Complex;SubSystem
BLOCKTYPE: Constant;M-S-Function;Outport;RealImagToComplex
BLOCKTYPE_FREQUENCY: 4;1;1;2
CHECKSUM: A4CCAFED783B554BC30757F6C2405B0F
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Level-2 MATLAB file S-function Demo: Fixed-Point M S-function Copyright 2008-2013 The MathWorks, Inc.


MODELNAME: msfcndemo_multirate
PATH: toolbox/simulink/sfuntemplates/msfcndemo_multirate.slx
BLOCK: Downsample by ;From Workspace;SubSystem;To Workspace
BLOCKTYPE: FromWorkspace;M-S-Function;ToWorkspace
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: E9AFAD8E0C507493737FC64B966AB9E1
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Level-2 MATLAB file S-function Demo: Multirate MATLAB S-function Copyright 1990-2013 The MathWorks, Inc.


MODELNAME: msfcndemo_varpulse
PATH: toolbox/simulink/sfuntemplates/msfcndemo_varpulse.slx
ANNOTATION: Copyright 2007-2013 The MathWorks, Inc.
BLOCKTYPE: DiscretePulseGenerator;Gain;M-S-Function;Outport;RandomNumber;Saturate;Scope
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1
CHECKSUM: C2F305BE63A8AED497D3CCD412F04D6B
PRODUCT: Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Creates a Variable Pulse Generator by using an S-function to control the pulse width of a Pulse Generator block.

BLOCK:
Gain;Level-2 MATLAB file S-Function that implements a variable pulse generator;Out;Pulse Generator;Random Number;Saturation;SubSystem;Variable Pulse Generator;Variable Pulse Signal


MODELNAME: msfcndemo_varsize
PATH: toolbox/simulink/sfuntemplates/msfcndemo_varsize.slx
ANNOTATION: Copyright 2009-2013 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;1;2;1;2;2;2;4;1;2;1;1
CHECKSUM: F51B351159650A90CAD63649888672C8
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
BLOCK:
Abs;Detect Size Change;Difference;Enable;Enabled subsystem;In;In ;Level-2 MATLAB file S-Function;Logical Operator;Out;Probe;Reference;Select;Selector;SubSystem;Switch

BLOCKTYPE:
Abs;Constant;Difference;DiscretePulseGenerator;EnablePort;Inport;Logic;M-S-Function;Outport;Probe;S-function:msfcn_holdStateUntilReset;Selector;Switch


MODELNAME: msfcndemo_vsfunc
PATH: toolbox/simulink/sfuntemplates/msfcndemo_vsfunc.slx
ANNOTATION: Copyright 2004-2013 The MathWorks, Inc.
BLOCKTYPE: Constant;M-S-Function;Mux;Outport;Scope;Sin;Switch
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;2;1
CHECKSUM: 60BFA2E64C8ADE7EF4DB888937A4834A
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
Constant;Continuous-Time Variable Step by MATLAB file (level 2) S-Function;Mux;Out;Scope;Sine Wave;SubSystem;Switch


MODELNAME: sfbuilder_busArrayUsage
PATH: toolbox/simulink/sfuntemplates/sfbuilder_busArrayUsage.slx
BLOCKTYPE_FREQUENCY: 6;6;1;1;4;2;1;1;1;1;2;2;2
CHECKSUM: 51C0CA40575920B40AF1A285B67947C0
PRODUCT: Embedded Coder;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
This demonstration illustrates how the S-function Builder can be used to generate S-functions using bus array inputs and outputs Copyright 2021 The MathWorks, Inc.

BLOCK:
Bus Selector;In;LIMITBUSCreator;Model Info;More Info;Out;Pulse Generator;Reference;S-Function Builder;S-function Builder;SFB_COUNTERBUSCreator;SIGNALBUSCreator;Scope;Selector;SubSystem;Unit Delay;Vector Concatenate;lower_ saturation_ limit;upper_saturation_limit

BLOCKTYPE:
BusCreator;BusSelector;CMBlock;Concatenate;Constant;DiscretePulseGenerator;Inport;Outport;S-Function;S-Function Builder;Scope;Selector;UnitDelay


MODELNAME: sfbuilder_bususage
PATH: toolbox/simulink/sfuntemplates/sfbuilder_bususage.slx
BLOCKTYPE_FREQUENCY: 5;2;2;2;1;5;3;2;1;2;2;1;1;2;2;1;2;2
CHECKSUM: DB620DC34A701623494012E2A52874F0
PRODUCT: Embedded Coder;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
\leftarrow call the Simulink version \leftarrow call the S-Function Builder version Copyright 2002-2013 The MathWorks, Inc. This demonstration illustrates how the S-function Builder can be used to generate S-functions using bus inputs and outputs

BLOCK:
 input; input GE lower; limit;Add;And;Bus Creator;Bus Selector;Bus to Vector;From;Goto;In;LIMITBUSCreator;Limits;Out;Previous Output;Pulse Generator;S-Function Builder;S-function Builder;SFB_COUNTERBUSCreator;SIGNALBUSCreator;ScopeA;Signal Conversion;SubSystem;Switch;Unit Delay;lower_ saturation_ limit;slCounter;upper GE input;upper_saturation_limit

BLOCKTYPE:
BusCreator;BusSelector;BusToVector;Constant;DiscretePulseGenerator;From;Goto;Inport;Logic;Outport;RelationalOperator;S-Function;S-Function Builder;Scope;SignalConversion;Sum;Switch;UnitDelay


MODELNAME: sfbuilder_euler2dc
PATH: toolbox/simulink/sfuntemplates/sfbuilder_euler2dc.slx
BLOCKTYPE: DataTypeConversion;MinMax;Mux;Reshape;S-Function;S-Function Builder;Scope;Sin;Trigonometry
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;3;1
CHECKSUM: 9BD83CB5106EFC5E5D9B80FD8657BAD7
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
This block determines the 3x3 Direction Cosine Matrix (DCM) from a 3x1 euler orientation. Copyright 2002-2013 The MathWorks, Inc.

BLOCK:
Data Type Conversion;MinMax;Mux;Reshape 3x3->9x;S-Function Builder;Scope;Sine Wave;SubSystem;Trigonometric Function


MODELNAME: sfbuilder_movingAverage
PATH: toolbox/simulink/sfuntemplates/sfbuilder_movingAverage.slx
BLOCK: Random Number;S-Function Builder;Scope;SubSystem
BLOCKTYPE: RandomNumber;S-Function;S-Function Builder;Scope
BLOCKTYPE_FREQUENCY: 1;1;1;1
CHECKSUM: 09F64B681CA63D488B47415AE26E4D97
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
This demonstration illustrates how the S-function Builder can utilize Start and Terminate methods for one-time setup. Copyright 2017 The MathWorks, Inc.


MODELNAME: sfbuilder_nestedBusArrayUsage
PATH: toolbox/simulink/sfuntemplates/sfbuilder_nestedBusArrayUsage.slx
BLOCKTYPE: BusCreator;BusSelector;CMBlock;Concatenate;Constant;Display;S-Function;S-Function Builder;Selector
BLOCKTYPE_FREQUENCY: 5;5;1;2;4;6;1;1;4
CHECKSUM: 9B8378CC03D394D338B1C17D47C16B26
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
 This demonstration illustrates how the S-function Builder can be used to generate S-functions using nested arrays of buses Copyright 2021 The MathWorks, Inc.

BLOCK:
Bus Creator;Bus Selector;Constant;Display;Model Info;More Info;Reference;S-Function Builder;Selector;SubSystem;Vector Concatenate


MODELNAME: sfbuilder_permutation
PATH: toolbox/simulink/sfuntemplates/sfbuilder_permutation.slx
BLOCK: Constant;Random Integer Generator;Reference;S-Function Builder;Scope;SubSystem
BLOCKTYPE: Constant;Random Integer Generator;S-Function;S-Function Builder;Scope
BLOCKTYPE_FREQUENCY: 1;1;1;1;1
CHECKSUM: 199B535F0C194A135F223EB6D27BC7E0
PRODUCT: Communications Toolbox;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Copyright 2018 The MathWorks, Inc. This demonstration illustrates how the S-function Builder can utilize PWorks in allocating memory and creating C++ Class Objects.


MODELNAME: sfbuilder_upsampling
PATH: toolbox/simulink/sfuntemplates/sfbuilder_upsampling.slx
BLOCK: 5X Upsampling;Linear Filtering;Scope;Sine Wave;SubSystem
BLOCKTYPE: RateTransition;S-Function;S-Function Builder;Scope;Sin
BLOCKTYPE_FREQUENCY: 1;1;1;1;1
CHECKSUM: 118395C8BF090F850AD5DF6636FE4CD7
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
 This model demonstrates the upsampling of a sine wave using linear filtering implemented with C++ STL algorithms. The staircase-like sine signal is upsampled 5 times, then filtered with a triangle (linear) kernel to smooth out the edges. As a result, an interpolated curve is produced. To implement linear filtering, a std::deque FIFO container is used to hold the signal window for convolution, its reverse iterator is utilized to represent the flipped signal (time-reversal), which performs std::inner_product() with kernel, and gives the convolution at a single time t. Copyright 2018 The MathWorks, Inc.


MODELNAME: sfcndemo_angle_events
PATH: toolbox/simulink/sfuntemplates/sfcndemo_angle_events.slx
ANNOTATION: Copyright 2016-2017 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;3;1;2;3;1;5;1;1
CHECKSUM: 38D9B6678C8D52A93B398B37E056E569
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
BLOCK:
Constant;Crank Angle Events (EventOutputType: FunctionCall);Crank Angle Events (EventOutputType: TriggerPulse);Scope;SubSystem;Switch;Terminator;Unit Delay;ev;function-call to trigger-pulse;rpm2deg/sec

BLOCKTYPE:
AngularIntegratorWithEventDetection;Constant;Gain;S-Function;Scope;Switch;Terminator;TriggerPort;UnitDelay


MODELNAME: sfcndemo_atmos
PATH: toolbox/simulink/sfuntemplates/sfcndemo_atmos.slx
BLOCKTYPE: CMBlock;Constant;S-Function;Scope;Sin;Sum
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1
CHECKSUM: 63042BFD64A4C07ECE5203BEA4063DF9
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Example of C calling Fortran - Atmospheric Properties This is a simulation-only demonstration of how a Level-2 C-MEX S-function can be used as a wrapper to call Fortran code for simulation purposes. This is documented in the Writing S-functions manual that is part of the SImulink documentation set. This demonstration does *not* provide support for integration of Fortran with Real-Time Workshop code generation. 

ANNOTATION:
Atmosphere Model in Fortran C-MEX Calling Fortran Example (Simulation only - no code generation support in this demo) Copyright 1990-2013 The MathWorks, Inc.

BLOCK:
C-MEX Gateway S-Function to Fortran;Constant;Model Info;More Info;Reference;Scope;Sine Wave;SubSystem;Sum


MODELNAME: sfcndemo_barplot
PATH: toolbox/simulink/sfuntemplates/sfcndemo_barplot.slx
DESCRIPTION: Custom Scope (Signal Viewer) Without Wires C-MEX S-function
BLOCK: Data Type Conversion;Floating Bar Plot;Mux;Reference;Reshape;Sine Wave;Terminator
BLOCKTYPE: DataTypeConversion;Floating Bar Plot;Mux;Reshape;Sin;Terminator
BLOCKTYPE_FREQUENCY: 3;1;2;1;2;5
CHECKSUM: CDC3E3C044B4A9E344F2403C4FA7F526
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Click on signal line to see the signal values displayed in a bar plot. Use shift-click to select and view multiple signals. This block is an example of how to write a C-Mex S-function that can access signals without directly connecting signal wires to its inputs. This is useful for data viewing blocks such as floating scopes and gauges. Copyright 1990-2013 The MathWorks, Inc. 1) Run the model 2) Click on a wire, then another wire


MODELNAME: sfcndemo_csparam
PATH: toolbox/simulink/sfuntemplates/sfcndemo_csparam.slx
DESCRIPTION: Context-Sensitive Parameters in C-MEX S-functions
BLOCK: Constant;Display;Gain;Out;S-Function;SubSystem
BLOCKTYPE: Constant;Display;Gain;Outport;S-Function
BLOCKTYPE_FREQUENCY: 1;2;2;2;2
CHECKSUM: 2FAA459C6446C90EA503FE58B30846AF
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Code generation - Generate code for the model. Through an inspection of the models Simulink Coder file and the generated code you will see that the gain value parameter is tunable. In addition, you will see that - the data type of K1 is real32_T - the data type of K2 is int8_T Inspect sfun_csparam.tlc for details on how to generate code for this S-Function. Simulation - Run the simulation. It should run infinitely. Update the value of K1 to 5 and K2 to int8(7) in the MATLAB workspace and do an Update Diagram. The use of a run-time parameter for the gain value of the S-function allows you to change the value during simulation. Inspect sfun_csparam.cpp for details on: - How to use context-sensitive run-time parameters. - How to register the parameters data type as an alias data type. Context-sensitive Parameter Demo NOTE: - The S-Function that is used in this model acts like a Gain block. It accepts a scalar parameter that is multiplied by the input signal. It sets up its input, output and parameter to all use the same data type. - The constant block is configured to output a signal of data type MYTYPE (MYTYPE is a Simulink.AliasType object in the MATLAB workspace). - K1 is a double (context-sensitive) parameter. As a result, its data type is determined by the blocks that use it. - K2 is an int8 parameter. It is not a context sensitive parameter so its data type is fixed. Blocks may need to cast it to the correct data type before using it. - Alias data types are ignored unless you are generating code with ert.tlc. When using ert.tlc, MYTYPE will be preserved in the generated code. Copyright 1990-2013 The MathWorks, Inc.


MODELNAME: sfcndemo_dtype_io
PATH: toolbox/simulink/sfuntemplates/sfcndemo_dtype_io.slx
DESCRIPTION: Data-Typed I/O Using a C-MEX S-function
BLOCKTYPE: Constant;Display;Ground;S-Function;Scope;SignalSpecification;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 5;1;6;4;1;1;2;1
CHECKSUM: A5A5EC4273C81BBFFBCAADBE6BB82D95
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Simulink calls mdlSetDefaultPortDataTypes of this block. Simulink calls mdlSetOutputPortDataType of this block. Simulink calls mdlSetInputPortDataType of this block. Simulink calls mdlSetInputPortDataType of this block. Copyright 1990-2013 The MathWorks, Inc.

BLOCK:
Bitwise OR;Bitwise XOR;Constant;Display;Ground;S-Function;Scope;Signal Specification;SubSystem;Terminator;Unit Delay


MODELNAME: sfcndemo_dtype_param
PATH: toolbox/simulink/sfuntemplates/sfcndemo_dtype_param.slx
DESCRIPTION: Data-Typed Parameter Handling in C-MEX S-functions
BLOCK: Bitwise AND;Constant;Display;SubSystem
BLOCKTYPE: Constant;Display;S-Function
BLOCKTYPE_FREQUENCY: 3;3;3
CHECKSUM: 5CF8CCF391CAE71AEA1957C39CB18FD2
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Simulink call mdlSetOutputPortDataType of this block. Bitwise AND Copyright 1990-2013 The MathWorks, Inc.


MODELNAME: sfcndemo_frame
PATH: toolbox/simulink/sfuntemplates/sfcndemo_frame.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;2;1;5;6;1;6;1;1;1
CHECKSUM: 1F3E3AC2EDDCF4504F47BA16D3D2CD1D
PRODUCT: Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
(Requires DSP System Toolbox) Frame-Based Processing for Removing Sinusoidal Noise Using C-MEX S-functions

ANNOTATION:
Removing sinusoidal noise from a multi-channel frame-based signal (Requires DSP System Toolbox) Simulation - During simulation, the A/D block produces a two-channel signal (each channel is a sinusoid). Both channels are contaminated with additive sinusoidal noise. The blocks between the A/D and D/A then remove the noise. The noisy and clean signals are displayed on the scope. Code generation - When code is generated for this model, the resulting C file will contain place-holders for the A/D, D/A, DFT, and IDFT blocks. This code is simply meant to illustrate how users can implement actual A/D and D/A blocks through a combination of S-functions and TLC files. Copyright 1990-2013 The MathWorks, Inc.

BLOCK:
A/D Converter;D/A Converter;DFT;IDFT;In;Out;Remove trailing zeros;S-Function;Scope;SubSystem;To Workspace;Unbuffer;Zero out Noise Coefficients in Frequency Domain;clean coef;cons;noisy coef;prod

BLOCKTYPE:
A/D Converter;Constant;D/A Converter;DFT;Frame Unbuffer;IDFT;Inport;Outport;Product;S-Function;Scope;Selector;SignalToWorkspace


MODELNAME: sfcndemo_io_handling
PATH: toolbox/simulink/sfuntemplates/sfcndemo_io_handling.slx
DESCRIPTION: Access Block Input, Output, and Parameter Values in Simulation and Code Generation C-MEX S-function
ANNOTATION: Copyright 1990-2013 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;2;3;1;2;1;1;16;1;1;10;1;2;6;1;4;1;18;4
CHECKSUM: A6F25AFCBEFCC600A2FB403D326FEE3A
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
Bus Creator;Complex I/O;Complex to Magnitude-Angle;Complex to Real-Imag;Constant;Discontiguous I/O;Discrete Pulse Generator;Discrete-Time Integrator;Enable;Gain;Goto;Ground;In;Input Permutations;Integrator;Mux;Out;Parameter File;Real I/O;Requires Contiguous I/O;Sine Wave;SubSystem;Sum;Terminator;w

BLOCKTYPE:
BusCreator;ComplexToMagnitudeAngle;ComplexToRealImag;Constant;DiscreteIntegrator;DiscretePulseGenerator;EnablePort;From;Gain;Goto;Ground;Inport;Integrator;Mux;Outport;Parameter File;S-Function;Sin;Sum;Terminator


MODELNAME: sfcndemo_port_triggered
PATH: toolbox/simulink/sfuntemplates/sfcndemo_port_triggered.slx
ANNOTATION: Copyright 1990-2013 The MathWorks, Inc.
BLOCK: Bus Creator;In;Out;Pulse Generator;S-Function;Scope;Sine Wave;SubSystem;Trigger;Triggered Subsystem
BLOCKTYPE: BusCreator;DiscretePulseGenerator;Inport;Outport;S-Function;Scope;Sin;TriggerPort
BLOCKTYPE_FREQUENCY: 2;1;1;3;2;2;2;1
CHECKSUM: FBCDF50087E7824FD436C7ACBE9D3BE2
PRODUCT: Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
Port-Based Sample Time C-MEX S-function, suitable for use standalone or inside any type of triggered subsystem


MODELNAME: sfcndemo_pulse_delay
PATH: toolbox/simulink/sfuntemplates/sfcndemo_pulse_delay.slx
ANNOTATION: Copyright 2016-2017 The MathWorks, Inc.
BLOCK: Bias;Cast;Reference;SubSystem;Terminator;cmp;delay;pulse_delay;urand [0,1]
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;1;1
CHECKSUM: 9F1D47E6770516CDEF7803F4D3A7BFD9
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
BLOCKTYPE:
Bias;Compare To Constant;DataTypeConversion;PulseDelay;S-Function;Sin;Terminator;UniformRandomNumber


MODELNAME: sfcndemo_runtime
PATH: toolbox/simulink/sfuntemplates/sfcndemo_runtime.slx
DESCRIPTION: Run-Time Parameter C-MEX S-functions with Real-Time Workshop details
BLOCKTYPE: Constant;S-Function;Scope;Sin
BLOCKTYPE_FREQUENCY: 1;4;2;2
CHECKSUM: 299963220FB024D1BBBE41D8D208A0DD
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Run-Time Parameter Demo Simulation - Run the simulation. It should run infinitely. For the first three S-functions, update the value of gainVal and gainVal2 to 2.5 and int8(2.5) respectively in the MATLAB workspace and do an Update Diagram. The use of a run-time parameter for the gain value of the S-function allows you to change the value of gain during simulation. Inspect sfun_runtime1.c, sfun_runtime2.c, and sfun_runtime3.c to see the different ways in which you can register and update run-time parameters. Code generation - Generate code for the model. Through an inspection of the models Simulink Coder file and the generated code you will see that the gain value parameter is tunable. Inspect the mdlRTW functions of the two S-functions. You will notice that there are no statements which explicitly write out the run-time parameters. It happens automatically. Copyright 1990-2013 The MathWorks, Inc. The fourth S-function above demonstrates how to create a run-time parameter as a function of multiple block dialog parameters. It takes force as an input and calculates acceleration using a single run-time parameter for the mass. The mass run-time parameter is calculated from the volume and density S-function parameters, which can be changed in the mask for sfun_runtime4.

BLOCK:
Acceleration;Calculate acceleration based on input force;Constant;Force;S-Function;Scope;Sine Wave;SubSystem


MODELNAME: sfcndemo_sfun_fcncall
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfun_fcncall.slx
DESCRIPTION: Function-call generator C-MEX S-function
ANNOTATION: Copyright 1990-2013 The MathWorks, Inc.
BLOCKTYPE: Constant;Demux;Outport;S-Function;S-function: sfun_fcncall;Scope;Sin;Sum;TriggerPort;UnitDelay
BLOCKTYPE_FREQUENCY: 2;1;4;1;1;1;1;2;2;2
CHECKSUM: 9F040048128345AB7D5BB5675892D0AD
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
Constant;Demux;Function call S-Function;Out;Scope;Sine Wave;SubSystem;Sum;Unit Delay;f;f1 subsys;f2 subsys


MODELNAME: sfcndemo_sfun_localsolver
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfun_localsolver.slx
BLOCK: Integrator;Integrator with Local ODE1 ;Out;Scope;Sine Wave;SubSystem
BLOCKTYPE: Integrator;Outport;S-Function;Scope;Sin
BLOCKTYPE_FREQUENCY: 1;2;1;2;2
CHECKSUM: 6F102E5436F39FA9977BBCA271520C17
PRODUCT: Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
S-function of a Continuous Integrator using Local Solver This model shows how to hide local continuous states from master solver and use local solver to upate them.

ANNOTATION:
 Local Solver Example: S-function of an Integrator using ODE1 as Local Solver  Copyright 2017 The MathWorks, Inc.


MODELNAME: sfcndemo_sfun_multiport
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfun_multiport.slx
DESCRIPTION: Multiple Port Signals C-MEX S-function
ANNOTATION: Copyright 1990-2013 The MathWorks, Inc.
BLOCKTYPE: Demux;Inport;Mux;Outport;S-Function;S-function: sfun_multiport;Scope;Sin
BLOCKTYPE_FREQUENCY: 1;1;2;2;3;3;1;2
CHECKSUM: 0C958C9C3BA2DFDEE375663419C437A7
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
Demux;In;Multiple Port Signals by S-function;Mux;Out;S-Function;Scope;Sine Wave;Sine Wave Vector;SubSystem


MODELNAME: sfcndemo_sfun_multirate
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfun_multirate.slx
DESCRIPTION: Multirate C-MEX S-function
ANNOTATION: Copyright 1990-2013 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;2;2;1;1;7;3
CHECKSUM: 1FF901E4D6E1FDBF6FCA96F073733750
PRODUCT: Simulink
PRODUCT_BASECODE: SL
BLOCK:
Constant;Discrete Pulse Generator;S-Function;Scope;SubSystem;Sum;To Workspace;To Workspce;Unit Delay

BLOCKTYPE:
Constant;DiscretePulseGenerator;S-Function;S-function: sfun_multirate;Scope;Sum;ToWorkspace;UnitDelay


MODELNAME: sfcndemo_sfun_rtwdwork
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfun_rtwdwork.slx
DESCRIPTION: DWork S-function example, including Real-Time Workshop considerations
BLOCK: Constant;Gain;Out;S-Function;SubSystem
BLOCKTYPE: Constant;Gain;Outport;S-Function
BLOCKTYPE_FREQUENCY: 1;1;2;2
CHECKSUM: 0BB5083174A2133D3D4B5199C3E39980
PRODUCT: Embedded Coder;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
dWork is named X with ExportedGlobal storage class and no type qualifier dWork is named Y with ExportedGlobal storage class and type qualifier volatile Copyright 1990-2013 The MathWorks, Inc.


MODELNAME: sfcndemo_sfun_zc_cstate_sat
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfun_zc_cstate_sat.slx
DESCRIPTION: Saturation Using Non-Sampled Zero Crossings C-MEX S-function
BLOCK: Out;Scope;Sine B;SubSystem;Zero Crossing with Continuous States S-Function
BLOCKTYPE: Outport;S-Function;S-function: sfun_zc_cstate_sat;Scope;Sin
BLOCKTYPE_FREQUENCY: 1;1;1;1;1
CHECKSUM: D963E9E1DAEF9F6B42027A41B348A5E7
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
 S-Function for Continuous States and Zero-Crossing Detection Copyright 1990-2017 The MathWorks, Inc.


MODELNAME: sfcndemo_sfunc_zc_pwm
PATH: toolbox/simulink/sfuntemplates/sfcndemo_sfunc_zc_pwm.slx
BLOCKTYPE: Constant;Gain;Inport;Integrator;Outport;S-Function;Scope;Sin;SliderBlock;Sum
BLOCKTYPE_FREQUENCY: 2;7;3;3;5;1;3;1;1;3
CHECKSUM: 2E85666A7299EF31B4C8C8E7646D7754
PRODUCT: Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
 $\omega$  di/dt  $\omega = \dot{\theta}$   $\theta$  PWM Controller  PWM Driven DC Motor model  $\omega$   $\theta$  i

BLOCK:
Add;Constant;Current;Electrical;Electrical constant;Gain;Inductance;Inertia;Input voltage;Integrator;Mechanical;PWM;PWM controler;Position;Resistance;S-Function;Scope;Sine Wave;Speed;SubSystem;Subtract;current;damping: motor viscous friction constant;mechanical constant;v


MODELNAME: sfcndemo_varsize
PATH: toolbox/simulink/sfuntemplates/sfcndemo_varsize.slx
ANNOTATION: Copyright 2009-2013 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;4;1;1;1;4;2;7;1;4;2
CHECKSUM: 9FD2CF114F7F3AEF3C0C4715759F6A56
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
BLOCK:
Abs;Detect Size Change;Difference;Enable;ITVS_ONLY;In;In_;Logical Operator;Out;OutConcat;OutDWorkReset;Probe;Reference;S-function;S-function Accepting Fix Size Signal;S-function Accepting Variable Size Signal;Select_1D;Signal selector;SubSystem

BLOCKTYPE:
Abs;Constant;Difference;DiscretePulseGenerator;EnablePort;Inport;Logic;Outport;Probe;S-Function;Switch


MODELNAME: sfcndemo_varsize_signalwidth
PATH: toolbox/simulink/sfuntemplates/sfcndemo_varsize_signalwidth.slx
ANNOTATION: Copyright 2008 The MathWorks, Inc.
BLOCK: Add;Constant;Out;Probe;S-Function;Sine Wave;SubSystem;Subsystem;Switch
BLOCKTYPE: Constant;Outport;Probe;S-Function;Sin;Sum;Switch
BLOCKTYPE_FREQUENCY: 8;4;2;2;4;2;4
CHECKSUM: CC9ED4274F9CC2C8159951C25082AC35
PRODUCT: Simulink
PRODUCT_BASECODE: SL
DESCRIPTION:
This example shows how to C-mex S-function to create Simulink(R) blocks with variable-size input and output signals. The two S-function blocks call the same S-function slexVardimsGetCurrentPortWidthSFcn. This S-function highlights the functionalities of three macros, ssGetCurrentInputPortWidth, ssSetInputPortDimsSameAsOutputPortDims and ssAddVariableSizeSignalsRuntimeChecker. ssGetCurrentInputPortWidth can be used to get the total widht (total number of elements) of the signal at input port. ssSetInputPortDimsSameAsOutputPortDims set the dimensions of output port to be equal to the dimensions of input port. This method is called from mdlSetWorkWidths. When this function is called, it indicates that the S-function does not set the output port current dimension. ssAddVariableSizeSignalsRuntimeChecker registers a method for checking the input dimensions. It is used in mdlSetWorkWidths. Two types of checks are allowed INPUTS_DIMS_MATCH and INPUTS_DISALLOW_EMPTY_SIGNAL. The input dimensions matching checks that the current dimensions of all the input ports match, otherwise an error is thrown. The empty signal checker verifies that no input signal is empty at runtime, otherwise an error is thrown. In this model, the first one is used. 


MODELNAME: sldemo_msfcn_edge_detect
PATH: toolbox/simulink/sfuntemplates/sldemo_msfcn_edge_detect.slx
BLOCK: Accelerator Simulation;Edge Detector;Load Movie;SubSystem;show_filtered;show_source
BLOCKTYPE: M-S-Function
BLOCKTYPE_FREQUENCY: 4
CHECKSUM: 7EBB59B6C9633AE352FECBC9E657A2DB
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
Level-2 MATLAB file S-function Demo: Image Edge Detection using Sobel Filter   Play Movie Copyright 2004-2013 The MathWorks, Inc.


MODELNAME: sldemo_msfcn_lms
PATH: toolbox/simulink/sfuntemplates/sldemo_msfcn_lms.slx
BLOCK: Gain;LMS Adaptive;Random Number;Scope;SubSystem;Sum;Unknown System
BLOCKTYPE: DiscreteFilter;Gain;M-S-Function;RandomNumber;Scope;Sum
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;2
CHECKSUM: 094EF0D58D4F07465A605C7D262FC2B3
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
ANNOTATION:
  Level-2 MATLAB file S-function Demo: System Identification for an FIR Filter  Copyright 2004-2013 The MathWorks, Inc.


MODELNAME: mSampleTime
BLOCK: Add;Integrator;Model Info;More Info;Out;PortEquation;Reference;Sine Wave;SubSystem
BLOCKTYPE: CMBlock;Integrator;Outport;Sin;Sum
BLOCKTYPE_FREQUENCY: 4;2;2;3;2
CHECKSUM: EFCC6B42AB721BF03A76DE4FC6AB2A89
PRODUCT: Simulink
PRODUCT_BASECODE: SL
PATH:
toolbox/simulink/simulink/sl_structure_analysis/+Simulink/+Structure/+Symbolic/Models/mSampleTime.slx


MODELNAME: mhouseheat
BLOCKTYPE_FREQUENCY: 2;7;1;4;2;5;6;3;6;2;2;2;2;6
CHECKSUM: 755990DEF0DBF148CBB828B4F0F6E4F3
PRODUCT: MATLAB;Simulink
PRODUCT_BASECODE: SL
PATH:
toolbox/simulink/simulink/sl_structure_analysis/+Simulink/+Structure/+Symbolic/Models/mhouseheat.slx

DESCRIPTION:
Thermal Model of a House This demo illustrates how you can use Simulink(R) to create the thermal model of a house. This system models the outdoor environment, the thermal characteristics of the house, and the house heating system. The sldemo_househeat_data.m file initializes data in the model workspace. To make changes, you can edit the model workspace directly or edit the MATLAB(R) file and re-load the model workspace. To view the model workspace, select View > Model Explorer from the Simulink editor. Note: Time is given in units of hours 

ANNOTATION:
$Output \ Equations\\Y_{1} = \mathrm{Mdot}\,U_{1}\,c\,\left(\mathrm{THeater}-U_{2}\right)$ $Output \ Equations\\Y_{1} = X_{2}\,\mathrm{cost}$ $Y_{2} = \frac{9\,X_{1}}{5}+32}$ $Derivative \ Equations\\\dot{X_{1}} =\frac{\frac{\frac{25\,\sin\left(\frac{\pi \,t}{12}\right)}{3}-X_{1}+10}{\mathrm{Req}}+\mathrm{Mdot}\,c\,\Omega _{\mathrm{out}}\left(\frac{190}{9}-X_{1}\right)\,\left(\mathrm{THeater}-X_{1}\right)}{M\,c}$ $\dot{X_{2}} =\mathrm{Mdot}\,c\,\Omega _{\mathrm{out}}\left(\frac{190}{9}-X_{1}\right)\,\left(\mathrm{THeater}-X_{1}\right)}$ $States \ Legend: \\X_{1}:mhouseheat/House/Integrator\\X_{1}(0) =TinIC$ $X_{2}:mhouseheat/Integrator\\X_{2}(0) =0$

BLOCK:
Avg Outdoor Temp;Blower switch;Bus Creator;Celsius to Fahrenheit;Cost Calculator;Daily Temp Variation;Fahrenheit to Celsius;Fahrenheit to Celsius ;Heat Losses;HeatFlow;HeatGain;Heater;Heater Air Temperature;Heater QDot In;Heater Switch;House;Integrator;Mc;Model Info;More Info;OnOff;Out;Outdoor Temp Tout;PlotResults;PortEquation;Reference;Relay;Room Temp Troom;Set Point;SubSystem;Sum;Terr;Thermostat;Troom

BLOCKTYPE:
BusCreator;CMBlock;CelsiusToFahrenheit;Constant;FahrenheitToCelsius;Gain;Inport;Integrator;Outport;Product;Relay;Scope;Sin;Sum


MODELNAME: ex_imagetypes
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/ex_imagetypes.slx
ANNOTATION: ? Copyright 2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 3;2;1;2;2;4;2;2;2;2;3
CHECKSUM: 14352FCA98F372FA19BB124F0B767166
PRODUCT_BASECODE: SM_OPENCV
BLOCK:
 Demux ; SFunction ; Terminator ;I;Image To Matrix;MatrixToImage_coins;MatrixToImage_peppers;Out_highContrast;Out_normal;Reference;Sine Wave;SubSystem;Switch;Video Viewer High Contrast;Video Viewer Original;coins;contrast_histeq;out;peppers_bw

BLOCKTYPE:
Constant;Demux;Image To Matrix Converter Block;Inport;Matrix To Image Converter Block;Outport;S-Function;Sin;Switch;Terminator;VideoViewer

PRODUCT:
Computer Vision Toolbox;Computer Vision Toolbox Interface for OpenCV in Simulink;Image Processing Toolbox;MATLAB;Simulink


MODELNAME: Cartoonizer
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/Cartoonizer/Cartoonizer.slx
ANNOTATION: Video Cartoonizer Mask Radius Threshold Ramp Size Copyright 2020 - 2021 The MathWorks, Inc.
BLOCKTYPE: Constant;DisplayBlock;From Multimedia File;SliderBlock;VideoViewer
BLOCKTYPE_FREQUENCY: 4;4;1;4;2
CHECKSUM: E4240B6643988007942A30C58C491D11
PRODUCT_BASECODE: SM_OPENCV
BLOCK:
Display;From Multimedia File;More Info;Reference;Slider;SubSystem;Video Viewer;maskRadius;ramp;threshold

PRODUCT:
Computer Vision Toolbox;Computer Vision Toolbox Interface for OpenCV in Simulink;Embedded Coder;MATLAB;Simulink


MODELNAME: DrawAtom
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawAtom.slx
BLOCK: Empty white image;More Info;Size;SubSystem;Video Viewer
BLOCKTYPE: Constant;VideoViewer
BLOCKTYPE_FREQUENCY: 3;2
CHECKSUM: 5829CDA72353F0DB2B24CFCC08826C69
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
In this model we pass an empty sqaure image and draw an atom on it.  Copyright 2019-2021 The MathWorks, Inc. Draw Atom Model

PRODUCT:
Computer Vision Toolbox;Computer Vision Toolbox Interface for OpenCV in Simulink;Embedded Coder;MATLAB;Simulink


MODELNAME: DrawAtomCcaller
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawAtomCcaller.slx
BLOCKTYPE_FREQUENCY: 3;13;1;5;2;4;5;2
CHECKSUM: D366A561E8BAFC99A8640EAE16B6F6C7
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
Add the generated slwrap_drawEllipse CCaller block at the four blank positions above. Center, axes size and color input remains same for all ellipses. Each successive CCaller block draws ellipse on the output of the previous CCaller block.  Copyright 2019-2020 The MathWorks, Inc. Add slwrap_drawFilledCircle CCaller block at the blank position above. Copyright 2019-2021 The MathWorks, Inc. Draw Atom with CCaller Model

BLOCK:
Bus Creator;Color;Constant;Empty white image;FromOpenCV;ImagewithEllipses;InputImage;More Info;Radius;Red;Reference;SubSystem;Terminator;ToOpenCV;Video Viewer;Yellow;angle;axes;center;drawEllipses

BLOCKTYPE:
BusCreator;Constant;FromOpenCV Converter Block;Inport;Outport;Terminator;ToOpenCV Converter Block;VideoViewer

PRODUCT:
Computer Vision Toolbox;Computer Vision Toolbox Interface for OpenCV in Simulink;Embedded Coder;MATLAB;Simulink


MODELNAME: DrawEllipse
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawEllipse.slx
BLOCK: Angle;Bus Creator;Constant;Image From File;More Info;Reference;SubSystem;Video Viewer
BLOCKTYPE: BusCreator;Constant;Image From File;VideoViewer
BLOCKTYPE_FREQUENCY: 3;7;1;2
CHECKSUM: B56DCF838B29649C3F614148FDF9F9D3
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
Takes an Image and two points, an angle and a RGB color as input. Draws an ellipse with centre (x1,y1), and RGB scalar color mentioned on the image. Copyright 2019-2021 The MathWorks, Inc. Draw Ellipse Model


MODELNAME: DrawFilledCircle
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawFilledCircle.slx
BLOCK: Bus Creator;Color;Constant;Image From File;More Info;Radius;Reference;SubSystem;Video Viewer
BLOCKTYPE: BusCreator;Constant;Image From File;VideoViewer
BLOCKTYPE_FREQUENCY: 2;5;1;2
CHECKSUM: 4DABB7C5C1A3DF4A6343DB6C6A61908D
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
 Takes an Image, point coordinate, a RGB color, and the radius as scalar input. Output is the same image with a circle drawn with centre (x1,y1) with the RGB scalar color mentioned  Copyright 2019-2021 The MathWorks, Inc. Draw Filled Circle Model


MODELNAME: DrawLine
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawLine.slx
BLOCK: Bus Creator;Color;Constant;Image From File;More Info;Reference;SubSystem;Video Viewer
BLOCKTYPE: BusCreator;Constant;Image From File;VideoViewer
BLOCKTYPE_FREQUENCY: 3;6;1;2
CHECKSUM: 2FFF3AEA48979DCCADE48A8659AAE42B
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
 Takes an Image, two point coordinates and a RGB color as input. Output is the same image with a line drawn from (x1,y1) to (x2,y2) with the RGB scalar color mentioned.  Copyright 2019-2021 The MathWorks, Inc. Draw Line Model


MODELNAME: DrawPolygon
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawPolygon.slx
BLOCKTYPE: BusCreator;Concatenate;Constant;Image From File;Outport;VideoViewer
BLOCKTYPE_FREQUENCY: 6;2;12;1;2;2
CHECKSUM: 4A7729D93686EE19FA50EC501111431B
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
 Takes an image and vector of points and line color as input Output is the same image with a polygon drawn with the RGB scalar color mentioned  Copyright 2019-2021 The MathWorks, Inc. Draw Polygon Model

BLOCK:
Bus Creator;Color;Constant;Image From File;More Info;Out;Point coordinates;Reference;SubSystem;Vector Concatenate;Video Viewer


MODELNAME: DrawRook
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/DrawShapes/DrawRook.slx
BLOCK: Empty white image;More Info;Size;SubSystem;Video Viewer
BLOCKTYPE: Constant;VideoViewer
BLOCKTYPE_FREQUENCY: 3;2
CHECKSUM: D90F0808B5A7DDE8759D8D46F58B721A
PRODUCT_BASECODE: SM_OPENCV
ANNOTATION:
In this model we pass an empty sqaure image and draw an rook on it  Copyright 2019-2021 The MathWorks, Inc. Draw Rook Model


MODELNAME: smileDetect
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/SmileDetector/smileDetect.slx
ANNOTATION: Copyright 2019-2021 The MathWorks, Inc. Smile Detection Model
BLOCKTYPE_FREQUENCY: 2;1;1;6;2;2;2;3
CHECKSUM: 5A56C9EFC6B2E7384408CC0DE28949C9
PRODUCT_BASECODE: SM_OPENCV
BLOCK:
 Demux ; SFunction ; Terminator ;Detected Face;From Multimedia File;Image To Matrix;MATLAB Function;More Info;Reference;Smiley Replacement ;SubSystem;faceDetectedImage;faceDetectedImage ;intensity;radius;x;y

BLOCKTYPE:
Demux;From Multimedia File;Image To Matrix Converter Block;Inport;Outport;S-Function;Terminator;VideoViewer


MODELNAME: smileDetect_codegen
PATH: toolbox/simulink/supportpackages/simulinkopencv/example/SmileDetector/smileDetect_codegen.slx
ANNOTATION: Copyright 2019-2021 The MathWorks, Inc. Smile Detection Code Generation Model
BLOCKTYPE_FREQUENCY: 2;4;1;11;4;2;2;2
CHECKSUM: AFD48B83F947D24AFC19DC686AA4275A
PRODUCT_BASECODE: SM_OPENCV
BLOCK:
 Demux ; SFunction ; Terminator ;Image From Workspace;Image To Matrix;In;MATLAB Function;More Info;Out;Reference;SubSystem;ToOpenCV;emoji;fdimage;fdimage ;intensity;radius;x;y

BLOCKTYPE:
Demux;Image From Workspace;Image To Matrix Converter Block;Inport;Outport;S-Function;Terminator;ToOpenCV Converter Block


MODELNAME: smileDetect_codegen_CCaller
ANNOTATION: Copyright 2019-2021 The MathWorks, Inc. Smile Detection Model
BLOCKTYPE_FREQUENCY: 2;1;4;11;4;2;2;1
CHECKSUM: B4A6590E621BD0D4C9EBAA05CB882A8D
PRODUCT_BASECODE: SM_OPENCV
PATH:
toolbox/simulink/supportpackages/simulinkopencv/example/SmileDetector/smileDetect_codegen_CCaller.slx

BLOCK:
 Demux ; SFunction ; Terminator ;FromOpenCV;Image From Workspace;In;MATLAB Function;More Info;Out;Reference;SubSystem;ToOpenCV;emoji;fdimage;fdimage ;intensity;radius;x;y

BLOCKTYPE:
Demux;FromOpenCV Converter Block;Image From Workspace;Inport;Outport;S-Function;Terminator;ToOpenCV Converter Block


MODELNAME: VehiclePedestrianDetector
ANNOTATION: Vehicle and Pedestrian Detector Copyright 2020 - 2021 The MathWorks, Inc.
BLOCK: From Multimedia File;More Info;Reference;SubSystem;Video Viewer
BLOCKTYPE: From Multimedia File;VideoViewer
BLOCKTYPE_FREQUENCY: 1;2
CHECKSUM: D90AFE13CDC4F1FAD8A40F4C5E900519
PRODUCT_BASECODE: SM_OPENCV
PATH:
toolbox/simulink/supportpackages/simulinkopencv/example/Vehicle_Pedestrian_Detector/VehiclePedestrianDetector.slx


MODELNAME: dasPanelDemo
PATH: toolbox/simulink/webblocks/webmanager-js/dasPanelDemo/dasPanelDemo.slx
BLOCKTYPE: CallbackButton;Constant;EditField;PanelWebBlock;StringConstant;Terminator;ToggleSwitchBlock
BLOCKTYPE_FREQUENCY: 4;9;5;2;6;13;5
CHECKSUM: 50DE09158EC5C26354B67699FBC3C999
PRODUCT: Simulink
PRODUCT_BASECODE: SL;SF
BLOCK:
Background Color;Body;Border Color;Callback Button;FixedAspectRatio;Height;LabelsOrUrl;LabelsOrUrlSwitch;Left;Moveable;Options;Resizable;SubSystem;Terminator;Title;Toggle Switch;Top;URL;Width;panelInfo;untitledPanel


MODELNAME: suspn3dof
PATH: toolbox/simulinkcompiler/examples/AppGeneration/suspn3dof.slx
ANNOTATION: Road-Suspension Interaction in 3 DOFs Copyright 2011-2018 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 5;7;28;26;25;23;5;6;2;13;3;1;20;2;4
CHECKSUM: 8B1ED6C59308B90B377F487E97F2BE07
PRODUCT: Simulink;Simulink Compiler
PRODUCT_BASECODE: SK
DESCRIPTION:
Automotive Suspension This demo describes a simplified car suspension model in three degrees of freedom (DoF): pitch, yaw and vertical displacement. The demo provides a description of the model to show how simulation can be used for investigating ride characteristics. The Signal Editor block was used to capture different road profiles to test the suspension against.

BLOCK:
Add;Body Dynamics;Body States;Body states;Demux;Divide;From;Front Left Suspension;Front Right Suspension;Fz;Goto;Gravity;InertiaX;InertiaY;Left tire;Left tire ;Mass;Moment arm;MomentArm;Mux;PHI;PHIdot;Pitch (THETA) dynamics;Pitch angle;Pitch rate;Rear Left Suspension;Rear Right Suspension;Right tire;Road Input;Road-Suspension Interaction;Roll (PHI) dynamics;Roll angle;Roll rate;Scope;States;Static Ext.;Static ext.;Static extension;SubSystem;Sum;Sum of Pitch moments;Sum of Roll moments;Sum of susp forces;Susp Forces;THETA;THETAdot;Transport Delay;Vertical (Z) dynamics;Vertical Force;Vertical disp;Vertical vel;Z;Zdot;acceleration due to gravity;damping;stiffness

BLOCKTYPE:
Constant;Demux;From;Gain;Goto;Inport;InportShadow;Integrator;Mux;Outport;Product;Scope;Sum;TransportDelay;half-car suspension


MODELNAME: MassSpringDamperModelWithDiscInput
PATH: toolbox/simulinkcompiler/examples/MassSpringDamperWithLiveIO/MassSpringDamperModelWithDiscInput.slx
DESCRIPTION: The van der Pol Equation This is a simulation of a nonlinear second order system.
BLOCKTYPE: Constant;Gain;Inport;Outport;SecondOrderIntegrator;Sum
BLOCKTYPE_FREQUENCY: 1;3;1;2;1;1
CHECKSUM: 9CA122CFDAE55451EA8C88B2CBB58EC6
PRODUCT: Simulink;Simulink Compiler
PRODUCT_BASECODE: SK
BLOCK:
Damping;External Force;Initial Position;Integrator, Second-Order;Mass;Position;Stiffness;Sum;Velocity


MODELNAME: RoadSuspensionInteractionIn3DOF
PATH: toolbox/simulinkcompiler/examples/Sk_OperatingPointDemo/RoadSuspensionInteractionIn3DOF.slx
ANNOTATION: Road-Suspension Interaction in 3 DOF
BLOCKTYPE_FREQUENCY: 2;2;5;7;28;26;25;21;5;6;14;3;20;2;4
CHECKSUM: 3CF9FF6589DE8B81A2DAFA827A3F9AD5
PRODUCT: Simulink;Simulink Compiler
PRODUCT_BASECODE: SK
DESCRIPTION:
Automotive Suspension This demo describes a simplified car suspension model in three degrees of freedom (DoF): pitch, yaw and vertical displacement. The demo provides a description of the model to show how simulation can be used for investigating ride characteristics. The Signal Editor block was used to capture different road profiles to test the suspension against.

BLOCK:
Add;Body Dynamics;Body States;Bus Creator;Bus Selector;Demux;Divide;From;Front Left Suspension;Front Right Suspension;Fz;Goto;InertiaX;InertiaY;Left Tire ;Left tire;Left tire ;Mass;Moment arm;MomentArm;Phi;PhiDot;PhiDotIntg;PhiIntg;Pitch (Theta) Dynamics;Rear Left Suspension;Rear Right Suspension;Right Tire;Right tire;Road Input;Road-Suspension Interaction;Roll Dynamics;States;Static Ext.;Static ext.;Static extension;SubSystem;Sum;Sum of Pitch moments;Sum of Roll moments;Sum of susp forces;Suspension Forces;Theta;ThetaDot;ThetaDotIntg;ThetaIntg;Transport Delay;Vertical (Z) Dynamics;Vertical Force;Z;ZDot;ZDotIntg;ZIntg;acceleration due to gravity;damping;out;stiffness

BLOCKTYPE:
BusCreator;BusSelector;Constant;Demux;From;Gain;Goto;Inport;InportShadow;Integrator;Outport;Product;Sum;TransportDelay;half-car suspension


MODELNAME: msf_car_under_mlroot
PATH: toolbox/slcheck/slmetrics/test/msf_car_under_mlroot.slx
BLOCKTYPE_FREQUENCY: 4;2;6;1;18;2;5;1;1;15;6;4;2;1;1;3;3;1;1;1
CHECKSUM: 60D16A3E8DC4B36D9695EB7B466E4348
PRODUCT: MATLAB;Simulink;Simulink Check;Stateflow
PRODUCT_BASECODE: VV
ANNOTATION:
Vehicle TORQUE CONVERTER gear Double-click to open the GUI and select an input maneuver  Copyright 1997-2014 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; Merge ; SFunction ; Terminator ;Engine;Integrator;K factor;Look-Up;Look-Up Table;Mux;Ne;Nin;Nout;Product;Reference;Sign;SubSystem;Sum;Ti;Tin;Torque Converter;Torque ratio;Tout;Tt;User Inputs;Vehicle;brake torque;down_th;engine + impeller inertia;engine RPM;engine torque;f;final drive ratio;gear;gear_state;impeller;interp_down;interp_up;linear speed;mph;out;quotient;road load;selection_state.calc_th;shift_logic;signed load;speed;speed ratio;throttle;transmission;transmission output speed;transmission output torque;transmission ratio;turbine;up_th;vehicle inertia;vehicle mph (yellow) & throttle %;vehicle speed;wheel speed

BLOCKTYPE:
Demux;Fcn;Gain;Ground;Inport;Integrator;Lookup_n-D;Merge;Mux;Outport;Product;S-Function;Scope;SignalEditor;Signum;Sum;Terminator;TriggerPort;torque converter;vehicle model


MODELNAME: sldrt_connectedio
PATH: toolbox/sldrt/sldrt/templates/sldrt_connectedio.slx
BLOCKTYPE_FREQUENCY: 2;5;2;3;1;1;1;3
CHECKSUM: C4F3F374C495C7D1003E2BCBA9F56EB2
PRODUCT: Simulink;Simulink Desktop Real-Time
PRODUCT_BASECODE: WT
ANNOTATION:
Simulink Desktop Real-Time Connected lO Mode  Tips for maximum performance: Both fixed-step and variable-step solvers can be used in Connected IO mode. All I/O blocks perform real-time synchronizaton. Use the Real-Time Synchronization block only if no I/O block is used. Use a single block that reads or writes all channels of given type, rather than multiple blocks for one channel each.

BLOCK:
Algorithm;Analog Input;Analog Output;Demux;In;Mux;Out;Real-Time Synchronization;Reference;SubSystem;Terminator

BLOCKTYPE:
Demux;Inport;Mux;Outport;Simulink Desktop Real-Time Analog Input;Simulink Desktop Real-Time Analog Output;Simulink Desktop Real-Time Synchronization;Terminator


MODELNAME: sldrt_runinkernel
PATH: toolbox/sldrt/sldrt/templates/sldrt_runinkernel.slx
BLOCK: Algorithm;Analog Input;Analog Output;Demux;In;Mux;Out;Reference;SubSystem;Terminator
BLOCKTYPE_FREQUENCY: 2;5;2;3;1;1;3
CHECKSUM: D6B60C91C0C6E61E4E572FB5D9BBA9DC
PRODUCT: Simulink;Simulink Desktop Real-Time
PRODUCT_BASECODE: WT
ANNOTATION:
 Tips for maximum performance: It is not necessary to use the Real-Time Synchronization block in Run in Kernel mode. The block performs no operation. It is not useful to use the Missed Ticks port in Run in Kernel mode. The port always outputs zero. Use a single block that reads or writes all channels of given type, rather than multiple blocks for one channel each. Simulink Desktop Real-Time Run in Kernel Mode

BLOCKTYPE:
Demux;Inport;Mux;Outport;Simulink Desktop Real-Time Analog Input;Simulink Desktop Real-Time Analog Output;Terminator


MODELNAME: slrt_ex_ethercatPositionControl
PATH: toolbox/slrealtime/examples/slrt_ex_ethercatPositionControl.slx
BLOCKTYPE_FREQUENCY: 2;1;1;1;1;3;2;1;1;1;3;1
CHECKSUM: 586FC21D3E401B10E3C6D4B031E565FF
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Get an amplitude from the slider Read the current position for display Send the new target position Send Mode of operation Send control word Copyright 2020 The MathWorks, Inc.  ?

BLOCK:
Constant;DC timing error;Data Type Conversion;Display;EtherCAT Init ;EtherCAT PDO Receive;EtherCAT PDO Transmit ;Gain;Mux;Reference;Scope;Sine Wave;Slider;State

BLOCKTYPE:
Constant;DataTypeConversion;Display;Gain;Mux;Scope;Selector;Sin;SliderBlock;ethercat_pdo_receive;ethercat_pdo_send;ethercatinit


MODELNAME: slrt_ex_ethercatVelocityControl
PATH: toolbox/slrealtime/examples/slrt_ex_ethercatVelocityControl.slx
BLOCKTYPE_FREQUENCY: 2;1;2;1;1;4;2;1;1;3;3;1
CHECKSUM: E4965F08384523629FBB1758A4D7A8DE
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Set mode of operation to velocity control Set control word to enabled Get an amplitude from the slider Copyright 2020-2022 The MathWorks, Inc.  ?

BLOCK:
Constant;DC timing error;Data Type Conversion;Display;EtherCAT Init ;EtherCAT PDO Receive;EtherCAT PDO Transmit ;Gain;Mux;Reference;Scope;Sine Wave;Slider;State

BLOCKTYPE:
Constant;DataTypeConversion;Display;Gain;Mux;Scope;Selector;Sin;SliderBlock;ethercat_pdo_receive;ethercat_pdo_send;ethercatinit


MODELNAME: slrt_ex_ethercat_asyncCoE_cycle
PATH: toolbox/slrealtime/examples/slrt_ex_ethercat_asyncCoE_cycle.slx
BLOCKTYPE_FREQUENCY: 6;5;13;1;1;3;1;5;5;8;1;4;7;1;1;1;1;2;1;4;1;1;1
CHECKSUM: 182218F3C5FCC338A0F3A51CB1F8DDC0
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Cycle through SDOrequests in a specific order set to go to PreOp (==2) state  Copyright 2020-2022 The MathWorks, Inc.  ?

BLOCK:
 Demux ; SFunction ; Terminator ;Bitwise Operator;Constant;Cycle control;Data;Data Type Conversion;Display;Enable;Error Codes;EtherCAT Async SDO Download;EtherCAT Async SDO Upload;EtherCAT Get State ;EtherCAT Init;EtherCAT PDO Transmit;EtherCAT Set State ;Go to Op;In;Mux;Number of SDO to do;Op State Model;Out;Pulse Generator;Reference;SDO commands in order;Scope;Selector;Status;Stop Simulation if an error occurred in any of the SDO commands;SubSystem;Trigger;Unit Delay;Wait for this state before SDOs execute;curstate;done;error;nsdo;oprequest;status;trigs;waitstate

BLOCKTYPE:
Bitwise Operator;Constant;DataTypeConversion;Demux;DiscretePulseGenerator;Display;EnablePort;Inport;Mux;Outport;S-Function;Scope;Selector;Stop;Terminator;TriggerPort;UnitDelay;ethercat_pdo_send;ethercatasyncsdodownload;ethercatasyncsdoupload;ethercatgetstate;ethercatinit;ethercatsetstate


MODELNAME: slrt_ex_ethercat_asyncSoE_SSC_InOrder
PATH: toolbox/slrealtime/examples/slrt_ex_ethercat_asyncSoE_SSC_InOrder.slx
BLOCKTYPE_FREQUENCY: 5;7;16;2;4;1;5;10;11;1;6;4;1;1;2;1;1;1;3;2;2;3;1;1;1;1
CHECKSUM: F442861BC6588789B2BBC2262A5B9227
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
set to go to PreOp (==2) state   Cycle through SSCrequests in a specific order Copyright 2020-2022 The MathWorks, Inc.  ?

BLOCK:
 Demux ; SFunction ; Terminator ;Bitwise Operator;Byte Unpacking ;Constant;Cycle control;Data;Data Type Conversion;Demux;Display;Enable;Enabled Subsystem;Error;EtherCAT Async SSC/SoE Download;EtherCAT Async SSC/SoE Upload;EtherCAT Get State ;EtherCAT Init;EtherCAT PDO Receive;EtherCAT PDO Transmit ;EtherCAT Set State ;Go to Op;HW Decode;HW Version;In;Mux;Null term;Number of SSC to do;Out;Reference;Scope;Selector;Sine Wave;SoE commands in order;Status;Stop Simulation if an error occurred in any of the SoE commands;SubSystem;Terminator;Trigger;Unit Delay;V2 Ascii Decode ;Wait for this state before SSCs execute;curstate;done;error;nsoe;oprequest;status;trigs;waitstate

BLOCKTYPE:
Bitwise Operator;Constant;DataTypeConversion;Demux;Display;EnablePort;Inport;Mux;Outport;S-Function;Scope;Selector;Sin;Stop;Terminator;TriggerPort;UnitDelay;asciidecode2;ethercat_pdo_receive;ethercat_pdo_send;ethercatasyncsoedownload;ethercatasyncsoeupload;ethercatgetstate;ethercatinit;ethercatsetstate;slreraltimebytepacking


MODELNAME: slrt_ex_ethercat_beckhoff_aio
PATH: toolbox/slrealtime/examples/slrt_ex_ethercat_beckhoff_aio.slx
ANNOTATION: Copyright 2020-2022 The MathWorks, Inc. ?
BLOCKTYPE: DataTypeConversion;Mux;Scope;Sin;ethercat_pdo_receive;ethercat_pdo_send;ethercatinit
BLOCKTYPE_FREQUENCY: 2;2;3;2;2;2;1
CHECKSUM: BD3727B1FDDCA12CD655650D3268A71F
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Data Type Conversion;EtherCAT Init;EtherCAT PDO Receive;EtherCAT PDO Transmit;Mux;Reference;Scope;Sine Wave


MODELNAME: slrt_ex_ethercat_beckhoff_dio
PATH: toolbox/slrealtime/examples/slrt_ex_ethercat_beckhoff_dio.slx
ANNOTATION: Copyright 2020-2022 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 2;5;1;1;2;3;2;2;1
CHECKSUM: 31DDFFF193296D79157B3D13C15174AB
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Bias;Data Type Conversion;EtherCAT Init ;EtherCAT PDO Receive;EtherCAT PDO Transmit ;Logical Operator;Mux;Pulse Generator;Reference;Scope

BLOCKTYPE:
Bias;DataTypeConversion;DiscretePulseGenerator;Logic;Mux;Scope;ethercat_pdo_receive;ethercat_pdo_send;ethercatinit


MODELNAME: slrt_ex_ethercat_notifyreset
PATH: toolbox/slrealtime/examples/slrt_ex_ethercat_notifyreset.slx
ANNOTATION: Display offsets Copyright 2020-2022 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 10;1;1;3;2;12;1;3;1;3;1;1;1;1
CHECKSUM: C5987E96EBD2340FD796AA671A01C15C
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
 Demux ; SFunction ; Terminator ;Bias;Enable;EtherCAT Get Notifications ;EtherCAT Get State ;EtherCAT Init ;EtherCAT Set State ;Mux;NewState;PrevState;Reference;Reset State Machine;Scope;Selector;SubSystem;Switch to Op State;Terminator;allop;dcinsync;fresp;linkstat;newstate;sbdone;scanbus;slaveError;state;statechg;stateebl;u;wkc

BLOCKTYPE:
Bias;Demux;EnablePort;Inport;Mux;Outport;S-Function;Scope;Selector;Terminator;ethercatgetnotify;ethercatgetstate;ethercatinit;ethercatsetstate


MODELNAME: slrt_ex_ethernetSendReceive
PATH: toolbox/slrealtime/examples/slrt_ex_ethernetSendReceive.slx
BLOCKTYPE_FREQUENCY: 10;4;1;9;1;9;1;8;2;2;2
CHECKSUM: 0B8CA5249FA5E7D71C04C2DC8F422F95
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
 Subsystem to tag with VLAN 32   System obj to tag with VLAN 24, 25, 26 Copyright 2021-2022 The MathWorks, Inc.  ?

BLOCK:
Add;Add VLAN tag;Assign ;Assign 13:;Assign 17:;Assign 27:;Assign 31:;Assign 35:;Assign 37:;Assign 41:;Assign 7:;Constant;Enable;Ethernet Receive;Ethernet Send;In;MATLAB System Object ;Out;Queue;Reference;Selector ;Selector 13:;Selector 1:;Selector 27:;Selector 31:;Selector 35:;Selector 37:;Selector 7:;SubSystem;Subsystem ;clear checksum;increment dst port;switch src dst IP address;switch src dst MAC address;switch src dst port

BLOCKTYPE:
Assignment;Constant;EnablePort;Inport;MATLABSystem;Outport;Queue;Selector;Sum;slrealtime.EthernetReceive;slrealtime.EthernetSend


MODELNAME: slrt_ex_helloworld_sfunbuilder
PATH: toolbox/slrealtime/examples/slrt_ex_helloworld_sfunbuilder.slx
BLOCK: Digital Clock;Display;S-Function Builder
BLOCKTYPE: DigitalClock;Display;S-Function;S-Function Builder
BLOCKTYPE_FREQUENCY: 1;1;1;1
CHECKSUM: E09CFB446DCE1CA51CF8DE697C176938
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Model slrt_ex_helloworld_sfunbuilder Simulink Real-Time example model Copyright 2021-2022 The MathWorks, Inc.   ?


MODELNAME: slrt_ex_lamp_instrument
PATH: toolbox/slrealtime/examples/slrt_ex_lamp_instrument.slx
BLOCK: Constant;Digital Clock;Math Function;Mux;Signal Copy;Terminator;Uniform Random Number
BLOCKTYPE: Constant;DigitalClock;Math;Mux;SignalConversion;Terminator;UniformRandomNumber
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;2;3
CHECKSUM: 4BAF218FC373521ECA960C8764A0140F
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Model slrt_ex_lamp_instrument Simulink Real-Time example model Copyright 2021-2022 The MathWorks, Inc.   ?


MODELNAME: slrt_ex_mds_and_tasks
PATH: toolbox/slrealtime/examples/slrt_ex_mds_and_tasks.slx
BLOCK: Model;Terminator
BLOCKTYPE: ModelReference;Terminator
BLOCKTYPE_FREQUENCY: 2;6
CHECKSUM: 09D44CEB340593A03F7E718C04E7C331
PRODUCT: MATLAB;Simulink;Simulink Real-Time
EXTERNALFILE_REFERENCE: slrt_ex_mds_subsystem1.slx___Model_Block___slrt_ex_mds_subsystem2.slx___Model_Block___
ANNOTATION:
Concurrent Execution on Simulink Real-Time Illustrated by Profiling Tool Copyright 2020-2021 The MathWorks, Inc.  ?


MODELNAME: slrt_ex_non_mds_and_tasks
PATH: toolbox/slrealtime/examples/slrt_ex_non_mds_and_tasks.slx
BLOCK: Model;Terminator
BLOCKTYPE: ModelReference;Terminator
BLOCKTYPE_FREQUENCY: 2;6
CHECKSUM: B06FD60C2156DC552FF6E4F4FC097351
PRODUCT: MATLAB;Simulink;Simulink Real-Time
EXTERNALFILE_REFERENCE: slrt_ex_non_mds_subsystem1.slx___Model_Block___slrt_ex_non_mds_subsystem2.slx___Model_Block___
ANNOTATION:
Concurrent Execution on Simulink Real-Time Illustrated by Profiling Tool Copyright 2020 The MathWorks, Inc.  ?


MODELNAME: slrt_ex_osc_cal
PATH: toolbox/slrealtime/examples/slrt_ex_osc_cal.slx
BLOCKTYPE_FREQUENCY: 4;5;6;2;2;3;1;5;3;3;1;3;1;3
CHECKSUM: D08974B7F4F7C2251C585281B6EC0BBE
PRODUCT: MATLAB;Simulink;Simulink Real-Time;Simulink Test
ANNOTATION:
Model slrt_ex_osc_cal Simulink Real-Time example model Copyright 1999-2020 The MathWorks, Inc.   ? This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;2-D Lookup Table;Demux;Gain;In_;Int;Integrator;Mux;Out_;Outport;Output Conversion Subsystem;Scope;SigGen;SigSpec_;Signal Generator;SubSystem;Sum;Test Assessment;ex_slrt_slt_osc;xpcosc

BLOCKTYPE:
Demux;Gain;Inport;Integrator;Lookup_n-D;ModelReference;Mux;Outport;S-Function;Scope;SignalGenerator;SignalSpecification;Sum;Terminator


MODELNAME: slrt_ex_osc_inlined
PATH: toolbox/slrealtime/examples/slrt_ex_osc_inlined.slx
BLOCK: Gain;Integrator;Mux;Scope;Signal Generator;Sum
BLOCKTYPE: Gain;Integrator;Mux;Scope;SignalGenerator;Sum
BLOCKTYPE_FREQUENCY: 3;2;1;1;1;1
CHECKSUM: 3082F12FB08A00DC7543A86C93056C05
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Model ex_slrt_inline_osc Simulink Real-Time example model ready for inlined parameter tuning Copyright 1999-2013 The MathWorks, Inc.   ?


MODELNAME: slrt_ex_osc_sltest
PATH: toolbox/slrealtime/examples/slrt_ex_osc_sltest.slx
BLOCKTYPE_FREQUENCY: 4;1;5;6;2;3;1;6;3;1;1;3;1;3;1;1
CHECKSUM: 68B4952FF9D095EE817034714A8467C3
PRODUCT: MATLAB;Simulink;Simulink Real-Time;Simulink Test
ANNOTATION:
Copyright 2020 The MathWorks, Inc.  ? This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure. This subsystem has been inserted by Simulink to adapt the output of the harnessed component to the interface required by the sink blocks. Modifying the contents of this subsystem may result in compilation and simulation failure.

BLOCK:
 Demux ; SFunction ; Terminator ;Demux;File Log;Gain;In_;Inport_;Int;Integrator;Mux;Out_;Out_From_;Outport;Outport_;Output Conversion Subsystem;Reference;Scope;SigGen;SigSpec_;Signal Generator;SubSystem;Sum;Test Assessment;Test Assessment Block;Zero-Order Hold;slrt_ex_osc_sltest;xpcosc

BLOCKTYPE:
Demux;From;Gain;Inport;Integrator;ModelReference;Mux;Outport;S-Function;Scope;SignalGenerator;SignalSpecification;Sum;Terminator;ZeroOrderHold;slrealtimeloggingblock


MODELNAME: slrt_ex_overload
PATH: toolbox/slrealtime/examples/slrt_ex_overload.slx
ANNOTATION: Model slrt_ex_overload Simulink Real-Time example model Copyright 2020-2022 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 1;2;2;1;1;1;1;1;2;1;1;1;1;1;1
CHECKSUM: 12CCA0F11A1A42FBE11B391A9F992A4B
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Busy-wait Subsystem;C Function;Chirp Signal;Constant;Data Type Conversion;Ground;Hit Crossing;Overload Options;Random Number;Rate Limiter;Reference;SubSystem;Sum;Switch;TID;Terminator;Unit Delay;Zero-Order Hold

BLOCKTYPE:
CFunction;Constant;DataTypeConversion;Ground;HitCross;Outport;RandomNumber;RateLimiter;Sum;Switch;Terminator;UnitDelay;ZeroOrderHold;chirp;slrtOverloadOptions


MODELNAME: slrt_ex_pendulum_100Hz
PATH: toolbox/slrealtime/examples/slrt_ex_pendulum_100Hz.slx
BLOCKTYPE_FREQUENCY: 5;5;1;1;2;3;5;1;1;3;3;1;1;1;3;3
CHECKSUM: 0A3D4AB66E31EFF427E269F8F04A72A8
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Inverted Pendulum with Animation This example shows how to model an inverted pendulum. The animation is created using MATLAB(R) Handle Graphics(R). The animation block is a masked S-function. For more information, use the context menu to look under the Animation blocks mask and open the S-function for editing.

ANNOTATION:
 Model slrt_ex_pendulum_100Hz Simulink Real-Time example model Copyright 2019-2021 The MathWorks, Inc.  ?

BLOCK:
Add;Cart;Constant Ref;Dis. State-space;Discrete State Estimator;Discrete Transfer Fcn;Discrete-Time Integrator;DiscreteTime Integrator;Fcn;Gain;Integral Gain;Multiport Switch;Mux;NudgeFlag;Nudgehit;Off;Pendulum;Proportional Gain;Rate Transition;Saturation;Sawtooth Wave;Sine Wave;Square Wave;SubSystem;Sum;U;Wave Control;X;theta

BLOCKTYPE:
Constant;DiscreteIntegrator;DiscreteStateSpace;DiscreteTransferFcn;Fcn;Gain;Inport;Inverted pendulum on cart;MultiPortSwitch;Mux;Outport;Pendulum Discrete state estimator;RateTransition;Saturate;SignalGenerator;Sum


MODELNAME: slrt_ex_pendulum_100Hz_dds
PATH: toolbox/slrealtime/examples/slrt_ex_pendulum_100Hz_dds.slx
BLOCKTYPE_FREQUENCY: 1;1;5;1;1;5;1;1;2;3;5;1;1;3;3;1;1;1;1;1;1;3;3
CHECKSUM: 429D487243C088E58E5A0A155C152AE8
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Inverted Pendulum with Animation This example shows how to model an inverted pendulum. The animation is created using MATLAB(R) Handle Graphics(R). The animation block is a masked S-function. For more information, use the context menu to look under the Animation blocks mask and open the S-function for editing.

ANNOTATION:
 Model slrt_ex_pendulum_100Hz_dds Simulink Real-Time example model Copyright 2022 The MathWorks, Inc.  ?

BLOCK:
Add;Bus Creator;Bus Selector;Cart;Constant Ref;DDS Receive;DDS Send;Dis. State-space;Discrete State Estimator;Discrete Transfer Fcn;Discrete-Time Integrator;DiscreteTime Integrator;Fcn;Gain;Integral Gain;Message Receive;Message Send;Multiport Switch;Mux;NudgeFlag;Nudgehit;Off;Pendulum;Proportional Gain;Rate Transition;Reference;Saturation;Sawtooth Wave;Scope;Sine Wave;Square Wave;SubSystem;Sum;U;Wave Control;X;theta

BLOCKTYPE:
BusCreator;BusSelector;Constant;DDS Receive;DDS Send;DiscreteIntegrator;DiscreteStateSpace;DiscreteTransferFcn;Fcn;Gain;Inport;Inverted pendulum on cart;MultiPortSwitch;Mux;Outport;Pendulum Discrete state estimator;RateTransition;Receive;Saturate;Scope;Send;SignalGenerator;Sum


MODELNAME: slrt_ex_pmsm
PATH: toolbox/slrealtime/examples/slrt_ex_pmsm.slx
BLOCKTYPE_FREQUENCY: 1;3;4;23;6;44;32;2;15;3;1;19;110;39;83;20;168;29;1;31;1;6;9;10;103;1;1;38;30;6;1;1;1;50;17;8;1;1;24
CHECKSUM: 383F5FD30493E6AF82A9F95C6DCF00B7
PRODUCT: MATLAB;Simulink;Simulink Real-Time;Stateflow
ANNOTATION:
Fault Enable Calculate State Based on Switch Control - FPGA Clock Rate Output Voltages Based on Switch State - FPGA Model Rate Subcycle Averaging - FPGA Model Rate Short Between Rails Connected to Negative Rail Connected to Positive Rail Open Circuit Subcycle Averaging - FPGA Clock Rate permanently short device if both devices turned on Fault Enable Calculate State Based on Switch Control - FPGA Clock Rate Output Voltages Based on Switch State - FPGA Model Rate Subcycle Averaging - FPGA Model Rate Short Between Rails Connected to Negative Rail Connected to Positive Rail Open Circuit Subcycle Averaging - FPGA Clock Rate permanently short device if both devices turned on Fault Enable Calculate State Based on Switch Control - FPGA Clock Rate Output Voltages Based on Switch State - FPGA Model Rate Subcycle Averaging - FPGA Model Rate Short Between Rails Connected to Negative Rail Connected to Positive Rail Open Circuit Subcycle Averaging - FPGA Clock Rate permanently short device if both devices turned on Decode Fault Word Override External Signals Electrical Equations Mechanical Equations Model slrt_ex_pmsm Simulink Real-Time example model Copyright 1999-2021 The MathWorks, Inc.   ?

BLOCK:
 Demux ; SFunction ; Terminator ;+;-;A+;A+ Close;A+ Fault;A+ Open;A-;A- Close;A- Fault;A- Open;ABC;ALeadsB;AND;Abs;Add;Alpha;Alpha_Gain;Angular Position;Angular Speed;B+;B+ Close;B+ Fault;B+ Open;B-;B- Close;B- Fault;B- Open;Beta;Beta_Gain;Bit Shift;Bitwise Operator;C+;C+ Close;C+ Fault;C+ Open;C-;C- Close;C- Fault;C- Open;Carrier;Chart;Clarke Transform;Clarke to Park Angle Transform;Compare To Constant;Compare To Zero;Config;Configurations;Constant;Cos;Count;CountPerRevolution;Counter;D;DAC_Ia;DAC_Ib;DAC_Ic;DAC_reset;DUT_frequ;DUT_frequency;Data Type Conversion;Delay;Demux;Discrete-Time Integrator;Divide;Electromagnetic torque;Enable;Enc_A;Enc_B;Enc_Count;Enc_Z;Encoder;Encoder_Config;Extract Bits;Fault;Fault_En;Fault_Word;From;G;Gain;Gate mode;GateMode;Gates;Goto;HDL Counter;Half-Bridge SCA Math A;Half-Bridge SCA Math B;Half-Bridge SCA Math C;I;I_DC;I_Phase;I_abc;Ia;Ib;Ic;In;Incorporate Fault Signals;Inertia;Inport;Inverse Clarke Transform;Inverse Park Transform;Inverter SCA Simulink Implementation;Iout;Lambda_pm;Latch;Ld;Logical Operator;Lq;Max;Minus;Mod;ModWave;Motor and Inverter HDL Wrapper;Motor and Inverter Mathmatical Models;Motor shaft initial position;Moving Window Average (SCA HDL);Multiply;Mux;NOT;NPP;Negative Rail Switch Characteristics;Null_DAC_trigger;Number of pole pairs;Number of slits;OR;Open Circuit;Out;PCIe_DAC_reset;PCIe_Encoder_Config;PCIe_Fault_Word;PCIe_I_DC;PCIe_Ia;PCIe_Iabc_bias;PCIe_Iabc_gain;PCIe_Ib;PCIe_Ic;PCIe_Motor_Config;PCIe_PWM_DutyCycle;PCIe_PWM_Enable;PCIe_PWM_Period;PCIe_RC_or_TTL;PCIe_V_minus;PCIe_V_plus;PCIe_thMotor;PCIe_trq/spd_Flag;PCIe_trq/spd_external;PCIe_trqMotor;PCIe_wMotor;PMSM Configuration;PWM Generator;PWM Period;Park Transform;Park to Clarke Angle Transform;Permanent Magnet Synchronous Motor;Permanent magnet flux linkage;Positive Rail Switch Characteristics;Product;Q;Rate Transition;Reference;Relational Operator;S+;S-;Scope;Selector;Short Between Rails Characteristics;Sig_frequ;SiganlFrequency;Sin;Sine_Cosine;Spd/Trq Input;Stator d-axis inductance;Stator q-axis inductance;Stator resistance per phase;SubSystem;Subsystem;Subtract;Sum;Switch;TTL_DAC_trigger;TTL_Enc_A;TTL_Enc_B;TTL_Enc_Count;TTL_Enc_Z;TTL_S;Te/Spd_mech;Terminator;TorqueInFlag;TriggerResetValue;Triggering;Unit Delay;Unit Delay Enabled Synchronous;V;V_minus;V_plus;VaVb;Vabc;Vin;Vll_abc;Vll_calculate_A;Vll_calculate_B;Vll_calculate_C;Vneg;Vout;Vph_abc;Vpos;Wrapped State DTI;ZOffset;a;b;bias;config;constant;convert;count;dq;gain;iabc;period;slotTheta;sp/trq_external;thMotor;theta;torque_in_flag;trigger;trq;trqMotor;trq_elec_Motor;twopi;u;vs_LL;w;wMotor;y

BLOCKTYPE:
Abs;Bit Shift;Bitwise Operator;Compare To Constant;Compare To Zero;Constant;DataTypeConversion;Delay;Demux;DiscreteIntegrator;Encoder;Extract Bits;From;Gain;Goto;HDL Counter;Inport;InportShadow;Inverter SCA Simulink Implementation;Logic;Math;MinMax;Moving Window Average (SCA HDL);Mux;Outport;PMSMConfig;Permanent Magnet Synchronous Motor;Product;RateTransition;RelationalOperator;S-Function;Scope;Selector;Sum;Switch;Terminator;Trigonometry;Unit Delay Enabled Synchronous;UnitDelay


MODELNAME: slrt_ex_pmsm_gm
PATH: toolbox/slrealtime/examples/slrt_ex_pmsm_gm.slx
BLOCKTYPE_FREQUENCY: 28;15;1;9;22;2;25;1;2;5;1;5;1;1;12;1;1;1;7;14
CHECKSUM: E16DB9F4520F8567285A1587D0A98A8F
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Generated by HDL Workflow Advisor on 11-Jan-2022 11:11:22 Model slrt_ex_pmsm Simulink Real-Time example model Copyright 1999-2021 The MathWorks, Inc.  Generated by HDL Workflow Advisor on 11-Jan-2022 11:11:22  ?

BLOCK:
ALeadsB;Add;Constant;DAC_Ia;DAC_Ib;DAC_Ic;DAC_reset;DUT_frequ;DUT_frequency;Data Type Conversion;DataTypeConversion;Demux;Divide;Gate mode;Ground;IO334 DAC Setup;IO3xx Setup;Ia;Ib;Ic;Inertia;Motor and Inverter HDL Wrapper;Motor shaft initial position;Mux;Null_DAC_trigger;Number of pole pairs;Number of slits;PCIRead_PCIe_I_DC;PCIRead_PCIe_Ia;PCIRead_PCIe_Ib;PCIRead_PCIe_Ic;PCIRead_PCIe_thMotor;PCIRead_PCIe_trqMotor;PCIRead_PCIe_wMotor;PCIWrite_PCIe_DAC_reset;PCIWrite_PCIe_Encoder_Config;PCIWrite_PCIe_Fault_Word;PCIWrite_PCIe_Iabc_bias;PCIWrite_PCIe_Iabc_gain;PCIWrite_PCIe_Motor_Config;PCIWrite_PCIe_PWM_DutyCycle;PCIWrite_PCIe_PWM_Enable;PCIWrite_PCIe_PWM_Period;PCIWrite_PCIe_RC_or_TTL;PCIWrite_PCIe_V_minus;PCIWrite_PCIe_V_plus;PCIWrite_PCIe_trq/spd_Flag;PCIWrite_PCIe_trq/spd_external;PCIe_DAC_reset;PCIe_Encoder_Config;PCIe_Fault_Word;PCIe_I_DC;PCIe_Ia;PCIe_Iabc_bias;PCIe_Iabc_gain;PCIe_Ib;PCIe_Ic;PCIe_Motor_Config;PCIe_PWM_DutyCycle;PCIe_PWM_Enable;PCIe_PWM_Period;PCIe_RC_or_TTL;PCIe_V_minus;PCIe_V_plus;PCIe_thMotor;PCIe_trq/spd_Flag;PCIe_trq/spd_external;PCIe_trqMotor;PCIe_wMotor;PMSM Configuration;Permanent magnet flux linkage;Port Settings -2x;Product;Rate Transition;Reference;Scope;Sig_frequ;SiganlFrequency;Stator d-axis inductance;Stator q-axis inductance;Stator resistance per phase;SubSystem;Subsystem;TTL_DAC_trigger;TTL_Enc_A;TTL_Enc_B;TTL_Enc_Count;TTL_Enc_Z;TTL_S;Terminator;ZOffset;bias;constant;dtc;gain;sSpec;theta;trq;w

BLOCKTYPE:
Constant;DataTypeConversion;Demux;Ground;Inport;Mux;Outport;PMSMConfig;Product;RateTransition;Scope;SignalSpecification;Speedgoat IO334-325k Interface Block;Sum;Terminator;io334_dac_setup;io3xx-21;io3xx_fpga_board_setup;io3xx_read;io3xx_write


MODELNAME: slrt_ex_ptp_offset_time_receiver
PATH: toolbox/slrealtime/examples/slrt_ex_ptp_offset_time_receiver.slx
BLOCK: IEEE 1588 Read Parameter;Output;Reference
BLOCKTYPE: IEEE_1588_read_param;Outport
BLOCKTYPE_FREQUENCY: 1;1
CHECKSUM: DD8036AF83BC9D07A115EE558DD72DF1
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
 ? <!DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.0//EN http://www.w3.org/TR/REC-html40/strict.dtd> <html><head><meta name=qrichtext content=1 /><style type=text/css> p, li { white-space: pre-wrap; } </style></head><body align=center style= font-family:Helvetica; font-size:10px; font-weight:400; font-style:normal;> <p align=center style= margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;><span style= font-size:14px;>Model slrt_ex_ptp_offset_time_receiver</span></p> <p align=center style= margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;><span style= font-size:14px;>Simulink Real-Time example model</span></p> <p align=center style=-qt-paragraph-type:empty; margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px; font-size:14px;><br /></p> <p align=center style= margin-top:0px; margin-bottom:0px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-indent:0px;><span style= font-size:14px;>Copyright 2022 The MathWorks, Inc.


MODELNAME: slrt_ex_serialasciisplit
PATH: toolbox/slrealtime/examples/slrt_ex_serialasciisplit.slx
ANNOTATION: Copyright 2004-2019 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 1;2;1;2;1;1;2;1;1;1
CHECKSUM: A8FBFD86778E204AAA0B320D7842E02B
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
ASCII Encoding/Decoding Resync Loopback Test This model shows the ability of the FIFO Read HDRS block to resynchronize after being repeatedly disabled as well as the ability to resolve errors such as when a message is only partially complete at the time the read is attempted. The Switch block alternates between the first and last parts of the message on successive sample times. This mimics a worst case scenario where the model updates before the message construction is complete. As a result, sometimes only part of the message is received. The second pulse generator alternately enables and disables the FIFO Read HDRS block. Scope 1 graphs the decoded sine wave data received at each time step. When the Pulse Generator1 block outputs a |0|, the count from the FIFO Read HDRS block is |0|. When it outputs a |1|, the read catches up by throwing away extra data and returns the last complete value found in the FIFO. Scope 2 indicates when new data is present. 

BLOCK:
ASCII Decode ;ASCII Encode ;Demux;FIFO ASCII read ;FIFO write ;Pulse Generator;Reference;Scope;Sine Wave;Switch;Terminator

BLOCKTYPE:
ASCII Decode;ASCII Encode;Demux;DiscretePulseGenerator;FIFO Block: reader;FIFO Block: writer;Scope;Sin;Switch;Terminator


MODELNAME: slrt_ex_serialasciitest
PATH: toolbox/slrealtime/examples/slrt_ex_serialasciitest.slx
ANNOTATION: Copyright 2004-2019 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 3;1;1;1;1;1;1;2
CHECKSUM: F3FF61A0F93EDCA6FB20E2DC342CCE22
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
ASCII Encoding/Decoding Loopback Test This model shows how to send ASCII data over a serial link. The ASCII Encode block generates a message with three different sub messages along with some extraneous junk to show how the FIFO Read HDRS block can remain synchronized to the valid byte stream even in the presence of transmission errors. The FIFO Read HDRS block can handle an arbitrary number of headers; just add them as strings to the cell array in the block parameters dialog box. The messages must share the same termination string. In this example, it is a carriage return followed by a line feed: |\r\n|. 

BLOCK:
ASCII Decode ;ASCII Encode ;FIFO ASCII read ;FIFO write ;Mux;Pulse Generator;Reference;Scope;Sine Wave

BLOCKTYPE:
ASCII Decode;ASCII Encode;DiscretePulseGenerator;FIFO Block: reader;FIFO Block: writer;Mux;Scope;Sin


MODELNAME: slrt_ex_serialbaseboardasciisplit
PATH: toolbox/slrealtime/examples/slrt_ex_serialbaseboardasciisplit.slx
ANNOTATION: Copyright 2004-2020 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 1;2;1;2;1;1;2;2;1;1;2
CHECKSUM: E6AFBF56BCB241263E6CE7427DE29D2C
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
ASCII Encoding/Decoding Resync Loopback Test (With Baseboard Blocks) This model shows the ability of the FIFO Read HDRS block to resynchronize after being repeatedly disabled as well as the ability to resolve errors such as when a message is only partially complete at the time the read is attempted. The Switch block alternates between the first and last parts of the message on successive sample times. This mimics a worst case scenario where the model updates before the message construction is complete. As a result, sometimes only part of the message is received. The second pulse generator alternately enables and disables the FIFO Read HDRS block. Scope 1 graphs the decoded sine wave data received at each time step. When the Pulse Generator1 block outputs a |0|, the count from the FIFO Read HDRS block is |0|. When it outputs a |1|, the read catches up by throwing away extra data and returns the last complete value found in the FIFO. Scope 2 indicates when new data is present. To test this model: # The target computer must have two COM ports. # Connect COM1 to COM2 with a null modem cable. This example is configured to use baseboard serial ports (COM1 and COM2). You can also use COM3 and COM4 by changing the board setup in the Baseboard blocks. Other serial blocks could be used in place of the Baseboard blocks. For instance, a single Quatech(R) 4-port block could be used whereby you send on port 1 and receive on port 2. 

BLOCK:
ASCII Decode ;ASCII Encode ;Demux;FIFO ASCII read ;Ground;Legacy Serial F;Pulse Generator;Reference;Scope ASCII Decode;Scope FIFO Read HDRS;Sine Wave;Switch;Terminator

BLOCKTYPE:
ASCII Decode;ASCII Encode;Demux;DiscretePulseGenerator;FIFO Block: reader;Ground;Scope;Serial F;Sin;Switch;Terminator


MODELNAME: slrt_ex_serialbaseboardasciitest
PATH: toolbox/slrealtime/examples/slrt_ex_serialbaseboardasciitest.slx
ANNOTATION: Copyright 2004-2019 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 3;1;1;1;1;1;1;2;2;1
CHECKSUM: FF64533C053ECACBC2666B40E2C475AD
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
ASCII Encoding/Decoding Loopback Test (With Baseboard Blocks) This model shows how to send ASCII data over a serial link. The ASCII Encode block generates a message with three different sub messages along with some extraneous junk to show how the FIFO Read HDRS block can remain synchronized to the valid byte stream even in the presence of transmission errors. The FIFO Read HDRS block can handle an arbitrary number of headers; just add them as strings to the cell array in the block parameters dialog box. The messages must share the same termination string. In this example, it is a carriage return followed by a line feed: |\r\n|. To test this model: # The target computer must have two COM ports. # Connect COM1 to COM2 with a null modem cable. This example is configured to use baseboard serial ports (COM1 and COM2). You can also use COM3 and COM4 by changing the board setup in the Baseboard blocks. Other serial blocks could be used in place of the Baseboard blocks. For instance, a single Quatech(R) 4-port block could be used whereby you send on port 1 and receive on port 2. 

BLOCK:
ASCII Decode ;ASCII Encode ;FIFO ASCII read ;Ground;Legacy Serial F;Mux;Pulse Generator;Reference;Scope ASCII Decode;Sine Wave;Terminator

BLOCKTYPE:
ASCII Decode;ASCII Encode;DiscretePulseGenerator;FIFO Block: reader;Ground;Mux;Scope;Serial F;Sin;Terminator


MODELNAME: slrt_ex_serialbaseboardbinarysplit
PATH: toolbox/slrealtime/examples/slrt_ex_serialbaseboardbinarysplit.slx
BLOCKTYPE_FREQUENCY: 7;3;2;2;1;1;1;2;1;2;2;1;3
CHECKSUM: 1BD087B86FB06E2BD1F7F33F4232AA44
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Binary Encoding/Decoding Resync Loopback Test (With Baseboard Blocks) This model shows the ability of the FIFO Read BINARY block to handle messages that are interrupted and only partially complete. This is a worst case example where every message is interrupted. The Segmented Message Constructor subsystem contains blocks that prepare and send only parts of messages on each time step. On the receive side, the FIFO read BINARY block is looking for two different two-character headers. If it finds |[170,1]| it outputs |[3,170,1,N]| on port 1. If it finds |[170,2]|, it outputs |[4,170,2,44,M]| to port 2. |N| and |M| are numbers between |0| and |255| that are incrementing and decrementing, respectively. If a message header is not found in the FIFO on a given time step, then that port will output |0|. The outputs are padded to the maximum vector size specified in the FIFO Read BINARY block. In this example output vectors are |1024| in width. The count in the first element tells how many elements are significant. The Demux blocks discard the uninteresting parts of the signal. Scope 1 displays the received message 1 data. Scope 2 displays the received message 2 data. To test this model: # The target computer must have two COM ports. # Connect COM1 to COM2 with a null modem cable. This example is configured to use baseboard serial ports (COM1 and COM2). You can also use COM3 and COM4 by changing the board setup in the Baseboard blocks. Other serial blocks could be used in place of the Baseboard blocks. For instance, a single Quatech(R) 4-port block could be used whereby you send on port 1 and receive on port 2. 

ANNOTATION:
This subsystem produces an interrupted byte stream emulating a condition that could occur in real applications. The top counter increments from 0:3 and then repeats. This selects a different input on each iteration. None of the selections are a complete message that the FIFO Read BINARY block is looking for. The sequence produced by this subsystem is: step: output 0: [3 5 170 1] 1: [1 inc cnt 0 0] 2: [3 170 2 44] 3: [1 dec cnt 0 0] repeat Copyright 2004-2019 The MathWorks, Inc.  ?

BLOCK:
Add;Constant;Count;Counter Limited;Data Type Conversion;Demux;FIFO bin read ;Ground;Legacy Serial F;Multiport Switch;Mux;Out;Reference;Scope FIFO Read BINARY ;Segmented Message Construction;SubSystem;Terminator

BLOCKTYPE:
Constant;Counter Limited;DataTypeConversion;Demux;FIFO Block: reader;Ground;MultiPortSwitch;Mux;Outport;Scope;Serial F;Sum;Terminator


MODELNAME: slrt_ex_serialbaseboardbinarytest
PATH: toolbox/slrealtime/examples/slrt_ex_serialbaseboardbinarytest.slx
ANNOTATION: Copyright 2004-2019 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 3;2;2;2;1;1;1;1;1;2;2;1;3
CHECKSUM: EDA92A56F83F3C06D5CD794BDCFBCEDC
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Binary Encoding/Decoding Loopback Test (With Baseboard Blocks) This model shows how to send Binary data over a serial link. The transmitted data are: |[8,5,170,1,N,170,2,44,M]|. This byte stream contains two messages along with other elements as defined below. * The first byte, |8|, is a count of the remaining number of bytes in the stream. * The second byte, |5|, is an extraneous value (EV). * |[170,1,N]| is message 1 (M1). * |[170,2,44,M]| is message 2 (M2). * |N| and |M| are numbers between |0| and |255| that are incremenenting and decrementing, respectively. Notice that when the data contains extraneous bytes (|5| in this case) the FIFO Read BINARY block can handle and ignore this extra information. Scope 1 displays the received message 1 data. Scope 2 displays the received message 2 data. Scope 3 shows the transmitted byte stream. The gain block on the signal to Scope 3 makes the elements of the vector non-virtual so the scope can see them. To test this model: # The target computer must have two COM ports. # Connect COM1 to COM2 with a null modem cable. This example is configured to use baseboard serial ports (COM1 and COM2). You can also use COM3 and COM4 by changing the board setup in the Baseboard blocks. Other serial blocks could be used in place of the Baseboard blocks. For instance, a single Quatech(R) 4-port block could be used whereby you send on port 1 and receive on port 2. 

BLOCK:
Add;Constant;Constructed Message;Counter Limited;Data Type Conversion;Demux;FIFO bin read ;Ground;Legacy Serial F;Message Construction;Mux;Out;Reference;Scope FIFO Read BINARY ;SubSystem;Terminator

BLOCKTYPE:
Constant;Counter Limited;DataTypeConversion;Demux;Display;FIFO Block: reader;Ground;Mux;Outport;Scope;Serial F;Sum;Terminator


MODELNAME: slrt_ex_serialbaseboardsimpleascii
PATH: toolbox/slrealtime/examples/slrt_ex_serialbaseboardsimpleascii.slx
ANNOTATION: Copyright 2004-2020 The MathWorks, Inc. ?
BLOCKTYPE: ASCII Decode;ASCII Encode;FIFO Block: reader;Ground;Scope;Serial F;Sin;Terminator
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;2;1;1
CHECKSUM: 56F041882D9822FA9D07C866B32CBB0E
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Simple ASCII Encoding/Decoding Loopback Test (With Baseboard Blocks) This simple model shows how a single floating point number can be converted to ASCII and transmitted over a serial link. The sending serial port and receiving serial port can be in the same system or in different systems. To test this model: # The target computer must have two COM ports. # Connect COM1 to COM2 with a null modem cable. This example is configured to use baseboard serial ports (COM1 and COM2). You can also use COM3 and COM4 by changing the board setup in the Baseboard blocks. Other serial blocks could be used in place of the Baseboard blocks. For instance, a single Quatech(R) 4-port block could be used whereby you send on port 1 and receive on port 2. 

BLOCK:
ASCII Decode ;ASCII Encode ;Baseboard Serial F;FIFO read ;Ground;Reference;Scope ASCII Decode;Sine Wave;Terminator


MODELNAME: slrt_ex_serialbinarysplit
PATH: toolbox/slrealtime/examples/slrt_ex_serialbinarysplit.slx
BLOCKTYPE_FREQUENCY: 7;3;2;2;1;1;1;2;1;2;1
CHECKSUM: 5F59B282C902CA007D077C5408BB198C
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Binary Encoding/Decoding Resync Loopback Test This model shows the ability of the FIFO Read BINARY block to handle messages that are interrupted and only partially complete. This is a worst case example where every message is interrupted. The Segmented Message Constructor subsystem contains blocks that prepare and send only parts of messages on each time step. On the receive side, the FIFO read BINARY block is looking for two different two-character headers. If it finds |[170,1]| it outputs |[3,170,1,N]| on port 1. If it finds |[170,2]|, it outputs |[4,170,2,44,M]| to port 2. |N| and |M| are numbers between |0| and |255| that are incremenenting and decrementing, respectively. If a message header is not found in the FIFO on a given time step, then that port will output |0|. The outputs are padded to the maximum vector size specified in the FIFO Read BINARY block. In this example output vectors are |6| in width. The count in the first element tells how many elements are significant. Scope 1 displays the received message 1 data. Scope 2 displays the received message 2 data. 

ANNOTATION:
This subsystem produces an interrupted byte stream emulating a condition that could occur in real applications. The top counter increments from 0:3 and then repeats. This selects a different input on each iteration. None of the selections are a complete message that the FIFO Read BINARY block is looking for. The sequence produced by this subsystem is: step: output 0: [3 5 170 1] 1: [1 inc cnt 0 0] 2: [3 170 2 44] 3: [1 dec cnt 0 0] repeat Byte Count, 0 or 3 First header byte Second header byte Byte Count, 0 or 4 First header byte Second header byte Fixed data byte Decrementing counter Incrementing counter Copyright 2004-2019 The MathWorks, Inc. 6 bytes were read. The remaining 3 bytes can be ignored. 6 bytes were read. The remaining 2 bytes can be ignored.  ?

BLOCK:
Add;Constant;Count;Counter Limited;Data Type Conversion;FIFO bin read ;FIFO write ;Message 1 with header [170,1];Message 2 with header [170,2];Multiport Switch;Mux;Out;Reference;Scope FIFO Read ;Segmented Message Construction;SubSystem

BLOCKTYPE:
Constant;Counter Limited;DataTypeConversion;Display;FIFO Block: reader;FIFO Block: writer;MultiPortSwitch;Mux;Outport;Scope;Sum


MODELNAME: slrt_ex_serialbinarytest
PATH: toolbox/slrealtime/examples/slrt_ex_serialbinarytest.slx
BLOCKTYPE_FREQUENCY: 3;2;2;2;1;1;1;1;2;1
CHECKSUM: AC10889ABCB84A4A7D5EB5188ED7E716
PRODUCT: MATLAB;Simulink;Simulink Real-Time
DESCRIPTION:
Binary Encoding/Decoding Loopback Test This model shows how to send Binary data over a serial link. The transmitted data are: |[8,5,170,1,N,170,2,44,M]|. This byte stream contains two messages along with other elements as defined below. * The first byte, |8|, is a count of the remaining number of bytes in the stream. * The second byte, |5|, is an extraneous value (EV). * |[170,1,N]| is message 1 (M1). * |[170,2,44,M]| is message 2 (M2). * |N| and |M| are numbers between |0| and |255| that are incremenenting and decrementing, respectively. Even though the data stream includes extraneous bytes (|5| in this case), the FIFO Read BINARY block can handle and ignore this extra information. Scope 1 displays the received message 1 data. Scope 2 displays the received message 2 data. 

ANNOTATION:
Byte Count First header byte Second header byte Incrementing counter 6 bytes were read. The remaining 3 bytes can be ignored. Copyright 2004-2019 The MathWorks, Inc. Byte Count First header byte Second header byte Decrementing counter 6 bytes were read. The remaining 2 bytes can be ignored. Fixed data byte  ?

BLOCK:
Add;Constant;Counter Limited;Data Type Conversion;FIFO bin read ;FIFO write ;Message 1 with header [170,1];Message 2 with header [170,2];Message Construction;Mux;Out;Reference;Scope FIFO Read ;SubSystem

BLOCKTYPE:
Constant;Counter Limited;DataTypeConversion;Display;FIFO Block: reader;FIFO Block: writer;Mux;Outport;Scope;Sum


MODELNAME: slrt_ex_sf_car
PATH: toolbox/slrealtime/examples/slrt_ex_sf_car.slx
BLOCKTYPE_FREQUENCY: 1;2;6;17;2;6;1;13;6;1;2;1;1;3;1;1;1
CHECKSUM: B8EBD82750B6D9DE623150A5F4DC4AD9
PRODUCT: MATLAB;Simulink;Simulink Real-Time;Stateflow
ANNOTATION:
Vehicle TORQUE CONVERTER Choose Start from the Simulation menu to run the simulation. Double-click to open the GUI and select an input maneuver  Copyright 2008-2022 The MathWorks, Inc.  ?

BLOCK:
 Demux ; SFunction ;CALC_TH();Engine;Integrator;K factor;Look-Up Table;Mux;Ne;Nin;Nout;Product;Reference;Sign;SubSystem;Sum;Threshold Calculation;Ti;Tin;Torque Converter;Torque ratio;Tout;Tt;User Inputs;Vehicle;brake torque;down_th;engine + impeller inertia;engine RPM;engine torque;final drive ratio;gear;impeller;interp_down;interp_up;linear speed;mph;quotient;road load;run;shift_logic;signed load;speed;speed ratio;throttle;transmission;transmission output speed;transmission output torque;transmission ratio;turbine;up_th;vehicle inertia;vehicle mph (yellow) & throttle %;vehicle speed;wheel speed

BLOCKTYPE:
Demux;Fcn;Gain;Inport;Integrator;Lookup_n-D;Mux;Outport;Product;S-Function;Scope;SignalEditor;Signum;Sum;TriggerPort;torque converter;vehicle model


MODELNAME: slrt_ex_sine_waves
PATH: toolbox/slrealtime/examples/slrt_ex_sine_waves.slx
BLOCK: Scope;Sine Wave;Trigonometric Function
BLOCKTYPE: Scope;Sin;Trigonometry
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: 0D0D107DF34FF7143407B61D0AB96242
PRODUCT: MATLAB;Simulink;Simulink Real-Time
ANNOTATION:
Model slrt_ex_sine_waves Simulink Real-Time example model Copyright 2021-2022 The MathWorks, Inc.   ?


MODELNAME: slrt_ex_soc_dist
PATH: toolbox/slrealtime/examples/slrt_ex_soc_dist.slx
ANNOTATION: Model slrt_ex_soc_dist Simulink Real-Time example model Copyright 2020 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 1;2;24;1;9;16;17;1;10;11;24;1;21;2;3
CHECKSUM: D3328FBD3C69F985B99CF12E6DEA04A8
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
 Demux ; SFunction ; Terminator ;AND;Add;Clock;Compare To Constant;Constant;Discrete-Time Integrator;E;Exp;Gain;H;Ia;Im;Ip;Is;MATLAB Function;Math Function;Product;Reference;S;SubSystem;Subsystem;Switch;Terminator;dEIa;dEIp;dHD;dHR;dIaR;dImR;dIpIm;dIpIs;dIsH;dSE;date;soc_dist_end;thresh_H_end;thresh_H_start;y

BLOCKTYPE:
Clock;Compare To Constant;Constant;Demux;DiscreteIntegrator;Gain;Inport;Logic;Math;Outport;Product;S-Function;Sum;Switch;Terminator


MODELNAME: slrt_ex_sw_fc
PATH: toolbox/slrealtime/examples/slrt_ex_sw_fc.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 3;2;1;1;3;2;1;2;2;3;2
CHECKSUM: 47F8BA4182BF4A0CC70EF2B352694AC6
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Data Type Conversion;For Iterator;For Iterator Subsystem;Func ;Mux;Out;Pulse Generator;RT;Rate Transition;Reference;Scope;Sine Wave;SubSystem;Terminator;function;t1 Thread;t3 Thread

BLOCKTYPE:
DataTypeConversion;DiscretePulseGenerator;ForIterator;Mux;Outport;RateTransition;Scope;Simulink Real-Time software interrupt;Sin;Terminator;TriggerPort


MODELNAME: slrt_ex_target_to_host_TCP
PATH: toolbox/slrealtime/examples/slrt_ex_target_to_host_TCP.slx
ANNOTATION: slrt_ex_target_to_host_TCP Simulink Real-Time example model Copyright 2020 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 1;1;1;4;1;1;1;1;1;1;1
CHECKSUM: 4B45F4D3EF1B60584A8F1BC4C3EE198A
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Byte Packing ;Byte Unpacking;Constant;Mux;Reference;Signal Generator;TCP Receive;TCP Send;TCP Server;Terminator;Transfer Function;Width

BLOCKTYPE:
Constant;Mux;SignalGenerator;Terminator;TransferFcn;Width;slrealtimebytepacking;slrealtimetcpreceive;slrealtimetcpsend;slrealtimetcpserver;slreraltimebytepacking


MODELNAME: slrt_ex_target_to_host_UDP
PATH: toolbox/slrealtime/examples/slrt_ex_target_to_host_UDP.slx
ANNOTATION: slrt_ex_target_to_host_UDP Simulink Real-Time example model Copyright 2020 The MathWorks, Inc. ?
BLOCKTYPE_FREQUENCY: 2;1;1;1;1;1;1;1;1
CHECKSUM: 19033F93305904DD40229E07AB534766
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Byte Packing;Byte Unpacking ;Mux;Reference;Signal Generator;Terminator;Transfer Function;UDP Receive;UDP Send;Width

BLOCKTYPE:
Mux;SignalGenerator;Terminator;TransferFcn;Width;slrealtimebytepacking;slrealtimeudpreceive;slrealtimeudpsend;slreraltimebytepacking


MODELNAME: slrt_ex_udpsend
PATH: toolbox/slrealtime/examples/slrt_ex_udpsend.slx
ANNOTATION: Copyright 2021-2022 The MathWorks, Inc. ?
BLOCKTYPE: Clock;Constant;Display;EnablePort;RelationalOperator;Width;slrealtimeudpreceive;slrealtimeudpsend
BLOCKTYPE_FREQUENCY: 1;2;2;1;1;1;1;1
CHECKSUM: 7FD7733A15C0DE856357A307E855CAE0
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCK:
Clock;Display;Enable;Equal;Reference;SendPacketSubsystem;SubSystem;UDP Receive;UDP Send;Width;enableAtTime;payload


MODELNAME: slrt_ex_udpsendreceiveA
PATH: toolbox/slrealtime/examples/slrt_ex_udpsendreceiveA.slx
ANNOTATION: Copyright 2006-2022 The MathWorks, Inc. ?
BLOCK: Byte Packing ;Byte Unpacking ;C;Receive;Reference;Send;Terminator;Width
BLOCKTYPE_FREQUENCY: 3;5;1;1;1;1;1
CHECKSUM: 0593F512BC7DE4BFE911E4FEBC789A29
PRODUCT: MATLAB;Simulink;Simulink Real-Time
BLOCKTYPE:
Constant;Terminator;Width;slrealtimebytepacking;slrealtimeudpreceive;slrealtimeudpsend;slreraltimebytepacking


MODELNAME: slrealtimeTemplate
PATH: toolbox/slrealtime/simulink/coder/templates/slrealtimeTemplate.slx
BLOCK: Gain;Scope;Sine Wave
BLOCKTYPE: Gain;Scope;Sin
BLOCKTYPE_FREQUENCY: 1;1;1
CHECKSUM: 9DE10AF8D42AF796E2CF866F7634C04C
PRODUCT: MATLAB;Simulink;Simulink Real-Time
PRODUCT_BASECODE: XP
ANNOTATION:
This model has been set up with FixedStepDiscrete solver, stop time=10s, and sample time = 1ms. Click here to adjust these options.  ?


MODELNAME: LogicAnalyzerPlot
PATH: toolbox/soc/fpga/simulation/LogicAnalyzerPlot.slx
ANNOTATION: SoC Blockset 24.1 Copyright 2019-2024 The MathWorks, Inc.
BLOCKTYPE: Demux;Ground;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;1;12;1;13
CHECKSUM: 63F3D12200AFECB4E858DB5308F659BF
PRODUCT: Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HW
BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;DMA1FIFOUtilization;DMA2FIFOUtilization;Master;Overall;SubSystem;Terminator;TimeInfo;Trace Data


MODELNAME: soc_ADSB
PATH: toolbox/soc/socexamples/soc_ADSB.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;5;1;2;3;1;1;1
CHECKSUM: E95F6DB89C73252E0827F77192AB9838
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_ADSB_fpga.slx___Model_Block___soc_ADSB_proc___Model_Block___
ANNOTATION:
External I/O External I/O  Packet-Based ADS-B Transceiver  Memory Processor FPGA  Copyright 2019-2022 The MathWorks, Inc.

BLOCK:
AD9361Rx;AD9361Tx;AXI4-Stream to Software;Channel;Enable;FPGA Algorithm;IO Data Sink;LED;Processor;Processor-Frame based processing;RFIn;RFOut;Reference;Simple delay channel;SubSystem;Task Manager;Terminator;UDP Write;UDP Write ;UDP data;data;dataTask;done

BLOCKTYPE:
AD9361 Rx Playback;AD9361 Tx Playback;AXI4-Stream to Software;Delay;EnablePort;IO Data Sink;Inport;LED;ModelReference;Outport;Task Manager;Terminator;UDP Write


MODELNAME: soc_ADSB_UDP_HostPrintout
PATH: toolbox/soc/socexamples/soc_ADSB_UDP_HostPrintout.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc. Host Model for Receiving ADS-B Messages
BLOCKTYPE: Demux;Inport;S-Function;Terminator;UDP Read
BLOCKTYPE_FREQUENCY: 1;2;1;1;1
CHECKSUM: 11A32ED13145D0C45B23249877523893
PRODUCT: MATLAB;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
 Demux ; SFunction ; Terminator ;MATLAB Function;Reference;SubSystem;UDP Read;dataLength;dataReceived


MODELNAME: soc_ADSB_fpga
PATH: toolbox/soc/socexamples/soc_ADSB_fpga.slx
BLOCKTYPE_FREQUENCY: 2;1;5;2;8;1;1;5;1;1;1;7;6;32;1;2;1;2;1;8;1;3;42;13;1;2;1;2;52;1;1;1;1;1;2;4;4;1;2;5;1
CHECKSUM: 377DFF25B5FF2CF3F64BA223C4E116BC
PRODUCT_BASECODE: HW
ANNOTATION:
Grab only 16 newest samples (including current input bit from TDL) Pad MSBs with zeros MSB in word is newest sample 33 rows = 32 bits in TDL + current input bit (needed to form last word at correct time...) Toggle on last word 4-word FIFO Delay compensation (32/4 == 8) Tapped Delay Line and concatenate Count for word (to 32) Valid Bit Counter delay of the approximation is 4 clock clyces - delay valid signal to account for this sqrt(I^2+Q^2) can be approximated as |L|+0.4*|S|, where |L| is the absolute value of the larger of I or Q, and |S| is the absolute value of the smaller of I or Q. See |L|+0.4|S| Algorithm on page 238 in Digital Signal Processing in Communication Systems by Marvin Frerking.  Type Conversion from 12bit int16to 16bit_15 (0:1)  NOTE: In this system, the data source (an AD9361 FMC board) cannot stop sending data in the presence of back-pressure. So, if back-pressure is asserted, then very quickly any FIFOs will get full and data will be dropped. Instead of delaying the inevitable, we let the source continue, and indicate that data is being dropped by means of an LED. ADS-B data is only present on the real channel, imaginary samples are all set to 0 See note in ADS-B Rx about back-pressure. An LED will toggle with each received packet. An LED will light when data has been dropped. Copyright 2019 The MathWorks, Inc.

BLOCK:
; Demux ; SFunction ; Terminator ;1-D Lookup Table;ADS-B Data Source Select;ADS-B RX;ADS-B Rx Algorithm;ADS-B Tx Algorithm;AND;Abs;ActivateBP;Add;Assertion;Bit Concat;Bit Process;Bit Shift;Bit Slice;Bit-Shift;BitPacking;BitPacking_32bit;Bus Creator;Bus Selector;CRC_Valid;CalcSyncCorr;Calculate Threshold;Ch1Q_Ch1I_FPGA;Ch1Q_Ch1I_RF;Compare To Constant;Compare To Zero;Complex Modulus;Complex to Real-Imag;Compute CRC and Frame validation;Constant;CurrentBit;Data Type Conversion;Delay;Delay Enable;Discrete FIR Filter;En;Enable;Enabled Delay;FIFO_comp;FPGAdata;Falling Edge Detector;Frame Bit Out;Gain;General CRC Syndrome HDL Optimized;HDL Counter;HDL FIFO;HDLRxIpCore;HDLTxIpCore;IP Core Register Read;ImagIn;In;LED;Logical;Logical Operator;MagOut;MinMax;Multiport Selector;Multiport Switch;Out;Preamble detection;PrepInputs;Product;Real-Imag to Complex;RealIn;Reference;Relational Operator;Reset;Rfdata;Rising Edge Detector;RstFrame;RxData;RxDataI_In;RxDataI_Out;RxDataQ_In;RxDataQ_Out;RxValid_Out;Scope;Signal Specification;State Control;SubSystem;Subsystem;Subtract;Switch;SyncCorr;TDL_comp;Tapped Delay;TappedDelayEnabled;Terminator;Threshold;Timing Control;Trigger;TxData;TxDataI_Out;TxDataQ_Out;TxTransmitPeriod;TxValid;TxValid_Out;Valid;Valid Generation;ValidBit;ValidFrame;ValidGen;ValidOut;XOR;bitIn;bit_in;chCtrlIn;chCtrlOut;chData;crcValid;dataDropped;dataIn;dataOut;dataValidIn;dvalidOut;in;last_Word;last_word_out;out;readyFromDown;signal spec;threshold;valid;validIn;validOout;validOut;valid_RF;wordOut;word_out

BLOCKTYPE:
Abs;Assertion;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Compare To Zero;Complex Modulus;ComplexToRealImag;Constant;DataTypeConversion;Delay;Demux;DiscreteFir;EnablePort;Gain;General CRC Syndrome Detector HDL Optimized;HDL Counter;HDL_FIFO;IP Core Register Read;Inport;Logic;Lookup_n-D;MinMax;MultiPortSwitch;Multiport Selector;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Scope;SignalSpecification;StateControl;Sum;Switch;Tapped Delay Line;Terminator;TriggerPort

PRODUCT:
Communications Toolbox;DSP System Toolbox;Embedded Coder;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset


MODELNAME: soc_ADSB_proc
PATH: toolbox/soc/socexamples/soc_ADSB_proc.slx
BLOCKTYPE_FREQUENCY: 1;3;1;1;5;6;3;1;1;2;1;1;1;1
CHECKSUM: C80820CCAE100EA75629F26E9B24D9EA
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
ANNOTATION:
Threshold for detection algorithm Transmit period of test waveform, in clock cycles. Must be greater than 500. Select RF data (0) or FPGA data (1) Copyright 2019 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Asynchronous Task Specification;Constant;Event Listener;Initialize Function;Processor Algorithm;Processor Algorithm Wrapper;Reference;Register Write;Stream Read;SubSystem;Terminator;Trigger;UDP Write;UDP data;Unpack ADSB Messages;Zynq and FMCOMMS2/3/4 Receiver;Zynq and FMCOMMS2/3/4 Transmitter;data;dataTask;done;packedFrame;unpackedFrame

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;Demux;EventListener;Inport;Outport;Register Write;S-Function;Stream Read;Terminator;TriggerPort;UDP Write;comm.internal.SDRRxZC706FMC234RFSL;comm.internal.SDRTxZC706FMC234RFSL


MODELNAME: soc_ddr4datacapture_fpga
PATH: toolbox/soc/socexamples/soc_ddr4datacapture_fpga.slx
BLOCKTYPE_FREQUENCY: 1;2;1;1;2;2;2;3;5;2;9;15;3;3;1;26;6;14;3;2;6;90;65;4;88;4;2;3;4;1;5;6;19;4;7
CHECKSUM: 73F30992E4131166B6C8F1761B37F1DA
PRODUCT: DSP HDL Toolbox;Fixed-Point Designer;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input Trigger every 0.5 sec by default This will wait for WrReady to go online first before enabling TriggerOut Ignore Trigger Captures if we are still reading DDR out  AXI4 MM Writes AXI4 MM Diagonstics axim_rd_m2s - DDR Read AXI4 Stream Master DMA  axim_rd_s2m - DDR Read Ack axim_wr_m2s - DDR Write axim_wr_s2m - DDR Write Ack  Using 4 NCOs to generate 4 samples in one clock  Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;64BitSample;<wr_complete>;ADC Capture;ADC_Data;ADC_Valid;AXI4S_Master_FIFO ;AXI4Trigger;AXI4_Trigger;AXIS_DMA_FIFO_AFull;AXIS_Data;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;AXIS_Valid;Add;AlmostFull;AutoTrigger;BckPrssre;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CaptureFIFONum;CaptureFIFONumReg;CaptureValid;Channel1_Scaling;Compare To Constant;Compare To Zero;Constant;CounterOut;DAC Tone Generation;DDR Read Conroller;DDR Write Conroller;DDR4 Capture;DDRWrStart;DDR_WrStart;Data Type Conversion;DataCaptureEn;DataCaptureLogic;DataPushFrequency;DebugCapture;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;FIFO_AFull;FIFO_DataAvail;FrameSize;From;Gain;Goto;HDL Counter;HDL FIFO;IP Core Register Read;In;Logical Operator;MATLAB Function;MaxCount;NCO HDL Optimized;NCO1_Valid;NCO_Vector_samples;NCO_tData;NOT;Out;Product;Q;R;ReadDone;Ready;Reference;Relational Operator;Reset;Rst;S;SW_en;Sample;Signal Conversion;Signal Specification;SubSystem;Subsystem;Switch;TLAST_Out;Terminator;ToggleTLAST;Tready;Trig;Trigger;TriggerCapture;TriggerOut;Unit Delay;WastedWriteCycles;WrNotRdy;WrReady;WrValid;adcDataIn;adcTdata;adcTlast;adcTvalid;adcValid;adcValidin;afull;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_rd_valid;axim_wr_m2s;axim_wr_s2m;axis_master_ready;burst_len;cache_reg;captureDataOut;capture_fifo_num;capture_fifo_rd_ack;chCtrlIn;chCtrlOut;count_out;dacData;dacValid;data_i;data_o;ddr4rdctrlin;ddr4rdctrlout;ddr4rddata;ddr4wrctlout;ddr4wrctrlin;ddr4wrctrlout;ddr4wrdata;ddr_read_done;ddr_write_done;debug_state;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;ram_addr;rd_ack;rd_ack_i;rd_ack_low_count;rd_addr;rd_aready;rd_avalid;rd_dvalid;rd_len;scaleIn;scaleOut;shift 16 bits;shift 32 bits;shift 48 bits;sr_latch;start;streamEn;triggerFreq;valid_out;wasted_cycle_cnt;wr_addr;wr_complete;wr_data;wr_len;wr_ready;wr_valid

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;IP Core Register Read;Inport;Logic;NCO;Outport;Product;RelationalOperator;S-Function;SignalConversion;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_ddr4datacapture_proc
PATH: toolbox/soc/socexamples/soc_ddr4datacapture_proc.slx
BLOCKTYPE_FREQUENCY: 1;1;6;5;1;4;2;3;4;6;5;1;1;1;1
CHECKSUM: C9703FBF7C2E2E8A6533C855C045B8BE
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Phase increment value for the corresponding sinusoidal tone frequency.  Bit slicing the input 64bit stream data into 4 16bit samples.  Reshaping the frame data to arrange it in a column vector of consecutive samples. Copyright 2021 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Constant;Data Type Conversion;DataIn;DataOut;DataTask;Event Listener;Extract Bits;Gain;Initialize Function;Processor Algorithm Wrapper;Reference;Register Write;Reshape;Slider Gain;Stream Read;SubSystem;Terminator;Trigger;Vector Concatenate;dataIn;dataOut;done

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;EventListener;Extract Bits;Gain;Inport;Outport;Register Write;Reshape;Slider Gain;Stream Read;Terminator;TriggerPort


MODELNAME: soc_ddr4datacapture_top
PATH: toolbox/soc/socexamples/soc_ddr4datacapture_top.slx
BLOCKTYPE_FREQUENCY: 1;1;1;3;2;3;1;1;1;2;1
CHECKSUM: 2AD1064BD728264FAE30B3AD57D32B74
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_ddr4datacapture_fpga.slx___Model_Block___soc_ddr4datacapture_proc.slx___Model_Block___
ANNOTATION:
 Copyright 2021-2022 The MathWorks, Inc.  Data Capture Using DDR4 on RFSoC Device FPGA Processor Testbench Output RF I/O PL Memory PS Memory

BLOCK:
ADC Captured Scope Output;ADC Captured Signal;AXI4 Random Access Memory;AXI4-Stream to Software;DAC Output;Delay;FPGA Data Capture;Processor;Processor - Frame based processing;RF Data Converter;RF Loopback;Rate Transition;Reference;SubSystem;Task Manager;adc1In;dac7Out;dataIn;dataOut;dataTask;done

BLOCKTYPE:
AXI4 Random Access Memory;AXI4-Stream to Software;Delay;Inport;ModelReference;Outport;RF Data Converter;RateTransition;Scope;SpectrumAnalyzer;Task Manager


MODELNAME: soc_ddr4transmitrepeat_fpga
PATH: toolbox/soc/socexamples/soc_ddr4transmitrepeat_fpga.slx
BLOCKTYPE_FREQUENCY: 4;16;2;2;9;10;5;3;3;7;2;16;46;8;5;1;31;20;3;2;9;144;69;154;3;8;4;20;2;2;9;9;31;4;7
CHECKSUM: 91D9B11615633A2ED0E9180EF81C14E5
PRODUCT: Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
ANNOTATION:
Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious  This is to prevent any left over samples in registers that are not valid WrStart triggers DDR state machine OutputAddr and OutputLen is fed to DDR State Machine Samples are fed into FWFT FIFO with its rdy-valid signal attached.  if VALID_PULSE pulse out a frame start if WAIT_FOR_PULSE check if current/previous pulse differ If TLAST on next clock cycle if valid, pulse frame start detect on next clock cycle if ~valid, be in wait for start state  Route DDR4 Read Data To DAC Start DDR Read After Wr Complete AXI4 MM Writes AXI4 MM Reads axim_rd_m2s - DDR Read axim_rd_s2m - DDR Read Ack axim_wr_m2s - DDR Write axim_wr_s2m - DDR Write Ack AXI4 Stream Slave DMA  Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious AXI4 MM Read Registers Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input  Copyright 2021 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;<AXIS_Slave_Tlast>;<AXIS_Slave_Valid>;<DataOut>;<signal1>;AFull;AXI4 Master DDR4 Read CtrlIn;AXI4 Master DDR4 Read CtrlOut;AXI4 Master DDR4 Read Data;AXI4 Master DDR4 Write CtrlIn;AXI4 Master DDR4 Write CtrlOut;AXI4 Master DDR4 Write Data;AXI4-Stream DMA Master CtrlIn;AXI4-Stream DMA Master CtrlOut;AXI4-Stream DMA Master Data;AXI4-Stream DMA Slave CtrlIn;AXI4-Stream DMA Slave CtrlOut;AXI4-Stream DMA Slave Data;AXI4-Stream DMA Slave Ready;AXI4-Stream DMA Slave Tlast;AXI4-Stream DMA Slave Valid;AXI4M_WrComplete;AXI4RdCount;AXI4S;AXI4SDecode;AXI4S_Tready;AXI4WrCount;AXI4_AXISDecodeState;AXI4_DDR4State;AXI4_FIFOCapture_Overflow;AXI4_FIFO_AFULL;AXI4_RdCommplete;AXI4_RdGapCount;AXI4_ReadCompleteCount;AXI4_Slave_Ready;AXI4_WRIgnoredCmd;AXI4_WrAddrCmd;AXI4_WrLenCmd;AXI4_WrValidAccum;AXI4_WriteCompleteCount;AXIS_DMA_FIFO_AFull;AXIS_FIFO_Full;AXIS_FIFO_Num;AXIS_FrameInfo;AXIS_MM2S;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;AXIS_OutputAddr;AXIS_OutputLen;AXIS_Slave_Data;AXIS_Slave_TLast;AXIS_Slave_Valid;AccumulatedWrValid;Add;AutoTrigger;BackPressureCounterEn;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CaptureFIFONum;CaptureFIFONumReg;CaptureOverflowCount;Compare To Constant;Compare To Zero;ConsecFrames;Constant;DAC Interface;DACI;DACQ;DAC_Write;DDR Read Conroller;DDR Write Conroller;DDR4 Transmit Repeat;DDR4WrAddr;DDR4WrLen;DDR4WrStart;DDR4_DAC_Data;DDR4_RdInfo;DDR4_Wr_State;DDRAddr;DDRWrLen;DDR_Capture_Logic;DDR_Wr_Comp;Data;Data Type Conversion;DataAvailable;DataCaptureEn;DataOut;DataPushFrequency;DebugBus;DebugInput;DebugReg;DebugRegisters;DecodeFrameInfo;DecodeState;Decode_AXIS_Frame;Decode_State_Machine;Decode_State_Machine_OLD;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Detect Start Of AXI4S Frame;DetectHeader;Display;EnableAuto;EnableConsecutiveFrames;EnumToInteger;FIFO_DataAvail;FWFT_FIFO;FormatData;FrameAddrWr;FrameLen;FrameSizeRd;FrameStartDetect;From;Goto;HDL Counter;HDL FIFO;IP Core Register Read;IgnoreCmdPulse;IgnoredCmd;In;IntOut;IterationNum;Logical Operator;MATLAB Function;MM2S_Data;MM2S_Ready;MM2S_TLast;MM2S_Valid;MaxCount;MuteDAC;NotIdle;OffsetAddr;Out;OutputAddr;OutputLen;Q;R;RdAddr;RdData;RdFrameAddrInput;RdFrameAuto;RdFrameIterations;RdFrameManual;RdGapCount;RdIterations;RdLen;RdLoopActive;RdMode;RdStart;RdTrigger;RdTriggerMode;ReadActive;ReadCompleteCount;Reference;Relational Operator;S;SW_en;SelectRdTriggerSource;Selector;Signal Conversion;Signal Specification;SoC Bus Creator;SoC Bus Selector;State;State Control;StateMachine;StateOutput;StoreLengthAddr;StreamEn;SubSystem;Subsystem;Switch;TData;TDataIn;TDataOut;TLast;TLastTAG;TReady;TValid;Terminator;Tile1 DAC Ch2 IData;Tile1 DAC Ch2 QData;Tile1 DAC Ch2 Valid;ToggleTLAST;Transmit Repeat;Trig;Trigger;Trigger Capture;TriggerAuto;TriggerCapture;TriggerManual;TriggerRisingEdge;Unit Delay;Valid;ValidHeaderPkt;ValidOut;ValidPkt;Vector Concatenate;WrAddrCmd;WrLenCmd;WrStart;WrStartPulse;WrValid;WriteCompleteCount;adcIData;adcQData;adcValid;afull;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_wr_data;axim_wr_m2s;axim_wr_s2m;burst_len;cache_reg;count_out;dacIData;dacQData;dacValid;data_i;data_o;ddr_read_done;ddr_write_done;debug_state;detect_increase;dtci;empty_i;empty_o;enb;full;fwft_logic;gap_counter;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;pulseOut;push;ram_addr;rd_ack;rd_ack_i;rd_addr;rd_addr_base;rd_aready;rd_avalid;rd_dvalid;rd_len;sr_latch;start;stateMeasure;state_machine;tlast;u;valid;valid_out;wasted_cycle_cnt;wr_addr;wr_complete;wr_data;wr_len;wr_ready;wr_valid;y

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Goto;HDL Counter;HDL_FIFO;IP Core Register Read;Inport;Logic;Outport;RelationalOperator;S-Function;Selector;SignalConversion;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_ddr4transmitrepeat_proc
PATH: toolbox/soc/socexamples/soc_ddr4transmitrepeat_proc.slx
ANNOTATION: Copyright 2021 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;1;10;1;1;1;1;1;11;10;2;10;1;1;1;4;2
CHECKSUM: 3D47C20B8B63BCC20C391907FD81C964
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;AXI4RdCount;AXI4WrCount;Asynchronous Task Specification;Buffer;Compare To Constant;Constant;Delay;Enable;Enable DUT DDR Read;Event Listener;Initialize Function;ReadActive;Reference;Register Read;Register Write;Stream Read;Stream Write;SubSystem;Subsystem;Terminator;Trigger;dataReadTask;dataWriteTask;done;msg;readDataIn;readDataOut;readDone;waveFormReader;writeDataOut;writeDone

BLOCKTYPE:
AsynchronousTaskSpecification;Compare To Constant;Constant;Delay;Demux;EnablePort;EventListener;Ground;Inport;Outport;Register Read;Register Write;S-Function;Stream Read;Stream Write;Terminator;TriggerPort


MODELNAME: soc_ddr4transmitrepeat_top
PATH: toolbox/soc/socexamples/soc_ddr4transmitrepeat_top.slx
BLOCKTYPE_FREQUENCY: 1;1;4;8;1;1;4;8;2;6;1;1;2;1;6;1;2;1
CHECKSUM: FD8622EC742441CD5989644750C48850
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_ddr4transmitrepeat_fpga.slx___Model_Block___soc_ddr4transmitrepeat_proc.slx___Model_Block___
ANNOTATION:
 Transmit Repeat a Waveform Using DDR4 on Xilinx RFSoC Device  Copyright 2021-2022 The MathWorks, Inc. RF I/O FPGA Processor Testbench Output PS Memory PL Memory

BLOCK:
ADC Spectrum;AXI4 Random Access Memory;AXI4-Stream to Software;AXI4RdCount;AXI4WrCount;DAC Spectrum;Data Type Conversion;Delay;Demux;Extract Bits;FPGA;Loop back;Packed data;Processor;Processor - Frame based processing;RF Data Converter;RT;ReadActive;Real-Imag to Complex;Reference;Register Channel;Reshape;Software to AXI4-Stream;SubSystem;Task Manager;Unpack data;Unpacked data;Vector Concatenate;adcIn;dacOut;dataReadTask;dataWriteTask;readDataIn;readDataOut;readDone;writeDataOut;writeDone

BLOCKTYPE:
AXI4 Random Access Memory;AXI4-Stream to Software;Concatenate;DataTypeConversion;Delay;Demux;Extract Bits;Inport;ModelReference;Outport;RF Data Converter;RateTransition;RealImagToComplex;Register Channel;Reshape;Software to AXI4-Stream;SpectrumAnalyzer;Task Manager


MODELNAME: soc_histogram_equalization_frame
PATH: toolbox/soc/socexamples/soc_histogram_equalization_frame.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;1;3;1;2;15;17;2;3;1;5
CHECKSUM: 9573113BCB120018AC9C969FAB10C775
PRODUCT: Embedded Coder;Image Processing Toolbox;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
 Demux ; SFunction ; Terminator ;Bus Creator;Bus Selector;Constant;Delay;HSize;HistogramEqualization;LED;Reference;Selector;SubSystem;Switch;Terminator;VSize;Vector Concatenate;accumOut;applyHistEq;bypass;cdf_vector;computeHist;frBufRdCtrlIn;frBufRdCtrlOut;frBufRdData;frBufWrCtrlIn;frBufWrCtrlOut;frBufWrData;fromBuffCtrl;fromBuffData;fromBuffRdy;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;im;imageIn;pbBypass;toBuffCtrl;toBuffData;toBuffFsync;toBuffRdy;y

BLOCKTYPE:
Bus Creator;Bus Selector;Concatenate;Constant;Delay;Demux;Inport;Outport;S-Function;Selector;Switch;Terminator


MODELNAME: soc_histogram_equalization_pixel
PATH: toolbox/soc/socexamples/soc_histogram_equalization_pixel.slx
BLOCKTYPE_FREQUENCY: 1;3;1;1;1;1;2;9;2;2;3;1;33;28;1;2;3;1;1;3;3;2
CHECKSUM: 87399702A59BACB115E4FE9BADE9514C
PRODUCT: Embedded Coder;Fixed-Point Designer;Simulink;SoC Blockset;Vision HDL Toolbox
PRODUCT_BASECODE: HW
ANNOTATION:
Create an always HIGH signal for ready as it is not generated by HDMI Output. Terminate the wrCtrlOut (ready signal) as it is not handled by HDMI input Copyright 2019 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Constant;CtrlIn;Delay;Display;Equalization;HDL Counter;HSize;Histogram;Histogram Computation;HistogramEqualization;LED;Pixel Control Bus Selector;PixelIn;Rate Transition;Reference;Signal Specification;State Control;SubSystem;Sum;Switch;Terminator;VSize;Video Stream Connector;Video Stream FIFO;accmHist;accm_hist;accumHist;applyEq;binReset;bypass;cdf;cdfIn;cdfVectorGen;cdf_vector;ctrl;ctrlBusIn;ctrlIn;ctrlOut;detectFrameSize;done;error;frBufRdCtrlIn;frBufRdCtrlOut;frBufRdData;frBufWrCtrlIn;frBufWrCtrlOut;frBufWrData;fromBuffCtrl;fromBuffData;fromBuffRdy;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;histComp;hist_accum;hist_data;histeqVideo;im;orgVideo;pbBypass;pixel;pixelIn;pixelOut;readDone;ready;toBuffCtrl;toBuffData;toBuffFsync;toBuffRdy;valid;validOut;wrCtrlOut;y;ycdf

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;BusSelector;Compare To Constant;Constant;Delay;Demux;Display;HDL Counter;Histogram;Inport;Outport;RateTransition;S-Function;SignalSpecification;StateControl;Sum;Switch;Terminator;Video Stream Connector


MODELNAME: soc_histogram_equalization_top
PATH: toolbox/soc/socexamples/soc_histogram_equalization_top.slx
BLOCKTYPE_FREQUENCY: 1;1;1;6;1;1;2;6;1
CHECKSUM: F3B72C21B114B4DADB02A937443F6F05
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
ANNOTATION:
External Memory External I/O  Copyright 2019-2022 The MathWorks, Inc.  Histogram Equalization Using Video Frame Buffer FPGA  External I/O 

BLOCK:
 frBufRdCtrlOut; frBufWrCtrlOut; frBufWrData;Contention;FPGA;Frame Buffer;Frame based processing;HDMI Rx;HDMI Tx;LED;Pixel based processing;Push Button;Reference;SubSystem;frBufRdCtrlIn ;frBufRdData ;frBufWrCtrlIn ;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;pbBypass

BLOCKTYPE:
AXI4 Video Frame Buffer;HDMI Rx;HDMI Tx;Inport;LED;Memory Traffic Generator;ModelReference;Outport;Push Button

EXTERNALFILE_REFERENCE:
soc_histogram_equalization_frame.slx___Model_Block___soc_histogram_equalization_pixel.slx___Model_Block___


MODELNAME: soc_hwsw_interrupt_fpga
PATH: toolbox/soc/socexamples/soc_hwsw_interrupt_fpga.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: Bit Slice;Counter Free-Running;EnablePort;Inport;Logic;Outport;UnitDelay
BLOCKTYPE_FREQUENCY: 4;2;4;6;10;14;4
CHECKSUM: 9AD2BC228DD955E7F6477CA5EEA40922
PRODUCT: Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
AND;Bit Slice;Counter;Counter Free-Running;Enable;Interrupt Generator;Latch Counter Value;NOT;OR;Out;Reference;SubSystem;Unit Delay;cntVal;enable;interrupt


MODELNAME: soc_hwsw_interrupt_proc
PATH: toolbox/soc/socexamples/soc_hwsw_interrupt_proc.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 2;2;1;6;8;2;2;2
CHECKSUM: B54BE91A734233120689E52E8BE0A804
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
Asynchronous Task Specification;Constant;Event Listener;Initialize Function;Processor Algorithm;Reference;Register Read;Register Write;SubSystem;Trigger;cntVal;cntValIn;enable;interruptTask

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;EventListener;Inport;Outport;Register Read;Register Write;TriggerPort


MODELNAME: soc_hwsw_interrupt_top
PATH: toolbox/soc/socexamples/soc_hwsw_interrupt_top.slx
BLOCKTYPE: Inport;Interrupt Channel;ModelReference;Outport;RateTransition;Register Channel;Scope;Task Manager
BLOCKTYPE_FREQUENCY: 4;1;2;4;2;2;1;1
CHECKSUM: B979E2282BF7E64FAD383C48E1CD0FD6
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_hwsw_interrupt_fpga.slx___Model_Block___soc_hwsw_interrupt_proc.slx___Model_Block___
ANNOTATION:
FPGA Processor  Triggering Software Tasks by FPGA Interrupts  Copyright 2020 The MathWorks, Inc. Interrupt Register Testbench Output 

BLOCK:
FPGA;Interrupt Channel;Processor;Rate Transition;Reference;Register Channel;Scope;SubSystem;Task Manager;cntVal;cntValIn;enable;interruptTask1Event;interruptTask2Event


MODELNAME: soc_hwsw_stream_fpga
PATH: toolbox/soc/socexamples/soc_hwsw_stream_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;10;1;2;1;15;18;16;2;1;15;1;2;15
CHECKSUM: DE772108B96004A14EAA1AA98D5C2C4C
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Outputs need to be scaled since filter used integer coefficients NOTE: Data output from DUT must be 32 bits  Copyright 2019 The MathWorks, Inc.

BLOCK:
10KHz Wave;1KHz Wave;Bus Creator;Bus Selector;Cast;Compare To Constant;Constant;Counter Limited;Data Stream Wire Channel;DataIn;DataOut;Enable;FPGA;FPGA Algorithm;FPGA Algorithm Wrapper;HeadSumR;HighFreq;HighFreqIndicator;HighFreqIndicatorOut;In;Low Pass Filter fstop/fpass = 0.45/0.;LowFreq;LowFreqIndicator;LowFreqIndicatorOut;Out;Product;RdyIn;RdyOut;Reference;Scale Output;Shift Arithmetic;Signal Generator;SourceSelector;SubSystem;Switch;Terminator;Test Source;Test Source Wrapper;TestData;TestValid;Tlast;Unit Delay;ValidIn;ValidOut;rdCtrlIn;rdCtrlOut

BLOCKTYPE:
ArithShift;Bus Creator;Bus Selector;Compare To Constant;Constant;Counter Limited;DataTypeConversion;EnablePort;Inport;Outport;Product;Sine Wave;Stream Connector;Sum;Switch;Terminator;UnitDelay


MODELNAME: soc_hwsw_stream_fpga_frame
PATH: toolbox/soc/socexamples/soc_hwsw_stream_fpga_frame.slx
BLOCKTYPE_FREQUENCY: 1;1;1;11;2;1;15;18;16;2;1;15;1;2;15
CHECKSUM: 4798F05E10143621911983D99D58059D
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Outputs need to be scaled since filter used integer coefficients NOTE: Data output must be 32 bits  Copyright 2019 The MathWorks, Inc.

BLOCK:
10KHz Wave;1KHz Wave;Bus Creator;Bus Selector;Cast;Constant;Data Stream Wire Channel;DataIn;DataOut;Enable;FPGA;FPGA Algorithm;FPGA Algorithm Wrapper;HeadSumR;HighFreqIndicator;HighFreqIndicatorOut;HighFrequencySignal;In;Low Pass Filter fstop/fpass = 0.45/0.;LowFreqIndicator;LowFreqIndicatorOut;LowFrequencySignal;Out;Product;RdyIn;RdyOut;Reference;Scale Output;Shift Arithmetic;Signal Generator;SourceSelector;SubSystem;Switch;Terminator;Test Source;Test Source Wrapper;TestData;TestValid;Tlast;Unit Delay;Valid;ValidIn;ValidOut;dataIn;dataOut;rdCtrlIn;rdCtrlOut;signalOut

BLOCKTYPE:
ArithShift;Bus Creator;Bus Selector;Constant;DataTypeConversion;EnablePort;Inport;Outport;Product;Sine Wave;Stream Connector;Sum;Switch;Terminator;UnitDelay


MODELNAME: soc_hwsw_stream_implementation
PATH: toolbox/soc/socexamples/soc_hwsw_stream_implementation.slx
BLOCKTYPE_FREQUENCY: 3;1;2;28;3;1;15;2;1;2;19;34;1;2;47;1;2;47
CHECKSUM: D8DB545968914A76E8BB24EA1540E21C
PRODUCT: DSP System Toolbox;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Outputs need to be scaled since filter used integer coefficients Testbench Output  FPGA Processor Buffer High Freq Signal Low Freq Signal  DIP Switch External Input Detected Signal (LEDs) Copyright 2019-2021 The MathWorks, Inc.

BLOCK:
10KHz Wave;1KHz Wave;BodySumL;BodySumR;Buffer;Cast;Compare To Constant;Constant;DataIn;DataOut;Downsample;FPGA;FootSumR;HeadSumL;HeadSumR;High Pass Filter;High Pass Filter fc = 3KHz;HighFreq;HighFreqIndicator;In;Lamp;Low Pass Filter;Low Pass Filter fc = 3KHz;Low Pass Filter fstop/fpass = 0.45/0.;LowFreq;LowFreqIndicator;Manual Switch;Max;Out;OutData;Processor Algorithm;Product;Reference;Scale Filter Output;Scale Filter Outputs;Scale Output;SelectHighFreq;SelectLowFreq;Shift Arithmetic;Signal Generator;SourceSelector;SubSystem;Switch;Terminator;Test Source;TestData;Threshold;Unit Delay;Vector Scope;dataIn;dataOut

BLOCKTYPE:
ArithShift;Buffer;Compare To Constant;Constant;DataTypeConversion;DownSample;Inport;LampBlock;ManualSwitch;MinMax;Outport;Product;Scope;Sine Wave;Sum;Switch;Terminator;UnitDelay


MODELNAME: soc_hwsw_stream_proc
PATH: toolbox/soc/socexamples/soc_hwsw_stream_proc.slx
BLOCKTYPE_FREQUENCY: 2;1;2;18;3;12;2;19;18;2;1;32;1;1;32;2
CHECKSUM: 4E89747BFAA7A73DA36B230BBE565308
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
NOTE: BusyWait blocks are inserted to match task duration on hardware  Copyright 2019 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;BodySumL;BodySumR;Busy Wait;Cast;Compare To Constant;Constant;Data Type Conversion;DataIn;DataOut;DataTask;FootSumR;HeadSumL;High Pass Filter;High Pass Filter fc = 3KHz;HighFreqIndicator;In;Low Pass Filter;Low Pass Filter fc = 3KHz;LowFreqIndicator;Max;Out;OutData;Processor Algorithm;Processor Algorithm Wrapper;Product;Reference;Register Write;Scale Filter Output;Scale Filter Outputs;Shift Arithmetic;Stream Read;SubSystem;Terminator;Threshold;Trigger;Unit Delay;dataIn;dataOut;done

BLOCKTYPE:
ArithShift;AsynchronousTaskSpecification;Compare To Constant;Constant;DataTypeConversion;Inport;MinMax;Outport;Product;Register Write;Stream Read;Sum;Terminator;TriggerPort;UnitDelay;soc.blocks.BusyWait


MODELNAME: soc_hwsw_stream_top
PATH: toolbox/soc/socexamples/soc_hwsw_stream_top.slx
BLOCKTYPE_FREQUENCY: 1;2;1;6;1;2;1;3;8;1;1;1;1
CHECKSUM: A584A0E1C35219FCCE3C09C84531C714
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
FPGA Processor Memory Testbench Output  External Input/Output High Frequency Signal Low Frequency Signal  Copyright 2019-2022 The MathWorks, Inc. Streaming Data from Hardware to Software Detected Signal (LEDs)

BLOCK:
 DataOut; HighFreqIndicatorOut; LowFreqIndicatorOut; rdCtrlOut;AXI4-Stream to Software;DIP Switch;DataIn;DataOut;FPGA;Frame based processing;HighFreqIndicator;LED;Lamp;LowFreqIndicator;Manual Switch;Processor;Processor - Frame based processing;Rate Transition;Reference;Register Channel;Sample based processing;SelectHighFreq;SelectLowFreq;SourceSelector;SubSystem;Task Manager;Vector Scope;dataReadTaskEvent;done;rdCtrlIn 

BLOCKTYPE:
AXI4-Stream to Software;Constant;DIP Switch;Inport;LED;LampBlock;ManualSwitch;ModelReference;Outport;RateTransition;Register Channel;Scope;Task Manager

EXTERNALFILE_REFERENCE:
soc_hwsw_stream_fpga.slx___Model_Block___soc_hwsw_stream_fpga_frame.slx___Model_Block___soc_hwsw_stream_proc.slx___Model_Block___


MODELNAME: soc_image_rotation
PATH: toolbox/soc/socexamples/soc_image_rotation.slx
BLOCKTYPE: AXI4 Random Access Memory;Constant;Ground;IO Data Source;ModelReference;Register Channel;Terminator
BLOCKTYPE_FREQUENCY: 2;1;2;1;1;1;3
CHECKSUM: 57B08146829DD114CDC53A20AA639EDC
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_image_rotation_fpga.slx___Model_Block___
ANNOTATION:
 Random Access of External Memory  Copyright 2019-2023 The MathWorks, Inc. FPGA Memory Region 1 Memory Region 2

BLOCK:
Algorithm Start;Constant;FPGA Algorithm;Ground;Input Read Memory;Output Write Memory;Reference;Register Channel;Terminator


MODELNAME: soc_image_rotation_fpga
PATH: toolbox/soc/socexamples/soc_image_rotation_fpga.slx
BLOCKTYPE_FREQUENCY: 2;2;2;2;4;30;3;34;4;1;5
CHECKSUM: ECFEF657CC1F7819DE1858161B0F9351
PRODUCT: Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 Write one line of image data to Buffer in reverse order  Read one line of image data from Buffer  Simple Dual-port RAM sized to buffer one line of image data  Read one line of image data from external memory as one AXI4 burst  Write the reveresed data to external memory as one AXI4 burst and request next line  Reverse the order of the line data Copyright 2019-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AXI4MasterRead;AXI4MasterRead BusCreator;AXI4MasterRead BusSelector;AXI4MasterReadController;AXI4MasterWrite;AXI4MasterWrite BusCreator;AXI4MasterWrite BusSelector;AXI4MasterWriteController;Buffer;Data Type Conversion;Delay;ImageRotation;Logical Operator;OR;Out;PositiveEdgeDetection;ReadFromBuffer;Reference;ReverseDataOrder;SubSystem;Terminator;WriteToBuffer;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_wr_data;axim_wr_m2s;axim_wr_s2m;data;data_in;data_out;dvalid;dvalid_in;dvalid_out;rdCtrlIn;rdCtrlOut;rdData;rd_addr;rd_aready;rd_avalid;rd_data;rd_data_out;rd_dready;rd_dvalid;rd_dvalid_out;rd_len;ready;request_next_line;start;wrCtrlIn;wrCtrlOut;wrData;wr_addr;wr_complete;wr_data;wr_data_out;wr_done;wr_dvalid;wr_len;wr_ready;wr_valid

BLOCKTYPE:
Bus Creator;Bus Selector;DataTypeConversion;Delay;Demux;Inport;Logic;Outport;S-Function;Simple Dual-port RAM;Terminator


MODELNAME: soc_memory_traffic_generator
PATH: toolbox/soc/socexamples/soc_memory_traffic_generator.slx
BLOCK: Memory Controller;Memory Traffic Generator;Reference
BLOCKTYPE: Memory Controller;Memory Traffic Generator
BLOCKTYPE_FREQUENCY: 1;4
CHECKSUM: 90D6140828DA2BACD2CD6D18D4C17334
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
 Analyze Memory Bandwidth for SoC Design Using Traffic Generators  Copyright 2019 The MathWorks, Inc. TO DISPLAY (READING VIDEO FRAME) FROM CAMERA (WRITING VIDEO FRAME) FPGA ALGORITHM (READING VIDEO FRAME) FPGA ALGORITHM (WRITING VIDEO FRAME)


MODELNAME: soc_motor_behavior
PATH: toolbox/soc/socexamples/soc_motor_behavior.slx
CHECKSUM: EF5CEC9E1A4D2FE551117A104DCBCC22
PRODUCT: Embedded Coder;Fixed-Point Designer;Simscape;Simscape Electrical;Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HW
ANNOTATION:
Continuous To Discrete ADC Count to Current   Mod Two Pi Once Encoder Count To Rotor Position Wrap Neg Pi To Pi Once Rotor Position Delta If detect positive rise in valid, this is a bad sample since encoder index just reset First two velocity calculations are not valid If offset changes, this is a bad sample since the encoder was calibrated to a new value Rotor Position Delta To Velocity Rotor To Electrical Position  Fixed-point implementation which avoids overflow Encoder To Position And Velocity Clarke Transform Converts balanced three-phase quantities into balanced two-phase quantities. The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component. The alpha and beta components are still dependent on time and speed. Delay With Reset D Current Control Delay With Reset Q Current Control DQ Current Control Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Park Transform Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame. Sine Cosine Fixed Point LUT Space Vector Modulation FOC Current Control Over Current Detector Voltage To PWM Compare FOC Encoder Current Loop Discrete To Continuous Enum Data Type Conversion System Inputs Count To Limit Negate Zero To Two Pi Wrap Neg Pi To Pi Once Encoder Calibration Calibrate Encoder Offset Mod Two Pi Once Electrical Velocity To Position Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Detect Change Set Acceleration Ramp Velocity Rotor Velocity To Volts Open Loop Velocity Control Open Loop Velocity Control Disabled Velocity Control Velocity Control Controller Algorithm ADC Current Transducer ADC Current Dyno Coupling Dyno Short Phases Average Resistance Latch On Hi Detect Index Pulse Mod Two Pi Encoder Sensor And Peripheral Models the behavior of a relative quadrature encoder. The rotor angle and rotor velocity inputs are ideal measurements from the motor model. When the motor begins spinning the counter is initialized to zero. Once an index pulse is received, the count value is reset to a value corresponding to a valid rotor position. Hence, after the first index pulse is received, the count returned by the peripheral represents the absolute position of the encoder. Clarke Transform Park Transform Measurements PMSM Clarke Transform Park Transform Measurements PMSM PWM Peripheral And Inverter Motor And Load  Field-Oriented Control of PMSM (Behavioral Model)  Plant  Controller Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ; calibrateEncoder; closedLoop; enableInverter; openLoop;A;ABC;ABC_SVM;ADC;ADC_Count;ADC_Count_To_Current;ADC_Current;ADC_Phase_Currents;ADC_Transducer_Volt_At_Zero_Ampere;ADC_Transducer_Volt_Per_Ampere;AND;AND_Neg;AND_Pos;Abs;Acceleration;Add;Alpha;Alpha_Gain;At_Limit;B;Beta;Beta_Gain;Bias;Bias_After_Index_Found;Bias_Before_Index_Found;Bias_To_Remove;Bus_Creator;Bus_Selector;C;Calibrate_Encoder_Offset;Clarke_Transform;Command_Type;Compare;Constant;Continue_Count;Continuous_To_Discrete;Controlled_Voltage_Source;Controller;Controller_Mode;Cos;Cos_Coefficient;Count;Count_At_Zero_Transducer_Volt;Count_Data_Type;Count_Per_Radian;Count_Per_Transducer_Volt;Count_To_Limit;Current;Current Control;Current_Command;Current_Fixed_Point;Current_Greater_Than_Index;Current_Less_Than_Index;Current_Measured;Current_Sensor;Current_Transducer;D;DC;DQ_Current_Control;D_Command;D_Current;D_Current_Control;D_Voltage;Data_Type_Conversion;Data_Type_Convert;Delay;Demux;Detect_Change;Detect_Index_Pulse;Detect_Over_Current_Error;Detect_Rise;Difference;Direct_Voltage;Discrete_To_Continuous;Duration;Dyno_Coupling;Dyno_Short_Phases_Average_Resistance;E;EP;EV;Electrical Reference;Electrical_Position;Electrical_Reference;Electrical_Velocity;Electrical_Velocity_To_Position;En;En_Inv;Enable;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Calibration;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Count_To_Rotor_Position;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Index_Position;Encoder_Offset;Encoder_Position_Valid_At_Startup;Encoder_Sensor_And_Peripheral;Encoder_To_Position_And_Velocity;Enum_Data_Type;Enum_Data_Type_Conversion;Error;Extract_Lower_Bits;FOC_Current_Control;FOC_Velocity_Encoder;Frequency_To_Voltage;From;Gain;Gmin;Goto;Greater_Or_Equal;Greater_Than;IC;Ideal_Rotational_Mot ion_Sensor;Ideal_Switch;Ideal_Torque_Sensor;In;Index_Found;Inertia;Input_Range;Int32_Data_Type;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Inverter_Enable;Last_Valid_Position_Delta;Latch;Latch_On_Hi;Latch_Target;Less_Than;Limit;Logical Operator;Logical_AND;Logical_OR;Lookup_Tablle;M;Max;Max_Abs_Error;Measurements;Mechanical Rotational Reference;Memory;Merge;Min;Mod;Mod_Two_Pi;Mod_Two_Pi_Once;Mod_X_Two_Pi;Mode_Scheduler;Modulus;Motor_Commands;Motor_Measurements;Motor_On;Mux;NOT;Neg_Pi;Neg_Pi_Div_Two;Negate_Zero_To_Two_Pi;No_Change_Detected;No_Rise_Detected;Normalize;Normalize_Position;Not_Equal;Not_Equal_Zero;Not_Wrapped;Number_Of_Pole_Pairs;OR;Offset;Offset_Fixed_Point;One;Open_Loop_Velocity_Control;Out;Output_Range;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;P;PI;PMSM;PMSM_Load;PS-Simulink Converter;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;PWM_Peripheral_And_Inverter;Park_Transform;Permanent_Magnet_Synchronous_Motor;Phase Voltage;Phase_Current;Phase_Currents;Phase_Splitter;Phase_Voltage;Phase_Voltage_Amplitude;Phase_Voltage_Command;Pi_Div_Two;Plant;Pole_Pair_Gain;Position;Position_At_Zero_Count;Position_At_Zero_Count_Valid;Position_Delta;Position_Difference;Position_Single;Position_Valid;Previous_Greater_Than_Index;Previous_Less_Than_Index;Product;Proportional_Gain;Q;Q_Command;Q_Current;Q_Current_Command;Q_Current_Control;Q_Voltage;R;RT;RV;Ramp_Velocity;Rate_Transition;Reference;Register;Reset;Reset_Count;Rotational_Friction;Rotor_Inertia;Rotor_Position;Rotor_Position_Delta;Rotor_Position_Delta_To_Velocity;Rotor_Position_Per_Count;Rotor_To_Electrical_Position_No_Overflow_Fixpt;Rotor_Velocity;Rotor_Velocity_To_Volts;Sample_Frequency;Sample_Time;Sat;Saturate;Saturate_Magnitude;Saturate_Output;Saturation;Scalar;Scale_To_Two_Pi;Selector;Set_Acceleration;Signal_Builder_Experiments;Signed_Fixpt;Simulink_To_PS;Sin;Sin_Coefficient;Sine_Cosine;Sine_Cosine_LUT;Slope;Solver_Configuration;Space_Vector_Modulation;StandBy;Stop_Count;SubSystem;Subtract;Sum;Switch;Switch_Dir;Switch_Stop;System_Inputs;T;Terminator;Tick_Per_Sec;Transport_Delay;Two_Pi;Unary_Minus;Unsigned_Fixpt;Unsigned_Integer;V;V_Current;V_T;V_Target;Variable_Resistor_A;Variable_Resistor_B;Variable_Resistor_C;Velocity;Velocity Control;Velocity_Command;Velocity_Control;Velocity_Measured;Velocity_Single;Volt;Voltage;Voltage_Bias;Voltage_Fixed_Point;Voltage_To_PWM_Compare;Volts_Per_PWM_Count;W;Wrap;Wrap_Neg_Pi_To_Pi_Once;Wrap_Negative_Direction;Wrap_Positive_Direction;Wrapped;X;Y;Zero;Zero_During_Calibration;commandType;enableOverCurrentDetect;encoderIndexFound;encoderOffsetFound;error;mode;motorOn;overCurrentDurationTicks;overCurrentError;overCurrentLimit;phaseCurrentA;phaseCurrentB;positionDelta;rotorVelocity;rotorVelocityMeasured

BLOCKTYPE:
Abs;Bitwise Operator;BusCreator;BusSelector;Compare To Zero;Constant;Controlled Voltage Source;Convert to enumerated data type;Current Sensor (Three-Phase);DataTypeConversion;Delay;Demux;Detect Change;Electrical Reference;EnablePort;From;Gain;Goto;Ideal Rotational Motion Sensor;Ideal Torque Sensor;Inertia;InitialCondition;Inport;InportShadow;Logic;Lookup_n-D;Math;Mechanical Rotational Reference;Memory;Merge;MinMax;Mux;Outport;PMIOPort;PMSM;PS-Simulink Converter;Phase Splitter;Product;RateTransition;RelationalOperator;Resistor;Rotational Friction;Rotor position delta to velocity;S-Function;Saturate;Saturation Dynamic;Selector;SignalEditor;SignalSpecification;Simulink-PS Converter;Sine and Cosine;Solver Configuration;Sum;Switch;Terminator;TransportDelay;Trigonometry;UnaryMinus;Variable Resistor

BLOCKTYPE_FREQUENCY:
3;2;5;5;1;74;3;1;2;28;44;10;1;4;4;1;33;1;2;2;3;1;139;24;22;1;5;2;2;1;2;7;122;23;2;8;2;29;18;21;2;2;1;3;7;3;12;1;10;7;1;1;51;30;11;1;3;4;3


MODELNAME: soc_motor_fpga
PATH: toolbox/soc/socexamples/soc_motor_fpga.slx
BLOCKTYPE_FREQUENCY: 1;2;39;15;31;5;1;21;117;19;7;4;4;81;25;9;1;2;6;4;4;5;1;38;14;6;1;4
CHECKSUM: 91DC4053B4338AAA89F928E73452C789
PRODUCT: Embedded Coder;Fixed-Point Designer;Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HW
ANNOTATION:
ADC Count to Current Mod Two Pi Once Encoder Count To Rotor Position Wrap Neg Pi To Pi Once Rotor Position Delta If detect positive rise in valid, this is a bad sample since encoder index just reset First two velocity calculations are not valid If offset changes, this is a bad sample since the encoder was calibrated to a new value Rotor Position Delta To Velocity Rotor To Electrical Position  Fixed-point implementation which avoids overflow Encoder To Position And Velocity Clarke Transform Converts balanced three-phase quantities into balanced two-phase quantities. The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component. The alpha and beta components are still dependent on time and speed. Delay With Reset D Current Control Delay With Reset Q Current Control DQ Current Control Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Park Transform Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame. Sine Cosine Fixed Point LUT Space Vector Modulation FOC Current Control Clarke Transform Converts balanced three-phase quantities into balanced two-phase quantities. The A and B phases are converted to the direct axis (alpha) component and the quadrature axis (beta) component. The alpha and beta components are still dependent on time and speed. D Current Control Q Current Control DQ Current Control Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Park Transform Converts balanced two-phase orthogonal stationary system to an orthogonal rotating reference frame. Space Vector Modulation FOC Current Control  FOC Encoder Current Loop current control floating-point algorithm Over Current Detector Voltage To PWM Compare FOC Encoder Current Loop Field-Oriented Control of Velocity Zynq HDL Specification Copyright 2015-20120 The MathWorks, Inc.  Field-Oriented Control of PMSM (FPGA Model)  Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;A;ABC;ABC_SVM;ADC_Count_To_Current;ADC_Phase_Currents;AND;AXI_Current_Command;AXI_Electrical_Position;AXI_Enable_Closed_Loop;AXI_Enable_Inverter;AXI_Encoder_Index_Found;AXI_Encoder_Offset;AXI_Overcurrent_Error;AXI_Phase_Current_A;AXI_Phase_Current_B;AXI_Phase_Voltage_A;AXI_Phase_Voltage_B;AXI_Phase_Voltage_C;AXI_Rotor_Position;AXI_Rotor_Velocity;Abs;Add;Alpha;Alpha_Gain;B;Beta;Beta_Gain;Bias;Bias_To_Remove;Clarke_Transform;Compare;Constant;Cos;Cos_Coefficient;Count;Current;Current_Command;Current_Measured;D;DQ_Current_Control;D_Command;D_Current;D_Current_Control;D_Voltage;Data Type Conversion;Data_Type_Conversion;Data_Type_Convert;Delay;Demux;Detect_Change;Detect_Over_Current_Error;Detect_Rise;E;Electrical_Position;En_Inv;Enable_Current_Control;Enable_Inverter_In;Enable_Inverter_Out;Enable_Over_Current_Detection;Encoder_A_Leads_B;Encoder_Count;Encoder_Count_Per_Revolution;Encoder_Count_To_Rotor_Position;Encoder_Index_Found;Encoder_Index_Found_Out;Encoder_Offset;Encoder_To_Position_And_Velocity;Error;Extract_Lower_Bits;FOC_Current_Control;FOC_Velocity_Encoder;FPGA;FloatingPoint_FOC_Control;Gain;Greater_Than;IP_ADC_A_Count;IP_ADC_B_Count;IP_Encoder_A_Leads_B;IP_Encoder_Count;IP_Encoder_Count_Per_Revolution;IP_Encoder_Index_Found;IP_Inverter_Enable;IP_PWM_A_Compare;IP_PWM_B_Compare;IP_PWM_C_Compare;IP_PWM_Counter_Max;IP_PWM_Dead_Time_Count;In;Index_Found;Input_Range;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Last_Valid_Position_Delta;Less_Than;Logical Operator;Logical_AND;Max;Min;Mod_Two_Pi_Once;Mod_X_Two_Pi;Motor_On;Mux;NOT;Neg_Pi;No_Change_Detected;No_Rise_Detected;Normalize;Normalize_Position;Not_Equal;Offset;Out;Output_Range;Over_Current_Detector;Over_Current_Duration;Over_Current_Limit;P;PI;PWM_Compare;PWM_Counter_Max;PWM_Dead_Time_Count;Park_Transform;Phase_Current;Phase_Currents;Phase_Voltage;Phase_Voltage_Command;Pole_Pair_Gain;Position;Position_At_Zero_Count;Position_Delta;Product;Proportional_Gain;Q;Q_Command;Q_Current;Q_Current_Control;Q_Voltage;R;Reference;Register;Reset;Rotor_Position;Rotor_Position_Delta;Rotor_Position_Delta_To_Velocity;Rotor_Position_Per_Count;Rotor_To_Electrical_Position_No_Overflow_Fixpt;Rotor_Velocity;Sample_Time;Sat;Saturate;Saturate_Magnitude;Saturate_Output;Saturation;Scalar;Scale_To_Two_Pi;Signed_Fixpt;Sin;Sin_Coefficient;Sine_Cosine;Sine_Cosine_LUT;Slope;Space_Vector_Modulation;SubSystem;Subtract;Switch;Terminator;Tick_Per_Sec;Trigonometric Function;Two_Pi;Unary_Minus;Unsigned_Fixpt;Unsigned_Integer;Velocity;Voltage;Voltage_To_PWM_Compare;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Zero;enableOverCurrentDetect;error;overCurrentDurationTicks;overCurrentLimit;phaseCurrentA;phaseCurrentB;positionDelta;rotorVelocity

BLOCKTYPE:
Abs;Bitwise Operator;Constant;DataTypeConversion;Delay;Demux;Detect Change;Gain;Inport;InportShadow;Logic;MinMax;Mux;Outport;Product;RelationalOperator;Rotor position delta to velocity;S-Function;Saturate;Saturation Dynamic;Selector;SignalSpecification;Sine and Cosine;Sum;Switch;Terminator;Trigonometry;UnaryMinus


MODELNAME: soc_motor_proc
PATH: toolbox/soc/socexamples/soc_motor_proc.slx
BLOCKTYPE_FREQUENCY: 2;1;1;28;1;9;15;2;4;2;1;9;1;73;4;7;2;1;1;1;3;1;76;6;7;7;8;1;1;1;5;1;18;12;1;1;5;1;2
CHECKSUM: 2448A6582D787C108B88FD27AFC4B563
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset;Stateflow
PRODUCT_BASECODE: HW
ANNOTATION:
Enum Data Type Conversion Count To Limit Negate Zero To Two Pi Wrap Neg Pi To Pi Once Encoder Calibration Calibrate Encoder Offset Mod Two Pi Once Electrical Velocity To Position Inverse Clarke Transform Converts direct axis (alpha) component and the quadrature axis (beta) component to balanced three-phase quantities The alpha and beta components are dependent on time and speed. Inverse Park Transform Converts orthogonal rotating reference frame (dq) to two-phase orthogonal stationary reference frame (alpha, beta) Detect Change Set Acceleration Ramp Velocity Rotor Velocity To Volts Open Loop Velocity Control Open Loop Velocity Control Disabled Velocity Control Velocity Control Copyright 2022 The MathWorks, Inc.  Field-Oriented Control of PMSM (Processor Model)

BLOCK:
 Demux ; SFunction ; Terminator ; calibrateEncoder; closedLoop; enableInverter; openLoop;A;ABC;AND_Neg;AND_Pos;AXI4LiteRead;AXI4LiteWrite;AXI4Lite_Read_AXI_Electrical_Position_rd;AXI4Lite_Read_AXI_Encoder_Index_Found_rd;AXI4Lite_Read_AXI_Overcurrent_Error_rd;AXI4Lite_Read_AXI_Phase_Current_A_rd;AXI4Lite_Read_AXI_Phase_Current_B_rd;AXI4Lite_Read_AXI_Rotor_Position_rd;AXI4Lite_Read_AXI_Rotor_Velocity_rd;AXI4Reset;AXI4ResetModelSource;AXI_Current_Command;AXI_Current_Command_wr;AXI_Electrical_Position;AXI_Electrical_Position_rd;AXI_Enable_Closed_Loop;AXI_Enable_Closed_Loop_wr;AXI_Enable_Inverter;AXI_Enable_Inverter_wr;AXI_Encoder_Index_Found;AXI_Encoder_Index_Found_rd;AXI_Encoder_Offset;AXI_Encoder_Offset_wr;AXI_Interface;AXI_Overcurrent_Error;AXI_Overcurrent_Error_rd;AXI_Phase_Current_A;AXI_Phase_Current_A_rd;AXI_Phase_Current_B;AXI_Phase_Current_B_rd;AXI_Phase_Voltage_A;AXI_Phase_Voltage_A_wr;AXI_Phase_Voltage_B;AXI_Phase_Voltage_B_wr;AXI_Phase_Voltage_C;AXI_Phase_Voltage_C_wr;AXI_Rotor_Position;AXI_Rotor_Position_rd;AXI_Rotor_Velocity;AXI_Rotor_Velocity_rd;Abs;Acceleration;Add;Alpha;At_Limit;Beta;Bus Creator;Calibrate_Encoder_Offset;Command_Mode;Constant;Continue_Count;Cos_Coefficient;Count_To_Limit;Current;Current_Fixed_Point;D;Data_Type_Int;Delay;Demux;Detect_Change;Difference;Direct_Voltage;Duration;EP;EV;Electrical_Velocity;Electrical_Velocity_To_Position;Enable;Encoder_Calibration;Enum_Data_Type;Enum_Data_Type_Conversion;Error;Frequency_To_Voltage;From;Gain;Goto;Greater_Or_Equal;Greater_Than;In;Input_Range;Input_Source;Int32_Data_Type;Integral_Gain;Inverse_Clarke_Transform;Inverse_Park_Transform;Latch_Target;Less_Than;Limit;Logical_OR;Manual_Switch;Max_Abs_Error;Merge;Mod_Two_Pi_Once;Mod_X_Two_Pi;Mode_Scheduler;Model Header;Motor_On_Switch;Mux;NOT;Neg_Pi;Negate_Zero_To_Two_Pi;Not_Equal;Not_Equal_Zero;Number_Of_Pole_Pairs;OR;Offset_Fixed_Point;Open_Loop_Velocity_Control;Out;Output_Range;PI;Phase Voltage;Phase_Voltage;Phase_Voltage_Amplitude;Position;Position_At_Zero_Count;Position_At_Zero_Count_Valid;Position_Single;Position_Valid;Product;Proportional_Gain;Q;Q_Current_Command;RV;Ramp_Velocity;Reference;Register Read;Register Write;Reset;Reset_Count;Rotor_Position;Rotor_Velocity;Rotor_Velocity_To_Volts;Sample_Frequency;Sample_Time;Saturate_Magnitude;Saturate_Output;Select_Source;Set_Acceleration;Signal_Builder_Experiments;Sin_Coefficient;Sine_Cosine;Sine_Wave;StandBy;Stop_Count;SubSystem;Subtract;Sum;Switch;Switch_Dir;Switch_Stop;System Terminate;System_Input;Terminator;Two_Pi;Unary_Minus;V;V_Current;V_Target;Velocity_Command;Velocity_Control;Velocity_Measured;Velocity_Single;Voltage_Bias;Voltage_Fixed_Point;Wrap;Wrap_Neg_Pi_To_Pi_Once;X;Y;Zero;Zero_During_Calibration;commandType;encoderIndexFound;encoderOffsetFound;error;mode;motorOn

BLOCKTYPE:
Abs;BusCreator;Compare To Zero;Constant;Convert to enumerated data type;DataTypeConversion;Delay;Demux;EnablePort;Enumerated Constant;From;Gain;Goto;Inport;InportShadow;Logic;ManualSwitch;Merge;Model Header;Model Source;MultiPortSwitch;Mux;Outport;Product;Register Read;Register Write;RelationalOperator;S-Function;Saturation Dynamic;SignalEditor;SignalSpecification;Sine Wave;Sum;Switch;System Start;System Terminate;Terminator;Trigonometry;UnaryMinus


MODELNAME: soc_motor_top
PATH: toolbox/soc/socexamples/soc_motor_top.slx
BLOCKTYPE_FREQUENCY: 7;6;19;3;2;8;3;4;10;2;2;3;1;27;8;8;1;5;2;2;2;2;27;23;2;8;2;10;5;1;6;2;2;2;10;7;1;10;6;1;2;1;2;3
CHECKSUM: 681C81576F95FC9A3C847440887F48EB
PRODUCT: Embedded Coder;Simscape;Simscape Electrical;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_motor_fpga.slx___Model_Block___soc_motor_proc.slx___Model_Block___
ANNOTATION:
Continuous To Discrete Discrete To Continuous ADC Current Transducer ADC Current Dyno Coupling Dyno Short Phases Average Resistance Latch On Hi Detect Index Pulse Mod Two Pi Encoder Sensor And Peripheral Models the behavior of a relative quadrature encoder. The rotor angle and rotor velocity inputs are ideal measurements from the motor model. When the motor begins spinning the counter is initialized to zero. Once an index pulse is received, the count value is reset to a value corresponding to a valid rotor position. Hence, after the first index pulse is received, the count returned by the peripheral represents the absolute position of the encoder. Clarke Transform Park Transform Measurements PMSM Clarke Transform Park Transform Measurements PMSM PWM Peripheral And Inverter Motor And Load  Field-Oriented Control of PMSM (SoC Model)  FPGA  Copyright 2022 The MathWorks, Inc.  AXI Interface  Plant  Processor

BLOCK:
 ;A;ABC;ADC;ADC_Count;ADC_Current;ADC_Transducer_Volt_At_Zero_Ampere;ADC_Transducer_Volt_Per_Ampere;AND;Add;Alpha;Alpha_Gain;B;Beta;Beta_Gain;Bias_After_Index_Found;Bias_Before_Index_Found;Bus Creator;Bus Selector;Bus_Creator;Bus_Selector;C;Clarke_Transform;Constant;Continuous_To_Discrete;Controlled_Voltage_Source;Controller;Cos_Coefficient;Count;Count_At_Zero_Transducer_Volt;Count_Data_Type;Count_Per_Radian;Count_Per_Transducer_Volt;Current;Current_Greater_Than_Index;Current_Less_Than_Index;Current_Sensor;Current_Transducer;D;DC;Data Type Conversion;Data_Type_Conversion;Demux;Detect_Index_Pulse;Discrete_To_Continuous;Dyno_Coupling;Dyno_Short_Phases_Average_Resistance;Electrical Reference;Electrical_Reference;En;Enable;Encoder_Count;Encoder_Index_Found;Encoder_Index_Position;Encoder_Position_Valid_At_Startup;Encoder_Sensor_And_Peripheral;Gain;Gmin;IC;Ideal_Rotational_Mot ion_Sensor;Ideal_Switch;Ideal_Torque_Sensor;Index_Found;Inertia;Inverter_Enable;Latch;Latch_On_Hi;Logical_OR;Lookup_Tablle;M;Measurements;Mechanical Rotational Reference;Memory;Mod;Mod_Two_Pi;Mod_X_Two_Pi;Model;Modulus;Motor_And_Load;Motor_Commands;Motor_Measurements;Mux;Neg_Pi_Div_Two;Not_Wrapped;OR;One;Out;PMSM;PMSM_Load;PS-Simulink Converter;PWM_Compare;PWM_Peripheral_And_Inverter;Park_Transform;Permanent_Magnet_Synchronous_Motor;Phase_Splitter;Pi_Div_Two;Position;Position_Difference;Previous_Greater_Than_Index;Previous_Less_Than_Index;Product;Q;R;Rate_Transition;Reference;Register Channel;Rotational_Friction;Rotor_Inertia;Rotor_Position;Saturation;Selector;Simulink_To_PS;Sin_Coefficient;Sine_Cosine;Solver_Configuration;SubSystem;Switch;T;Task Manager;Terminator;Transport_Delay;Two_Pi;V;V_T;Variable_Resistor_A;Variable_Resistor_B;Variable_Resistor_C;Volt;Volts_Per_PWM_Count;W;Wrap_Negative_Direction;Wrap_Positive_Direction;Wrapped;X;Zero;inverterEnable

BLOCKTYPE:
BusCreator;BusSelector;Constant;Controlled Voltage Source;Current Sensor (Three-Phase);DataTypeConversion;Demux;Electrical Reference;Gain;Ideal Rotational Motion Sensor;Ideal Torque Sensor;Inertia;InitialCondition;Inport;InportShadow;Logic;Lookup_n-D;Math;Mechanical Rotational Reference;Memory;ModelReference;Mux;Outport;PMIOPort;PMSM;PS-Simulink Converter;Phase Splitter;Product;RateTransition;Register Channel;RelationalOperator;Resistor;Rotational Friction;Saturate;Selector;Simulink-PS Converter;Solver Configuration;Sum;Switch;Task Manager;Terminator;TransportDelay;Trigonometry;Variable Resistor


MODELNAME: soc_rf_playback_ref
PATH: toolbox/soc/socexamples/soc_rf_playback_ref.slx
BLOCKTYPE: DataTypeConversion;Extract Bits;Inport;Outport;Stream Read;Terminator;TriggerPort
BLOCKTYPE_FREQUENCY: 2;2;4;8;1;1;1
CHECKSUM: C353ED590DE63D58C23AABDB94D61BC6
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
NOTE: Received data is packed into 32 bits therefore I/Q data is extracted. Copyright 2020 The MathWorks, Inc.

BLOCK:
32bit_data;Data In;Data Type Conversion;DataTask;Done;Extract Bits;Extract IQ data;I;Processor Algorithm;Q;Reference;Stream Read;SubSystem;Terminator;Trigger


MODELNAME: soc_rfcapture
PATH: toolbox/soc/socexamples/soc_rfcapture.slx
BLOCKTYPE_FREQUENCY: 1;1;2;2;5;1;2;8;1;1;1
CHECKSUM: 375B158725248E432F2079B1F52D5902
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_rfcapture_fpga___Model_Block___soc_rfcapture_proc___Model_Block___
ANNOTATION:
NOTE: Received data is packed into 32 bits therefore I/Q data is extracted.  RF Capture Copyright 2019-2022 The MathWorks, Inc. Memory Processor FPGA RF I/O Testbench Output

BLOCK:
32bit_data;AD9361Rx;ARM;AXI4-Stream to Software;Data Type Conversion;DataOut;Extract Bits;Extract IQ data;FPGA;FPGA Receiver;I;In-Phase;LED;Processor Algorithm ;Q;Quadrature;Rate Transition;Reference;SubSystem;Task Manager;chCtrlIn;chCtrlOut;chData;data;dataDropped_LED;dataIn;dataTask;done

BLOCKTYPE:
AD9361 Rx Playback;AXI4-Stream to Software;DataTypeConversion;Extract Bits;Inport;LED;ModelReference;Outport;RateTransition;Scope;Task Manager


MODELNAME: soc_rfcapture_fpga
PATH: toolbox/soc/socexamples/soc_rfcapture_fpga.slx
ANNOTATION: LED will light up when data is dropped. Copyright 2019 The MathWorks, Inc.
BLOCKTYPE: Assertion;Bus Creator;Bus Selector;Constant;Delay;Inport;Outport;Terminator
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;4;7;1
CHECKSUM: B1537B780D26CE7E80DFBE94221E2EE3
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
Assertion;Bus Creator;Bus Selector;Constant;Delay;FPGA Data Capture;Reference;SubSystem;Terminator;chCtrlIn;chCtrlOut;chData;dataDropped;dataDropped_LED;dataIn;dataOut;readyFromDown;readyToUp;validOut


MODELNAME: soc_rfcapture_proc
PATH: toolbox/soc/socexamples/soc_rfcapture_proc.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;3;4;1;1;1;1
CHECKSUM: E050F5188ED09801712B89124438CA37
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
BLOCK:
Asynchronous Task Specification;DataOut;Event Listener;Initialize Function ;Processor Algorithm Wrapper;Reference;Stream Read;SubSystem;Terminator ;Trigger;Zynq and FMCOMMS2/3/4 Receiver;data;dataTask;done

BLOCKTYPE:
AsynchronousTaskSpecification;EventListener;Inport;Outport;Stream Read;Terminator;TriggerPort;comm.internal.SDRRxZC706FMC234RFSL


MODELNAME: soc_signal_detection
PATH: toolbox/soc/socexamples/soc_signal_detection.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc. Testbench Output Signal Detection Detected Signal (LEDs)
BLOCKTYPE_FREQUENCY: 2;1;2;2;1;4;1;1;1;6
CHECKSUM: CFAA1F1A7934481C8C1ABCFDFE42E110
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_hwsw_stream_proc.slx___Model_Block___
BLOCK:
DataIn;DataOut;HighFreq;IO Data Sink;IO Data Source;Lamp;LowFreq;Model;Processor Algorithm;RT;Reference;SubSystem;Task Manager;Terminator;Vector Scope;dataReadTaskEvent;done

BLOCKTYPE:
IO Data Sink;IO Data Source;Inport;LampBlock;ModelReference;Outport;RateTransition;Scope;Task Manager;Terminator


MODELNAME: soc_swhw_stream_fpga
PATH: toolbox/soc/socexamples/soc_swhw_stream_fpga.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE: Bus Creator;Bus Selector;Demux;Discrete FIR Filter;Inport;Outport;S-Function;Terminator
BLOCKTYPE_FREQUENCY: 1;1;3;2;11;17;3;4
CHECKSUM: F57E13909140D6CFD201C9C40C1A2C40
PRODUCT: DSP HDL Toolbox;Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
 Demux ; SFunction ; Terminator ;High Pass Filter;Low Pass Filter;MATLAB Function;Reference;SoC Bus Creator;SoC Bus Selector;SubSystem;Terminator;data;highFreqLED;highFreqReg;lowFreqLED;lowFreqReg;sineWaveFilter;streamEnable;tdata;tready;tvalid;valid;validDropLED;validDropReg;y


MODELNAME: soc_swhw_stream_proc
PATH: toolbox/soc/socexamples/soc_swhw_stream_proc.slx
BLOCKTYPE_FREQUENCY: 1;4;1;1;1;9;1;11;3;1;1;1;1;1;2;2
CHECKSUM: 9164BD41C5A52FF5F591507EA6C41CF2
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Actual frequency = round(FrameSize*SourceSTime*1e5)/(FrameSize*SourceSTime) Actual frequency = round(FrameSize*SourceSTime*1e6)/(FrameSize*SourceSTime) AXI Write AXI Read Copyright 2020 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Busy Wait;Constant;CountToNumBuffers;Counter Limited;Delay;Enable;Equal;NOT;Out;Priming;Reference;Register Read;Register Write;SourceSelector;Stream Write;SubSystem;Switch;Terminator;Trigger;Writer;data;dataOut;done;highFreq;highFreqReg;lowFreq;lowFreqReg;sendCmd;sineWave;streamEnable;validDrop;validDropReg;write_fcn;~100KHz;~1MHz

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;Counter Limited;Delay;EnablePort;Inport;Logic;Outport;Register Read;Register Write;RelationalOperator;Stream Write;Switch;Terminator;TriggerPort;soc.blocks.BusyWait


MODELNAME: soc_swhw_stream_top
PATH: toolbox/soc/socexamples/soc_swhw_stream_top.slx
BLOCKTYPE_FREQUENCY: 2;3;6;1;3;1;2;2;1;1;1;1
CHECKSUM: A98567D977CC07D7D2CBE3035F337D2D
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_swhw_stream_fpga.slx___Model_Block___soc_swhw_stream_proc.slx___Model_Block___
ANNOTATION:
 Copyright 2020-2022 The MathWorks, Inc. Low Frequency Signal  Streaming Data from Software to Hardware Detected Signal (LEDs) High Frequency Signal External Input/Output FPGA Memory Processor Testbench Input

BLOCK:
Constant;Display;FPGA;LED;Lamp;Manual Switch;Processor;Processor - Frame based processing;Rate Transition;Reference;Register Channel;Software to AXI4-Stream;SourceSelector;SubSystem;Task Manager;WriteTaskEvent;dataOut;done;highFreqReg;lowFreqReg;streamEnable;validDropReg

BLOCKTYPE:
Constant;Display;Inport;LED;LampBlock;ManualSwitch;ModelReference;Outport;RateTransition;Register Channel;Software to AXI4-Stream;Task Manager


MODELNAME: soc_task_execution
PATH: toolbox/soc/socexamples/soc_task_execution.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc. Task Execution Case 1
BLOCKTYPE: IO Data Source;Inport;ModelReference;Outport;RateTransition;Scope;Task Manager;Terminator
BLOCKTYPE_FREQUENCY: 2;5;1;7;2;1;1;3
CHECKSUM: A695DD9D196E9477882360624BD446F1
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_task_execution_proc.slx___Model_Block___
BLOCK:
DataIn;DataOut;HF;HighFreqIndicator;IO Data Source;In;LF;LowFreqIndicator;Model;Out;Processor Algorithm;RF Data Source;RT;Rate Transition;Reference;SamplesDroppedIn;SubSystem;Task Manager;Terminator;Test Data;Vector Scope;Viewer;dataTask;done


MODELNAME: soc_task_execution_proc
PATH: toolbox/soc/socexamples/soc_task_execution_proc.slx
BLOCKTYPE_FREQUENCY: 2;1;2;3;2;12;2;19;1;2;1;1;1;2
CHECKSUM: 59856755E11B4D94E534593CADF09882
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
NOTE: BusyWait blocks are inserted to match task duration on hardware  Copyright 2019 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Busy Wait;Cast;Compare To Constant;Data Type Conversion;DataIn;DataOut;DataTask;High Pass Filter;High Pass Filter fc = 3KHz;HighFreqIndicator;In;Low Pass Filter;Low Pass Filter fc = 3KHz;LowFreqIndicator;Max;Out;Processor Algorithm;Processor Algorithm Wrapper ;Reference;Register Read;Register Write;SamplesDroppedIn;SamplesDroppedOut;Scale Filter Output;Scale Filter Outputs;Shift Arithmetic;Stream Read;SubSystem;Terminator;Threshold;Trigger;dataIn;dataOut;done

BLOCKTYPE:
ArithShift;AsynchronousTaskSpecification;Compare To Constant;DataTypeConversion;DiscreteFir;Inport;MinMax;Outport;Register Read;Register Write;Stream Read;Terminator;TriggerPort;soc.blocks.BusyWait


MODELNAME: soc_task_execution_step2
PATH: toolbox/soc/socexamples/soc_task_execution_step2.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc. Task Execution Case 2
BLOCKTYPE_FREQUENCY: 1;7;1;1;2;8;1;11;2;2;1;1;2;8;1;1;4;1
CHECKSUM: 558873284608059F4293C30ACB436D1D
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_task_execution_step2_ref.slx___Model_Block___
BLOCK:
Abs;Add;Constant;Data Source;Data Type Conversion;Duration;From File;Gain;In;Intensity;Max;Mean;Min;Model;Motion Energy;Out;Product;Random Number;Reference;Relational Operator;Reshape;SAD;SD;Saturation Dynamic;SubSystem;Subsystem;Sum;Sum of Elements;Switch;Task Duration Estimation;Task Manager;Terminator;Threshold;Unit Delay

BLOCKTYPE:
Abs;Constant;DataTypeConversion;FromFile;Gain;Inport;ModelReference;Outport;Product;RandomNumber;RelationalOperator;Reshape;Saturation Dynamic;Sum;Switch;Task Manager;Terminator;UnitDelay


MODELNAME: soc_task_execution_step2_ref
PATH: toolbox/soc/socexamples/soc_task_execution_step2_ref.slx
ANNOTATION: Copyright 2019 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;3;1;4;14;1;2;2;4;1;2;3
CHECKSUM: E85689FE04567A6E1C7A897A1FB059EF
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
 Cnt;Abs;Algorithm;Combine Counts;Constant;Enable;Frame Counter;In;Intensity;Last;Main Algorithm;Motion Energy;Out;Reference;Relational Operator;Reshape;SAD;Selector;SubSystem;Sum;Sum of Elements;Terminator;Threshold;UDP Write;Unit Delay

BLOCKTYPE:
Abs;Concatenate;Constant;EnablePort;Inport;Outport;RelationalOperator;Reshape;Selector;Sum;Terminator;UDP Write;UnitDelay


MODELNAME: soc_video_flipping_fpga
PATH: toolbox/soc/socexamples/soc_video_flipping_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;3;2;3;1;5;3;5;4;23;38;3;4;2
CHECKSUM: A94EDCDA77DC8275CCA914FB43C067BC
PRODUCT: Embedded Coder;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
ANNOTATION:
Passthrough as placeholder Passthrough as placeholder  Balance 1 cycle delay from AXI4-Master Write Controller block  AXI Write to Memory AXI Read from Memory Debug logic  EOF  Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AXI Read FIFO;AXI Write FIFO;AXI write FIFO full;AXI4-Master Read Controller;AXI4-Master Write Controller;Assertion;Bit Slice;Bus Selector;Constant;Data Type Conversion;Delay;FIFOReady;From;Goto;MATLAB Function;Out;Placeholder Algorithm ;Reference;SoC Bus Creator;SubSystem;Terminator;Video Stream Connector;VideoFlipping;ctrl;ctrlIn;ctrlOut;errFrameDrop;hEnd;hStart;hdmiDataIn;hdmiDataOut;hdmiInputReady;hdmiOutputReady;rdCtrlIn;rdCtrlOut;rdData;rd_addr;rd_aready;rd_avalid;rd_dready;rd_dvalid;rd_len;rd_start;rd_valid_debug;rfifo_ready;rfifo_ready_debug;start;vEnd;vStart;valid;wfifo_ready;wfifo_ready_debug;wrCtrlIn;wrCtrlOut;wrDDR;wrData;wrValidIn;wrValidOut;wr_addr;wr_len;wr_valid;wr_valid_debug

BLOCKTYPE:
Assertion;Bit Slice;Bus Creator;BusSelector;Constant;DataTypeConversion;Delay;Demux;From;Goto;Inport;Outport;S-Function;Terminator;Video Stream Connector


MODELNAME: soc_video_flipping_top
PATH: toolbox/soc/socexamples/soc_video_flipping_top.slx
BLOCK: AXI4 Random Access Memory;Contention Read;Contention Write;FPGA;HDMI Rx;HDMI Tx;LED;Reference
BLOCKTYPE: AXI4 Random Access Memory;HDMI Rx;HDMI Tx;LED;Memory Traffic Generator;ModelReference
BLOCKTYPE_FREQUENCY: 1;1;1;1;2;1
CHECKSUM: A68A1D505EFD38F418A93AB13481B417
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: HW
EXTERNALFILE_REFERENCE: soc_video_flipping_fpga.slx___Model_Block___
ANNOTATION:
 Vertical Video Flipping Using External Memory Copyright 2020 The MathWorks, Inc. The model runs 480p by default. If you want to change the resolution, run one of these commands: soc_video_flipping_set_parameters(480p) soc_video_flipping_set_parameters(720p) soc_video_flipping_set_parameters(1080p)  Input  Output  FPGA External Memory


MODELNAME: soc_analyze_FIR_tb
PATH: toolbox/soc/socexamples/complexity/examples/FIR/soc_analyze_FIR_tb.slx
ANNOTATION: Analyze FIR Filter implementations for arithmetic operators Copyright 2019 The MathWorks, Inc.
BLOCKTYPE: Chirp;Concatenate;Constant;DiscreteFir;Inport;Outport;Product;Scope;SpectrumAnalyzer;Sum;UnitDelay
BLOCKTYPE_FREQUENCY: 1;2;6;2;13;3;15;2;2;17;17
CHECKSUM: 93FECDD62EDFA6F611D017FAFFCE418B
PRODUCT: DSP System Toolbox;Simulink;SoC Blockset
PRODUCT_BASECODE: HW
BLOCK:
BodyRSum;BodySumL;BodySumR;Chirp;FIR_Ref;FootSumR;HeadSumL;HeadSumR;Product;Reference;Spectrum Analyzer;SubSystem;Symmetric_FIR;Time Scope;Transposed_FIR;Unit Delay;Vector Concatenate;coef_;coef_1_in;coef_2_in;coef_3_in;coef_4_in;coef_5_in;data_in;data_out


MODELNAME: A4SSourceDUT
PATH: toolbox/soc/supportpackages/sdk/testmodels/A4SSourceDUT.slx
BLOCKTYPE_FREQUENCY: 1;1;1;4;2;3;3;8;7;2;14;3;2
CHECKSUM: E7C4C24C49C1BE31B5521D1EC0E9A853
PRODUCT: MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
AND;BufferLength;Bus Creator;Bus Selector;Control;Counter;Data Type Conversion;Delay;In;Logical Operator;Out;Pattern;Reference;Relational Operator;SubSystem;Subsystem;Switch;Tlast;Tlast_generation;Valid;ctrlBusIn;data;data_gen;full;ready;sample counter;selector;start;tlast

BLOCKTYPE:
A4S FPGA Data Source;Bus Creator;Bus Selector;Constant;DataTypeConversion;Delay;HDL Counter;Inport;Logic;Lookup_n-D;Outport;RelationalOperator;Switch


MODELNAME: mSoCRamp
PATH: toolbox/soc/supportpackages/sdk/testmodels/mSoCRamp.slx
BLOCKTYPE_FREQUENCY: 5;1;1;2;7;2;1;1;2
CHECKSUM: 3E4864AAFAE751E9FE1C064C851D19B7
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: mSoCRamp_arm.slx___Model_Block___mSoCRamp_fpga.slx___Model_Block___
BLOCK:
DataIn;DataOut;DataTask;FPGA;Mem Channel;Mem Controller;Model;Processor;Rate Transition;Reference;Register Channel;SamplesDropped;SamplesDroppedIn;SamplesDroppedOut;StreamEnable;SubSystem;Task Manager;Terminator;done;streamEnable;wrCtrlIn;wrCtrlOut;wrData

BLOCKTYPE:
Inport;Memory Channel;Memory Controller;ModelReference;Outport;RateTransition;Register Channel;Task Manager;Terminator


MODELNAME: mSoCRamp_arm
PATH: toolbox/soc/supportpackages/sdk/testmodels/mSoCRamp_arm.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;2;6;2;9;1;1;1;1
CHECKSUM: EE0FA88EA5C1751780F280174E50DC27
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Asynchronous Task Specification;Control;Data Processing;DataIn;DataOut;DataTask;Enable;Event Listener;Gain;MATLAB System;Processor User Logic;Reference;Register Read;Register Write;SamplesDroppedIn;SamplesDroppedOut;Stream Read;StreamEnable;SubSystem;Trigger;dataIn;dataOut;done;enable

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;EnablePort;EventListener;Gain;Inport;MATLABSystem;Outport;Register Read;Register Write;Stream Read;TriggerPort


MODELNAME: mSoCRamp_fpga
PATH: toolbox/soc/supportpackages/sdk/testmodels/mSoCRamp_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;1;2;7;1;9
CHECKSUM: DD0820F4E302EE95677C19DD1B59C389
PRODUCT: Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
AND;Bus Creator;Bus Selector;Compare To Constant;Constant;Control;Counter;Data Type Conversion;HDL Counter;In;Out;Reference;SamplesDropped;SubSystem;Subsystem;Test Source;Valid;ctrlBusIn;data;data_gen;ready;start;streamEnable

BLOCKTYPE:
A4S FPGA Data Source;Bus Creator;Bus Selector;Compare To Constant;Constant;DataTypeConversion;HDL Counter;Inport;Logic;Outport


MODELNAME: msoc_image_rotation_noAlgo
PATH: toolbox/soc/supportpackages/sdk/testmodels/msoc_image_rotation_noAlgo.slx
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;1;1;2
CHECKSUM: ED51B9A1E950CB809594DFE0BBBAB1BB
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: msoc_image_rotation_noAlgo_fpga.slx___Model_Block___
ANNOTATION:
 Random Access of External Memory  Copyright 2019 The MathWorks, Inc. Testbench Output Memory Controller FPGA Memory Region 1 Memory Region 2 Testbench Input

BLOCK:
AXI4 Master Sink;AXI4 Master Source;Algorithm Start;FPGA Algorithm;Input Read Memory Channel;Memory Controller;Output Write Memory Channel;Reference;Register Channel;To Workspace

BLOCKTYPE:
A4M Sink;A4M Source;IO Data Source;Memory Channel;Memory Controller;ModelReference;Register Channel;ToWorkspace


MODELNAME: msoc_image_rotation_noAlgo_fpga
PATH: toolbox/soc/supportpackages/sdk/testmodels/msoc_image_rotation_noAlgo_fpga.slx
BLOCKTYPE: Bus Creator;Bus Selector;Delay;Demux;Inport;Logic;Outport;S-Function;Terminator;UnitDelay
BLOCKTYPE_FREQUENCY: 2;2;2;2;24;3;27;2;4;5
CHECKSUM: 7FC413670D0B9556FCB1BFCA118E9F59
PRODUCT: Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 Read one line of image data from external memory as one AXI4 burst  Write the reveresed data to external memory as one AXI4 burst and request next line  Reverse the order of the line data Copyright 2019 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AXI4MasterRead;AXI4MasterRead BusCreator;AXI4MasterRead BusSelector;AXI4MasterReadController;AXI4MasterWrite;AXI4MasterWrite BusCreator;AXI4MasterWrite BusSelector;AXI4MasterWriteController;Delay;ImageRotation;In;Logical Operator;OR;Out;PositiveEdgeDetection;Reference;ReverseDataOrder;SubSystem;Terminator;Unit Delay;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_wr_data;axim_wr_m2s;axim_wr_s2m;data;data_in;data_out;dvalid;dvalid_in;dvalid_out;rdCtrlIn;rdCtrlOut;rdData;rd_addr;rd_aready;rd_avalid;rd_data;rd_data_out;rd_dready;rd_dvalid;rd_dvalid_out;rd_len;ready;request_next_line;start;wrCtrlIn;wrCtrlOut;wrData;wr_addr;wr_complete;wr_data;wr_data_out;wr_dvalid;wr_len;wr_valid


MODELNAME: soc_swhwsw_stream_fpga
PATH: toolbox/soc/supportpackages/versal/versalexamples/soc_swhwsw_stream_fpga.slx
ANNOTATION: Copyright 2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;2;1;4;3;1;12;5;25;1;1;2;1
CHECKSUM: B7755E1096FB8FD1002E3B402374830D
PRODUCT: Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
AND;AXI Stream to Software Master CtrlIn;AXI Stream to Software Master CtrlOut;AXI Stream to Software Master Data;AXI Stream to Software Master Ready;AXI Stream to Software Master TLast;AXI Stream to Software Master Valid;Bit Concat;Compare To Zero;Constant;Enabled Delay;Enabled Resettable Delay;HDL Counter;HDL_IP;LEDs General Purpose;NOT;Reference;SoC Bus Creator;SoC Bus Selector;Software to AXI Stream Slave CtrlIn;Software to AXI Stream Slave CtrlOut;Software to AXI Stream Slave Data;Software to AXI Stream Slave Ready;Software to AXI Stream Slave Valid;State Control;SubSystem;Subtract;Terminator;Unit Delay;errorData;errorStatus;numValidData;numvalidData;rampCheck;rx_tdata;rx_tready;rx_tvalid;start;tvalidLED;tx_tdata;tx_tready;tx_tvalid

BLOCKTYPE:
Bit Concat;Bus Creator;Bus Selector;Compare To Zero;Constant;Delay;HDL Counter;Inport;Logic;Outport;StateControl;Sum;Terminator;UnitDelay


MODELNAME: soc_swhwsw_stream_proc
PATH: toolbox/soc/supportpackages/versal/versalexamples/soc_swhwsw_stream_proc.slx
BLOCKTYPE_FREQUENCY: 2;3;2;1;1;1;15;12;4;1;1;1;1;2;6;3
CHECKSUM: 92BCF362239E56EB21603A14CF73F533
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 Add your test source in above subsystem  Add your processor algorithm in above subsystem  Add your Processor Algorithm in above subsystem Copyright 2022 The MathWorks, Inc.

BLOCK:
AXI Stream to Software Master Read Data In;AXI Stream to Software Master Read Data Out;AXI Stream to Software Master Read Done;AXI Stream to Software Master Read Task;Add;Constant;Delay;Demux;Enable;Equal;Function-Call Generator;In;Processor Algorithm Wrapper;Reference;Register Read;Register Write;Registers;Software to AXI Stream Slave Write Data Out;Software to AXI Stream Slave Write Done;Software to AXI Stream Slave Write Task;Stream Read;Stream Read Task Specification;Stream Write;Stream Write Task Specification;SubSystem;Terminator;Trigger;Verify Rx Data;errorData;errorStatus;function;numvalidData;readDataIn;readDataOut;readDone;rxData;rxError;start;writeDataOut;writeDone

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;Delay;Demux;EnablePort;Function-Call Generator;Inport;Outport;Register Read;Register Write;RelationalOperator;Stream Read;Stream Write;Sum;Terminator;TriggerPort


MODELNAME: soc_swhwsw_stream_top
PATH: toolbox/soc/supportpackages/versal/versalexamples/soc_swhwsw_stream_top.slx
ANNOTATION: Copyright 2022 The MathWorks, Inc. Full Duplex Data Streaming between Software and Hardware
BLOCKTYPE_FREQUENCY: 1;1;8;1;2;3;2;1;1;1;1
CHECKSUM: 3C0FF68F27EC56BC4886FA04772940FB
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_swhwsw_stream_fpga.slx___Model_Block___soc_swhwsw_stream_proc.slx___Model_Block___
BLOCK:
AXI Stream to Software Master;AXI Stream to Software Master Read Data In;AXI Stream to Software Master Read Done;AXI Stream to Software Master Task Event;Assertion;FPGA;NOT;Processor;Processor - Frame based processing;Rate Transition;Reference;Register Channel;Software to AXI Stream Slave;Software to AXI Stream Slave Task Event;Software to AXI Stream Slave Write Data Out;Software to AXI Stream Slave Write Done;SubSystem;Task Manager;Time Scope;errorData;errorStatus;numvalidData;start

BLOCKTYPE:
AXI4-Stream to Software;Assertion;Inport;Logic;ModelReference;Outport;RateTransition;Register Channel;Scope;Software to AXI4-Stream;Task Manager


MODELNAME: soc_nrhdlSIB1Recovery_fpga
PATH: toolbox/soc/supportpackages/whdlsocexamples/soc_nrhdlSIB1Recovery_fpga.slx
CHECKSUM: A31EC641D62A993AD8FDDBC40D345215
PRODUCT: DSP HDL Toolbox;Embedded Coder;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
FIFO buffer dont write if full count entries in FIFO write address counter read address counter dont read if empty FIFO buffer dont write if full count entries in FIFO write address counter read address counter dont read if empty FIFO buffer dont write if full count entries in FIFO write address counter read address counter dont read if empty FIFO buffer dont write if full count entries in FIFO write address counter read address counter dont read if empty Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2) Range of x_f=[1,4) S2 S1 S0 S0 S1 S2 Range of x_e=[1,2) Range of x_f=[1,4) S0 S1 S2 S2 S1 S0 Range of x_e=[1,2) dont read if empty read address counter write address counter count entries in FIFO dont write if full FIFO buffer FIFO buffer dont write if full count entries in FIFO write address counter read address counter dont read if empty Copyright 2022-2023 The MathWorks, Inc.

BLOCK:
; Demux ; SFunction ; Terminator ;1-D Lookup Table;AFull;AND;AWGNGenerator;AXI-Stream Arbitrator;AXI-Stream Mux;AXI4-Stream FIFO;Abs;Access Arbitration;Add;Add Constant;Arbitrator;Assertion;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Assignment;Bus Creator;Bus Selector;CORESET0 Decoding;Cast;Cast To Boolean;Channel;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConcatandExtract;Concatenate;Constant;Convert Length;Counter;CyclesPerOutput;DDC;DUT;Data Capture;Data FWFT FIFO;Data FWFT FIFOs;Data Type Conversion;Data Type Duplicate;DataIn;DataOut;Debug Data;Delay;Detect Decrease;Detect Increase;Diagnostics Bus Creation;Empty;Equal;External Memory Data Capture;External Memory Read;External Memory Write;Extract Bits;FIFO;FMCOMMS;FWFT FIFO;For Each;Format ADC Data;Format DAC Data;Format Data;Frequency Offset;From;Full;FunctionEvaluation;G;GIn;GOut;Gain;GaussianNoiseWithUnitVar;Generate Unit Noise;Goto;Goto Tag Visibility;GreaterThan;Grid Demod Ctrl;Grid Demodulation;Grid Demodulation Disabled;HDL Counter;HDL FIFO;In;In Bus Element;Input Setup;LDPC Decoding;LastIn;LastOut;Lmax;Logical Operator;MATLAB Function;MIB Recovery;MIB Recovery Output;Multiport Switch;Mux;NCO;NCellID;NCellIDIn;NCellIDOut;NOT;NR Receiver;NSlot;NSlotIn;NSlotOut;No Channel;NotEmpty;Num;OR;Out;Out ;Out Bus Element;Output FIFO;Output Pacing;Pacing Source;Pack Complex;Parse Header;Polar Decoding;Polar Decoding Chain;Pop;Product;Push;Q;R;RFSoC;Radio Interface;RangeReconstruction;RangeReduction;RdAck;ReadyIn;ReadyPort;Real-Imag to Complex;Receiver;Reference;Report Results Ctrl;S;SIB1 Bits AXI-Stream;SIB1 Decoders Input;SIB1 Decoding;SIB1 Decoding Disabled;SIB1 Grid AXI-Stream;SIB1 Recovery Output;SSB Decoding;SSB Detection;SSB Frequency Tracking;SSB Grid AXI-Stream;SSB Report AXI-Stream;Selector;Send SSB Reports;Shift Arithmetic;Signal Specification;Simple Dual Port RAM;SinCos;Sine HDL Optimized;SoC Bus Creator;SoC Bus Selector;Source Selection;SqrtEval;SqrtImplementation;Start Generation;StartEarly;SubSystem;Subsystem;Subtract;Switch;TLAST FWFT FIFO;TausURNG;TausUniformRandGen;Terminal State Detector;Terminator;Transmit Repeat;Unit Delay;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;ValidIn;ValidOut;Vector Concatenate;Wordlength Upsample;Zc;Zc lookup;ZcIn;ZcOut;a;activeCfg;adcDataI;adcDataOut;adcDataQ;adcDataValid;afull;awgnEn;axi-stream control;axiStreamCtrl;b;baseAddr;bchStatus;bchStatusIn;bchStatusOut;burstLen;cache_reg;captureCtrl;captureData;captureLen;captureSource;captureValid;capturedDataCnt;centerFrequency;cfg;channelAWGNEn;channelFrequencyOffset;channelNoisePow;clearStatus;coProcMode;convert bus;coreset0DecodingIn;coreset0Occasion;coreset0RBs;coreset0RBsIn;coreset0RBsOut;coreset0Resources;coreset0Status;coreset0StatusIn;coreset0StatusOut;coreset0Syms;coreset0SymsIn;coreset0SymsOut;count;dIn;dOut;dacData;dacDataI;dacDataQ;dacDataValid;dataIn;dataLen;dataOut;dataWaiting;data_i;data_in;data_o;data_out;dc_baseAddr;dc_captureLen;dc_captureSource;dc_debugMode;dc_diagnostics;dc_offset;dc_queueStart;dciData;dciDataIn;dciDiag;dciDone;dciErr;dciInput;dciNextFrame;dciOutput;dciSearchFailed;dciSearchFailedIn;dciStatus;dciValid;ddrRdCtrlM2S;ddrRdCtrlS2M;ddrRdData;ddrReadController;ddrWrCtrl;ddrWrCtrlM2S;ddrWrCtrlS2M;ddrWrData;debugMode;decodeChainDiagnostics;decodeChainIn;decodeChainInput;decodeChainOut;decodeChainOutput;decodeChainStatus;demodModeDMAEn;demodTimeOut;detectionStatus;detectionStatusIn;detectionStatusOut;diagnostics;dtci;e;empty_i;empty_o;enableCapture;enableSend;enb;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;fifoHighWater;fifoNum;fifoPopEmptyCnt;fifoPushFullCnt;fifo_afull;firstOrSecondSlot;firstOrSecondSlotIn;firstOrSecondSlotOut;freqTrackEn;frequencyOffset;full;fullValid;fwft_logic;g;g1(16,15);gridData;gridDemodEn;gridDemodEnIn;gridDemodEnOut;gridDemodParams;gridDemodStatus;gridDemodStatusIn;gridDemodStatusOut;gridFrequencyOffset;gridMode;gridSendEn;gridValid;hdl_fwft_fifo;header;highWater;idx;in;kmssb;lastBurstLen;last_burst_len;last_out;ldpcCtrl;leadingZeroDetector;len;log;logImplementation;loopbackEn;maxIn;mibDiag;mibInput;mibOutput;mibRecovered;mibStatus;mibStreamCtrlM2S;mibStreamCtrlS2M;mibStreamData;mibStreamTLast;mibStreamTReady;mibStreamValid;minChanBW;muxPattern;ncoDelay;nextFrame;nextSSB;noisePow;notEmpty;nrbGrid;num;numBursts;numSlots;numSlotsIn;numSlotsOut;num_bursts;num_i;num_o;num_out_calc;offset;out;out_prev;out_reg;pack DCI;pack complex;packReport;params;parsedMIB;pass;passIn;passOut;pbchPayload;pbchPayloadIn;pbchPayloadOut;pbchStatus;pbchStatusIn;pbchStatusOut;polarAccess;polarCtrl;pop;popEmpty;popFIFO;pop_o;push;pushFull;queueStart;rbOffsetGrid;rdBaseAddr;rdCtrlM2S;rdCtrlS2M;rdData;rdEn;rdPtr;rd_ack;rd_active;rd_addr;rd_aready;rd_avalid;rd_data;rd_dready;rd_dvalid;rd_len;read_prev;ready;readyIn;readyOut;ready_in;receiverParams;receiverStart;reportSendEn;restart;resultSendEn;rst;rxData;rxDataIn;rxValid;rxValidIn;scsGrid;scsSSB;searchSpaces;searchSpacesIn;searchSpacesOut;selDCI;selStream;sendSIB1Grid;sendSSBDemod;sendSSBGrid;sendingReport;sib1Bits;sib1BitsCtrl;sib1BitsCtrlIn;sib1BitsCtrlOut;sib1BitsStream;sib1BitsValid;sib1DecStreamCtrlM2S;sib1DecStreamCtrlS2M;sib1DecStreamData;sib1DecStreamTLast;sib1DecStreamTReady;sib1DecStreamValid;sib1En;sib1Err;sib1ErrIn;sib1Grid;sib1GridStream;sib1GridValid;sib1LDPCDecodingIn;sib1Status;sib1StatusIn;sib1StatusOut;sib1StreamCtrlM2S;sib1StreamCtrlS2M;sib1StreamData;sib1StreamTLast;sib1StreamTReady;sib1StreamValid;source;sr_latch;ssbData;ssbDecodeValid;ssbDecodeValidIn;ssbDemodDMAEn;ssbFrequencyOffset;ssbGrid;ssbGridStream;ssbGridValid;ssbIndex3Lsb;ssbIndex3LsbIn;ssbIndex3LsbOut;ssbMode;ssbPattern;ssbReport;ssbReportIn;ssbReportStream;ssbReportValid;ssbReportValidIn;ssbValid;sssCorrelation;sssThreshold;start;startDCI;startGridDemod;startIn;startMIB;startOut;state;state_out;status;stopDemod;streamData;streamTLast;streamTReady;streamValid;supportedFR;tLast;tValid;tbs;tbsIn;tbsOut;tdata;timingOffset;timingUpdate;timingUpdateValid;tlast;tlastIn;trackedSSBFreqOffset;trackedSSBFreqOffsetIn;trackedSSBFreqOffsetOut;transfer_base_addr;transfer_enable;transmitEn;tready;tvalid;txR_baseAddr;txR_channelAWGNEn;txR_channelFrequencyOffset;txR_channelNoisePow;txR_dataLen;txR_loopbackEn;txR_transmitEn;u;u0(16,16);u0(48,48);u1(16,16);unitNoise;unitVarNoise;validIn;validInCnt;validOut;valid_out;waitAck;wrAck;wrAckCnt;wrAddr;wrCtrlM2S;wrCtrlS2M;wrData;wrPtr;wrReady;wrValidCnt;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
Abs;ArithShift;Assertion;Bias;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;BusAssignment;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Conversion Inherited;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Detect Decrease;Detect Increase;Extract Bits;ForEach;From;Gain;Goto;GotoTagVisibility;HDL Counter;HDL FIFO;HDL_FIFO;Inport;Logic;Lookup_n-D;ModelReference;MultiPortSwitch;Mux;NCO;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Selector;SignalSpecification;Simple Dual-port RAM;Sine and Cosine HDL optimized block;Sum;Switch;Terminator;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;UnitDelay

BLOCKTYPE_FREQUENCY:
3;42;4;1;19;58;32;63;5;5;2;8;13;26;7;7;6;72;1;53;6;396;27;1;9;2;1;132;7;55;4;28;6;2;700;244;22;7;29;2;1;623;23;7;7;27;17;3;6;4;34;34;90;11;23;21

EXTERNALFILE_REFERENCE:
nrhdlCORESET0DecodingCore___Model_Block___nrhdlDDCCore___Model_Block___nrhdlGridDemodulationCore___Model_Block___nrhdlLDPCDecodingChainCore___Model_Block___nrhdlPolarDecodingChainCore___Model_Block___nrhdlSSBDecodingCore___Model_Block___nrhdlSSBDetectionCore___Model_Block___


MODELNAME: soc_nrhdlSIB1Recovery_hostUDPReceive
PATH: toolbox/soc/supportpackages/whdlsocexamples/soc_nrhdlSIB1Recovery_hostUDPReceive.slx
BLOCKTYPE_FREQUENCY: 4;13;1;1;8;9;7;5;4;13;1;1;2;5;36;2;1;23;1;2;13;16;5
CHECKSUM: 8712D2AB6705D461BEBF110D8EF21060
PRODUCT: Simulink;SoC Blockset
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Interprets first entry in PSS Report table. In demodulation mode only one entry is returned and this is when the model is triggered to stop. Stop Logic   Copyright 2022-2023 The MathWorks, Inc.

BLOCK:
AND;Bit Concat;Bit Slice;Cast To Boolean;Cast To Double;Cell ID;Compare To Constant;Compare To Zero;Constant;Data Type Conversion;Decoded Cell ID;Disable;Divide;Divide by K to convert Threshold to Energy;Enable;Gain;Interpret Final PSS Report;Interpret SSS Report;Kssb;Lmax;Log;MIB to workspace;Multiport Switch;NR-RSSI;NR-RSSI (dBm);PSS SNR;PSS SNR (dB);PSS_Correlation;PSS_FrequencyOffset;PSS_Threshold;PSS_TimingOffset;PSS_nCellID;ParseMIB;Process & Log PSS Reports;Process & Log SSS Report;Process & Log Signal Quality Report;Reference;SS-RSRP;SS-RSRP (dBm);SS-RSRQ;SS-RSRQ (dB);SS-SINR;SS-SINR (dB);SSS SNR (dB);SSS_SNR_DB;Scope;SelectedPSSReport_CorrelationStrength;SelectedPSSReport_FrequencyOffset;SelectedPSSReport_PSSID;SelectedPSSReport_TimingOffset;SelectedPSSReport_pssThreshold;Selector;Stop Simulation;Stop after first SIB1 received?;SubSystem;Subsystem;Subtract;Terminator;To Workspace;UDP Read;Zero;cellBarred;cellID;dmrsTypeAPos;enumToValue;frequencyRange;hrf;intraFreqResel;measurementsReport;pbchBits;pbchPayload;reportData;reportFormat;scsCommon;scsCommonEnum;selectedParameters_CorrelationStrength;selectedParameters_FrequencyOffset;selectedParameters_SubCarrierSpacing;sfn;sib1Bits;sib1Bits to workspace;sib1Config;ssbIndex;ssbIndex3Lsb;sssCorrelation;sssReport;sssThreshold

BLOCKTYPE:
Bit Concat;Bit Slice;Compare To Constant;Compare To Zero;Constant;DataTypeConversion;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;Math;MultiPortSwitch;Outport;Product;Scope;Selector;Stop;Sum;Terminator;ToWorkspace;UDP Read


MODELNAME: soc_nrhdlSIB1Recovery_proc
PATH: toolbox/soc/supportpackages/whdlsocexamples/soc_nrhdlSIB1Recovery_proc.slx
BLOCKTYPE_FREQUENCY: 1;4;15;1;3;4;2;41;36;4;10;1;4;8;66;1;48;181;2;9;1;179;13;2;18;34;10;2;2;1;27;5
CHECKSUM: A6ADD33CE476FDFC8DA5479063751174
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
adding delay to feedback loop with cell search controller Set useCentreFrequency = true to use centre frequency derived parameters Set false to use workspace variables Output SSB grid after demodulation  Number of frequency offset steps to search above/below centre (-n,...,-1,0,1,...,n) Data Capture Software Processing Copyright 2022-2023 The MathWorks, Inc. UDP send to host Signals To FPGA Signals From FPGA

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Add Constant;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Cast;Cast To Boolean;Cast To Double;Cell Search Controller;Center Frequency;Compare To Constant;Constant;DCI Preprocess;Data;Data Capture Control;Data Type Conversion;Delay;Detect Change;Detect Rise Positive;Enable;Fc;Fc_out;Format Data;From;Gain;Goto;Grid Construction;Hold Signal;Hz To NCO;In;Index Lookup;Input Setup;L max;LDPC Preprocess;Lmax;Lmax_out;Lmax_set;MATLAB Function;MIB;Measurements;Multiport Switch;Mux;NCellID;NCellID_out;NCellid;OR;Out;PSSReport Data;Parse MIB;Rate Transition;Read MIB Stream;Read SIB1 Stream;Real-Imag to Complex;Reference;Register Read;Register Write;Register_Read_NCellID;Register_Read_bchStatus;Register_Read_cfg;Register_Read_coreset0Status;Register_Read_dciData;Register_Read_dciErr;Register_Read_detectionStatus;Register_Read_firstOrSecondSlot;Register_Read_pbchPayload;Register_Read_pbchStatus;Register_Read_sib1DemodStatus;Register_Read_sib1Err;Register_Read_sib1Status;Register_Read_ssbIndex3Lsb;Register_Read_sssCorrelation;Register_Read_sssThreshold;Register_Read_trackedSSBFreqOffset;Register_Write_Lmax;Register_Write_NCellID;Register_Write_centerFrequency;Register_Write_chanAWGNEn;Register_Write_chanAWGNPow;Register_Write_chanFreqOffset;Register_Write_ddrReader_baseAddr;Register_Write_ddrReader_dataLength;Register_Write_ddrReader_en;Register_Write_demodModeDMAEn;Register_Write_demodTimeOut;Register_Write_freqTrackEn;Register_Write_frequencyOffset;Register_Write_gridDemodEn;Register_Write_loopbackEn;Register_Write_minChanBW;Register_Write_mode;Register_Write_nrbGrid;Register_Write_rbOffsetGrid;Register_Write_receiverStart;Register_Write_scsGrid;Register_Write_scsSSB;Register_Write_sendMIBGrid;Register_Write_sendSIB1Grid;Register_Write_sib1En;Register_Write_ssbPattern;Register_Write_stopDemod;Register_Write_timingOffset;SCS Lookup;SIB1 Processing;SIB1 SW Processing;SIB1 Stream Read;SSB Data In;SSB Data Out;SSB Signal Quality Measurements;SelectedPSSReport;SelectedParams;Signal Quality Report;Software Configuration;Software Start;Software Start LongPulse;Start/Restart Pulse Generator;Stream Read;Stream Write;SubSystem;Terminator;UDP Write;Unpack Stream Data;Vector Concatenate;axiLite from FPGA;axiLite to FPGA Receiver;axiLite to FPGA txRepeat;axiPayload;axiStreamMsg;axiStreamPayload;axiStreamValid;baseAddr;bchStatus;bchStatus_out;captureLen;captureSoure;carrierFrequency;cellID;cell_ID;centerFrequency;centerFrequencyIn;cfg;cfg_Out;chanAWGNEn;chanAWGNPow;chanFreqOffset;coarseFreqSteps;coreset0Status;coreset0Status_out;coresetNSlot;coresetNSlotOut;dataIn;dataOut;dataValid;dc_baseAddr;dc_captureLen;dc_captureSource;dc_debugMode;dc_diagnostics;dc_offset;dc_queueStart;dciData;dciData_out;dciErr;dciPayload;dciPayloadValid;ddrReader_baseAddr;ddrReader_dataLength;ddrReader_en;debugMode;demodModeDMAEn;demodReport;demodReportValid;demodTimeOut;detectionStatus;detectionStatus_out;diagnostics;done;enable;fOffset;firstOrSecondSlot;firstOrSecondSlot_out;freqTrackEn;frequencyOffset;grid;gridConstruct;gridData;gridDemodEn;gridMode;gridModeIn;gridValid;hardwareMode;hwMode;hwStart;hwStatus;isFR;loopbackEn;mib;mibStreamData;mibStreamDone;minChBand;minChanBW;minChanBW_idx;minChanBW_out;minChanBW_set;minChanBw;minChannelBW;muxPattern;muxPatternOut;nCellID;nCellIDIn;nCellIDOut;nCellID_out;newGrid;nrbGrid;numPSSout;offset;outputSSBGrid;parsedMIB;payloadValid;pbchPayload;pbchPayload_out;pbchStatus;permittedSCS;permittedssbPatterns;pssReport;pssReportValid;queueStart;rbOffsetGrid;receiverStart;reportVector;reportVectorValid;reset;restart;rst;scs;scsCommon;scsCommon_idx;scsGrid;scsSSB;scsSSB_idx;scs_ssb;secondSlotFlag;secondSlotFlag_out;selectedParams;selectedReport;sendNextSIB1Grid;sendSIB1Grid;sendSSBDemod;set;setupFreqDependantParams;sib1Bits;sib1BitsValid;sib1DemodStatus;sib1En;sib1Err;sib1Error;sib1Error_out;sib1Grid;sib1GridData;sib1GridValid;sib1Payload;sib1Status;sib1Status_out;sib1StreamData;sib1StreamDone;sigQualMeasurements;sigQualReportVector;signalQualityMeasurements;signalQualityMeasurementsValid;ssbData;ssbGrid;ssbGridData;ssbGridValid;ssbIdx;ssbIdx3Lsb;ssbIndex;ssbIndex3Lsb;ssbIndex3Lsb_out;ssbIndex_out;ssbMeasurements;ssbMode;ssbModeIn;ssbPat;ssbPattern;ssbPattern_set;sssCorr;sssCorrelation;sssCorrelation_out;sssThresh;sssThreshold;sssThreshold_out;stopDemod;stream write;streamData;streamDataIn;streamDone;streamValid;subcarrierSpacing;swStart;tOffset;timingOffset;trackedSSBFreqOffset;udp_SIB1Bits;udp_mibReport;udp_pssReport;udp_ssbMeasurements;udp_sssReport;useCenterFrequency;validIn;validOut;waitForDCI;writeData;writeDone

BLOCKTYPE:
Bias;Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Change;Detect Rise Positive;EnablePort;From;Gain;Goto;Inport;Logic;MultiPortSwitch;Mux;Outport;RateTransition;RealImagToComplex;Register Read;Register Write;S-Function;Signal From Workspace;Stream Read;Stream Write;Terminator;UDP Write

PRODUCT:
Communications Toolbox;DSP System Toolbox;Embedded Coder;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset


MODELNAME: soc_nrhdlSIB1Recovery_top
PATH: toolbox/soc/supportpackages/whdlsocexamples/soc_nrhdlSIB1Recovery_top.slx
BLOCKTYPE_FREQUENCY: 1;2;1;28;28;21;2;37;1;4;1;1;3
CHECKSUM: A594171E6B31D4A09DCBFFB0E567B6E5
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_nrhdlSIB1Recovery_fpga___Model_Block___soc_nrhdlSIB1Recovery_proc___Model_Block___
ANNOTATION:
Copyright 2022-2023 The MathWorks, Inc.  5G NR SIB1 Recovery for FR1 and FR2 Using Xilinx RFSoC Device

BLOCK:
AXI4 Random Access Memory;Delay;FPGA;From;Goto;Lmax;MIB AXI4-Stream to Software;NCellID;RF Data Converter;Reference;SIB1 AXI4-Stream to Software;Software;Software to AXI4-Stream;SubSystem;Task Manager;Terminator;bchStatus;centerFrequency;cfg;chanAWGNEn;chanAWGNPow;chanFreqOffset;coreset0Status;dc_baseAddr;dc_captureLen;dc_captureSource;dc_debugMode;dc_diagnostics;dc_offset;dc_queueStart;dciData;dciErr;ddrReader_baseAddr;ddrReader_en;ddrReader_numBursts;demodModeDMAEn;demodTimeOut;detectionStatus;extMemDataCaptureRegisters;firstOrSecondSlot;freqTrackEn;frequencyOffset;gridDemodEn;gridMode;loopbackEn;mibStreamData;mibStreamDone;minChanBW;nrbGrid;pbchPayload;pbchStatus;rbOffsetGrid;receiverRegistersM2S;receiverRegistersS2M;receiverStart;scsGrid;scsSSB;sendNextSIB1Grid;sendSSBDemod;sib1DemodStatus;sib1Error;sib1Status;sib1StreamData;sib1StreamDone;ssbIndex3Lsb;ssbMode;ssbPattern;sssCorrelation;sssThreshold;stopDemod;sw_inst;timingOffset;trackedSSBFreqOffset;txRepeatRegisters;writeData;writeDone

BLOCKTYPE:
AXI4 Random Access Memory;AXI4-Stream to Software;Delay;From;Goto;Inport;ModelReference;Outport;RF Data Converter;Register Channel;Software to AXI4-Stream;Task Manager;Terminator


MODELNAME: soc_nrhdlSignalDetection_fpga
PATH: toolbox/soc/supportpackages/whdlsocexamples/soc_nrhdlSignalDetection_fpga.slx
CHECKSUM: 7BD919D9D2E3B5209C820CA2D20782A9
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Enable OFDM Demod for 4 OFDM symbols  Delay data by Nfft + cyclic prefix of 18 to align detection peak with start of OFDM symbol containing selected PSS  DistributedPipelining =on to pipeline MAX tree Delay balance for pipelined MAX Delay balance for pipelined MAX  DistributedPipelining =on to pipeline MAX tree  DistributedPipelining =on to pipeline MAX tree Delay balance for pipelined MAX  Apply thresholding to correlation peaks and select strongest peak within sl_in.windowLength sample window Match delays in peak filtering subsystems Convert to unsigned  Increase integer bits to allow for growth in averaging filter Sum across a window of Nfft samples using a comb filter followed by an integrator. Synchronize signals between correlator and threshold paths Each PSS Correlator performs resource sharing. There are sl_in.cyclesPerSample clock cycles per input sample, allowing for serialization of the operations  convert to sfix16_15 to match filter input data type Decimate to 15KHz SCS rate 0 = 15kHz SCS 1 = 30kHz SCS Synchronize signals across PSS Detector dont read if empty read address counter write address counter count entries in FIFO dont write if full FIFO buffer FIFO buffer dont write if full count entries in FIFO write address counter read address counter dont read if empty

BLOCK:
 Demux ; SFunction ; Terminator ;A;AFull;AND;Add;B;Bit Concat;Bit Slice;C;Cast;Compare To Constant;Compare To Zero;Complex to Real-Imag;Constant;Convert Length;DUT;Data FWFT FIFO;Data FWFT FIFOs;Data Type Conversion;Data Type Duplicate;DataIn;DataOut;Delay;Delay Enabled Synchronous;Demux;Detect Rise Positive;E;Empty;Enable;Enabled Delay;Equal;External Memory Read;FIFO;FIR Decimator;FIR Interpolator;Find Peak;For Each;Format Data;From;Full;Gain;Goto;HDL Counter;In;LastIn;LastOut;Logical Operator;MATLAB Function;Max;Multiport Switch;Mux;NOT;Num;OFDM Demod Controller;OFDM Demodulator;OR;Out;Out ;Output FIFO;PSS Correlator ;PSS Detector;Pop;Product;Push;Q;R;RdAck;ReadyIn;Real-Imag to Complex;Reference;S;SSB Detect and Demod;Selector;Simple Dual Port RAM;Simple Dual Port RAM System;SoC Bus Creator;SoC Bus Selector;State Control;Stream Synchronizer;SubSystem;Switch;Synchronous Delay;Synchronous Enabled Nfft Sample Delay ;Synchronous Enabled Unit Delay;TLAST FWFT FIFO;Tapped Delay;Terminator;To Workspace;Transient Removal;TxData_im;TxData_re;TxValid;Unit Delay;Unit Delay Enabled Synchronous;ValidIn;ValidOut;baseAddr;cache_reg;corrMag;data;dataIn;dataIn_im;dataIn_re;dataIn_valid;dataLen;dataOut;dataOut_re;dataRawOut;dataRawValid;data_i;data_o;data_out;ddrCtrlIn;ddrCtrlOut;ddrRdData;ddrReadController;delay to symbol start;detectionPeaks;detectionStrobe;detector;done;empty_i;empty_o;en;enabledTapDelay;fifo_afull;filter peaks ;fwft_logic;inputDecimBy;last;lastBurstLen;last_burst_len;last_out;len;max;num;numBursts;num_bursts;num_i;num_o;num_out_calc;out_prev;out_reg;peaks;pipelinedMax;pop;pop_o;pssDetected;pssID;pssIndex;push;rawLast;rawOutput;rdAddr;rdBaseAddr;rdCtrlM2S;rdCtrlS2M;rdData;rdEn;rdPtr;rd_ack;rd_active;rd_addr;rd_aready;rd_avalid;rd_data;rd_dready;rd_dvalid;rd_len;read_prev;ready;register PSS ID;scsSSB;scsSelection;selectedPSS;signalMag;signalMagAverage;sliceHalf;sourceSelect;sr_latch;start;startIn;state_out;strobeOut;threhold;thresholdIn;transfer_base_addr;transfer_enable;transmitEn;txDisable;txRepeat DDR interface;u;unpackComplexVec;valid;validIn;validOut;valid_out;wrAddr;wrEn;wrPtr;y

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;DataTypeConversion;DataTypeDuplicate;Delay;Delay Enabled;Demux;Detect Rise Positive;Discrete FIR Filter;EnablePort;FIR Decimator;FIR Interpolator;ForEach;From;Gain;Goto;HDL Counter;HDL FIFO;Inport;Logic;MinMax;MultiPortSwitch;Mux;OFDM Demodulator;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Selector;Simple Dual-port RAM;StateControl;Sum;Switch;Tapped Delay Line;Terminator;ToWorkspace;Unit Delay Enabled Synchronous;UnitDelay;hdl.RAM

BLOCKTYPE_FREQUENCY:
1;1;2;1;5;2;6;8;12;2;139;1;10;1;3;3;3;1;1;37;1;13;8;2;159;70;3;12;1;1;148;9;1;7;8;6;2;7;6;4;4;25;7;6;6;2

PRODUCT:
DSP HDL Toolbox;Embedded Coder;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset;Wireless HDL Toolbox


MODELNAME: soc_nrhdlSignalDetection_top
PATH: toolbox/soc/supportpackages/whdlsocexamples/soc_nrhdlSignalDetection_top.slx
BLOCKTYPE_FREQUENCY: 1;1;4;1;5;7;1;1;2;1;1;1;2;2;2;5;4;1;4;3
CHECKSUM: 880586CD9AE1DA92CA4BA31CD2801D86
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_nrhdlSignalDetection_fpga.slx___Model_Block___
BLOCK:
AXI4 Random Access Memory;AXI4-Stream to Software;Bit Slice;Constant;Data Type Conversion;Delay;Enable;FPGA;Log Data;Log Stream Data;RF Data Converter;Real-Imag to Complex;Reference;Register Channel;Register Read;Register Write;Signal From Workspace;SoC Bus Creator;Stream Read;SubSystem;Terminator;To Workspace;done;msg;u

BLOCKTYPE:
AXI4 Random Access Memory;AXI4-Stream to Software;Bit Slice;Bus Creator;Constant;DataTypeConversion;Delay;EnablePort;Inport;ModelReference;Outport;RF Data Converter;RealImagToComplex;Register Channel;Register Read;Register Write;Signal From Workspace;Stream Read;Terminator;ToWorkspace

PRODUCT:
DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: priv_ZynqRFSoC_HostIIOSkeleton
BLOCKTYPE: Inport;Outport;soc.libiio.axistream.ReadHost;soc.libiio.axistream.WriteHost
BLOCKTYPE_FREQUENCY: 2;2;1;1
CHECKSUM: 9C941C7CEAFE2E3B503390283C768360
PRODUCT: Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/xilinxsoc/referencedesign/zynqrf/+ZynqRF/+common/priv_ZynqRFSoC_HostIIOSkeleton.slx

ANNOTATION:
ARM Interface to AXI4 Memory Map  Write to HW user logic here  Read from HW user logic here ARM Interface to AXI4 Stream DMA  AXI4 Stream DMA Write  AXI4 Stream DMA Read Title Intro

BLOCK:
AXI4-Stream IIO Read;AXI4-Stream IIO Write;DUTInterfaceBlock;DUTInterfaceIn;DUTInterfaceOut;Reference;SubSystem


MODELNAME: priv_ZynqRFSoC_SWprocSkeleton
BLOCKTYPE_FREQUENCY: 3;1;8;6;1;1;4
CHECKSUM: 6941A45A48BF0B82EDA856F70FC2D7E1
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
PATH:
toolbox/soc/supportpackages/xilinxsoc/referencedesign/zynqrf/+ZynqRF/+common/priv_ZynqRFSoC_SWprocSkeleton.slx

DESCRIPTION:
HDL model for RFSoC ADC/DAC 8x8 interfacing This model contains demonstrates how to interface to all 8 ADC and 8 DAC channels for the RFSoC. Please ensure that you run the initialization script to set the correct PLL clock rates. 

ANNOTATION:
 Write register to FPGA user logic here  Read register from FPGA user logic here Read / Write Registers Control Task  Stream data from FPGA user logic here Read from AXI4 Stream DMA Task  Stream data to FPGA user logic here Write to AXI4 Stream DMA Task ARM Interface to AXI4 Memory Map ARM Interface to AXI4 Stream DMA  Read/Write Register  AXI4 Stream DMA Read  AXI4 Stream DMA Write Intro Title

BLOCK:
Asynchronous Task Specification;Control Task;DUTInterfaceBlock;DUTInterfaceIn;DUTInterfaceOut;PeriodicRate;ReadTask;Reference;Stream Read;Stream Write;SubSystem;Subsystem;Write Task;WriteTask;data;done;function;rd_data;rd_done;wr_data;wr_done

BLOCKTYPE:
AsynchronousTaskSpecification;Function-Call Generator;Inport;Outport;Stream Read;Stream Write;TriggerPort


MODELNAME: priv_ZynqRFSoC_SWtopSkeleton
ANNOTATION: Title Intro
BLOCK: Processor;Reference;Stream from FPGA;Stream to FPGA;Task Manager
BLOCKTYPE: IO Data Sink;IO Data Source;ModelReference;Task Manager
BLOCKTYPE_FREQUENCY: 1;1;2;1
CHECKSUM: 14D7C5029021EC7EC9CF3B5DD6649C28
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: priv_ZynqRFSoC_SWprocSkeleton.slx___Model_Block___
PATH:
toolbox/soc/supportpackages/xilinxsoc/referencedesign/zynqrf/+ZynqRF/+common/priv_ZynqRFSoC_SWtopSkeleton.slx

DESCRIPTION:
HDL model for RFSoC ADC/DAC 8x8 interfacing This model contains demonstrates how to interface to all 8 ADC and 8 DAC channels for the RFSoC. Please ensure that you run the initialization script to set the correct PLL clock rates. 


MODELNAME: priv_SWprocSkeleton
PATH: toolbox/soc/supportpackages/xilinxsoc/referencedesign/zynqrf/templates/priv_SWprocSkeleton.slx
BLOCKTYPE_FREQUENCY: 3;1;8;5;1;1;4
CHECKSUM: D1F4F18F96A1E7695E23EB12C7FB30C9
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
HDL model for RFSoC ADC/DAC 8x8 interfacing This model contains demonstrates how to interface to all 8 ADC and 8 DAC channels for the RFSoC. Please ensure that you run the initialization script to set the correct PLL clock rates. 

ANNOTATION:
 Write register to FPGA user logic here  Read register from FPGA user logic here Read / Write Registers Control Task  Interrupt handler user logic here Interrupt Task  Stream data from FPGA user logic here Read from AXI4 Stream DMA Task  Stream data to FPGA user logic here Write to AXI4 Stream DMA Task FPGA Interrupt ARM Interface to AXI4 Stream DMA  AXI4 Stream DMA Read  AXI4 Stream DMA Write Intro Title  Read/Write Register ARM Interface to AXI4 Memory Map  FPGA Interrupt

BLOCK:
Asynchronous Task Specification;Control Task;DUTInterfaceBlock;DUTInterfaceIn;DUTInterfaceOut;Interrupt Task;InterruptTask;PeriodicRate;Read Task;ReadTask;Reference;Stream Read;Stream Write;SubSystem;Write Task;WriteTask;data;done;function;rd_data;rd_done;wr_data;wr_done

BLOCKTYPE:
AsynchronousTaskSpecification;Function-Call Generator;Inport;Outport;Stream Read;Stream Write;TriggerPort


MODELNAME: soc_AD9361DualChannel_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_AD9361DualChannel_fpga.slx
BLOCKTYPE_FREQUENCY: 3;1;1;1;3;2;1;7;1;5;12;1;2;1;7;2;2;3;1;7;34;37;2;37;3;1;1;1;2;5;4;2;4
CHECKSUM: 8E4A20DE97F4ADAE9D585B028FDAB461
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input  Copyright 2023 The MathWorks, Inc.

BLOCK:
AFull;AXI4-Stream DMA Master Data;AXIS_FIFO_Full;AXIS_FIFO_Num;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;Add;AutoTrigger;BackPressureCounterEn;Bit Concat;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;Data Type Conversion;DataCaptureEn;DataPushFrequency;DefaultConsecFrames;DefaultRegister;Delay;Demux;Detect Increase;Display;EnableConsecutiveFrames;FWFT_FIFO;From;Gain;Goto;HDL Counter;HDL FIFO;HDLTxIpCore;IP Core Register Read;In;Logical Operator;MaxCount;NCO;Out;Q;R;Reference;Relational Operator;Reshape;RxData;Rxdata;S;SW_en;Signal Specification;SoC Bus Creator;SoC Bus Selector;State Control;Stream DMA Master CtrlIn;Stream DMA Master CtrlOut;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Trig;Trigger;Trigger Capture;TriggerCapture;Tx Channel;Tx1DataI_Out;Tx1DataQ_Out;Tx1PhaseIncrement;Tx1Valid_Out;Tx2DataI_Out;Tx2DataQ_Out;Tx2PhaseIncrement;Tx2Valid_Out;TxData;TxValid;Unit Delay;ValidOut;Vector Concatenate;afull;cache_reg;data_i;data_o;dtci;empty_i;empty_o;enb;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sr_latch;txDataOut;txValid

BLOCKTYPE:
Bit Concat;Bus Creator;Bus Selector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;IP Core Register Read;Inport;Logic;NCO;Outport;RelationalOperator;Reshape;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay

PRODUCT:
DSP HDL Toolbox;Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_AD9361DualChannel_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_AD9361DualChannel_proc.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc. Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;7;6;1;4;4;4;8;2;7;2;1;1;1;1;1
CHECKSUM: 1A226DE8260C387248093B44087BF644
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Asynchronous Task Specification;Constant;Data Type Conversion;Event Listener;Extract Bits;Gain;Initialize Function;Packed data;Processor Algorithm Wrapper;Real-Imag to Complex;Reference;Register Write;Slider Gain;Stream Read;SubSystem;Terminator;Trigger;Unpack data;Zynq and FMCOMMS2/3/4 Receiver;Zynq and FMCOMMS2/3/4 Transmitter;channel1data;channel2data;data;data1Out;data2Out;dataIOut;dataQOut;dataTask;done

BLOCKTYPE:
AsynchronousTaskSpecification;Constant;DataTypeConversion;EventListener;Extract Bits;Gain;Inport;Outport;RealImagToComplex;Register Write;Slider Gain;Stream Read;Terminator;TriggerPort;comm.internal.SDRRxZC706FMC234RFSL;comm.internal.SDRTxZC706FMC234RFSL


MODELNAME: soc_AD9361DualChannel_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_AD9361DualChannel_top.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;3;2;4;2;2;2;1
CHECKSUM: 55C73B7316390D904681B7AD286A7FDC
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_AD9361DualChannel_fpga.slx___Model_Block___soc_AD9361DualChannel_proc.slx___Model_Block___
ANNOTATION:
 Transmit and Receive tones using AD9361 Dual Channels External I/O External I/O Memory Processor FPGA  Copyright 2023 The MathWorks, Inc.

BLOCK:
AD9361Rx;AD9361Tx;AXI4-Stream to Software;Channel;FPGA Algorithm;Processor;Processor-Frame based processing;RFIn;RFOut;RT;Reference;Simple delay channel;SubSystem;Task Manager;ch;ch1 spectrum;ch2 spectrum;data;data1out;data2out;dataTask;done

BLOCKTYPE:
AD9361 Rx Playback;AD9361 Tx Playback;AXI4-Stream to Software;Delay;Inport;ModelReference;Outport;RateTransition;Scope;SpectrumAnalyzer;Task Manager


MODELNAME: soc_IQ_datacapture_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_IQ_datacapture_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;3;4;2;7;1;5;6;2;1;7;3;2;3;1;6;37;37;4;36;3;1;1;2;5;7;2;4
CHECKSUM: DAA7B36BB7DECC468D8C6A09AAEF8D75
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input  Copyright 2022 The MathWorks, Inc.

BLOCK:
AFull;AXI4-Stream DMA Master CtrlIn;AXI4-Stream DMA Master CtrlOut;AXI4-Stream DMA Master Data;AXIS_FIFO_Full;AXIS_FIFO_Num;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;Add;AutoTrigger;BackPressureCounterEn;Bit Concat;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;DAC Tone Generation;DAC1_IData;DAC1_QData;DAC1_Valid;Data Type Conversion;DataCaptureEn;DataPushFrequency;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;EnableConsecutiveFrames;FWFT_FIFO;From;Gain;Goto;HDL Counter;HDL FIFO;IP Core Register Read;IP Core Register Read_;In;Increment;Logical Operator;MaxCount;NCO HDL Optimized;NCO_Im;NCO_Re;NCO_Transmit;Out;Q;R;Reference;Relational Operator;S;SW_en;Signal Specification;SoC Bus Creator;SoC Bus Selector;State Control;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Trig;Trigger;Trigger Capture;TriggerCapture;Unit Delay;Valid;ValidOut;Vector Concatenate;adcIData;adcQData;adcValid;afull;cache_reg;dacIData;dacQData;dacValid;data_i;data_o;dtci;empty_i;empty_o;enb;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sr_latch

BLOCKTYPE:
Bit Concat;Bus Creator;Bus Selector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;IP Core Register Read;Inport;Logic;NCO;Outport;RelationalOperator;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_IQ_datacapture_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_IQ_datacapture_proc.slx
ANNOTATION: Copyright 2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;2;6;9;1;8;2;3;4;1;6;10;1;1;1;1
CHECKSUM: 7028A2D63730282472F3300958C9EFE5
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Asynchronous Task Specification;Constant;Data Type Conversion;DataIn;DataOut;DataTask;Event Listener;Extract Bits;Gain;Initialize Function;Processor Algorithm Wrapper;Real-Imag to Complex;Reference;Register Write;Reshape;Slider Gain;Stream Read;SubSystem;Terminator;Trigger;Vector Concatenate;dataIn;dataOut;done

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;EventListener;Extract Bits;Gain;Inport;Outport;RealImagToComplex;Register Write;Reshape;Slider Gain;Stream Read;Terminator;TriggerPort


MODELNAME: soc_IQ_datacapture_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_IQ_datacapture_top.slx
BLOCKTYPE_FREQUENCY: 1;1;3;2;3;1;1;1;1;1
CHECKSUM: 18B6F8FDF41A0457EF283E05180F06B8
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_IQ_datacapture_fpga.slx___Model_Block___soc_IQ_datacapture_proc.slx___Model_Block___
ANNOTATION:
IO Data/ Test bench Processor Memory  Transmit and Receive a Tone Using RFSoC Device  Copyright 2022 The MathWorks, Inc. FPGA RF IO

BLOCK:
ADC Captured Scope Output;ADC Captured Signal;AXI4-Stream to Software;Delay;FPGA Data Capture;Processor;Processor - Frame based processing;RF Data Converter;RF Loopback;Rate Transition;Reference;SubSystem;Task Manager;adc1In;dac1Out;dataIn;dataOut;dataTask;done

BLOCKTYPE:
AXI4-Stream to Software;Delay;Inport;ModelReference;Outport;RF Data Converter;RateTransition;Scope;SpectrumAnalyzer;Task Manager


MODELNAME: soc_QPSK_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_QPSK_fpga.slx
CHECKSUM: AEC98930535E381D8BA9419696BF8909
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 Fixed point precision loss warnings are supressed in Mask Init Callback fixed point precision loss warning supressed for this subsystem store the value in the Reg before reset  Set this value to zero to disable phase ambiguity correction  Let Z be the complex Phase Ambiguity estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z)) peak picker This subsystem generates variables required for QPSKRxVerification for validation Proportional-Plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence  HDL Data Scrambler Polynomial: x^7+x^4+1 Initial state: [1 0 1 1 1 0 1]  The Preamble is padded with zeros in the LUT such that the length is the 2^nextpow2(length(Preamble)) for efficient resource mapping to RAM  HDL Data Scrambler Polynomial: x^7+x^4+1 Initial state: [1 0 1 1 1 0 1]  As the symbols come at a clock rate twice the symbol rate with discrete valid, this logic is an equivalent to upsample by 2. QPSK Transmit and Receive  Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AXI4S_Data_Out;AXI4S_Valid_Out;Add;All High;Assertion;Automatic Gain Control;Average Estimates;BER;BIT_XOR;Bit Concat;Bit Packetizer;Bit Shift;Bit Slice;Bits Store;Bits to Char;Bus Creator;Bus Selector;CFO step change detector;Capture Data Bits;Carrier Synchronizer;Cast To Double;Coarse Frequency Compensator;Coarse Frequency Estimator;Compare To Constant;Complex to Magnitude-Angle;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Conj;Constant;ConstellationCtrlIn;ConstellationData;ConstellationValid;Correlation Time Scope;Correlator;Data Bits Counter;Data Bits Store;Data Type Conversion;Data Type Duplicate;Delay;Delay Adjust;Delay Adjust End;Delay Adjust Start;Delta;Direct Digital Synthesis;Direct Lookup Table (n-D);Discrete FIR Filter;Display;Divide by ;Downsample;E;EOF;Enable;End Generator;Error Detector;Extract Bits;Extract Frequency;FIFO;Frame Counter;Frequency and Time Synchronizer;From;Function Impl;GTED;Gain;Gardner TED;Goto;H;HDL Counter;HDL Data Descrambler;HDL Data Scrambler;In;InputGen;Integ Reg;IntegOut;IntegValid;Integer Delay;Integrator;Interpolation Control;Interpolation Filter;K;L;LUT;LUTAddr;Logical Operator;Loop Filter;MATLAB Function;Magnitude Squared;Magnitude Squared and Moving Sum;Math Function;Multiplexer;Multiport Switch;Mux;NCO;NCO HDL Optimized;No HDL;Null;Out;Packet Controller;Peak Search;Phase Ambiguity Corrector;Phase Ambiguity Estimation and Correction;Phase Ambiguity Estimator;Phase Error Detector;PhaseError;Preamble;Preamble Bits Counter;Preamble Bits Store;Preamble Detector;Preamble LUT;Prepare Inputs;Prepare Outputs;Product;QPSK Demodulator;QPSK Demodulator Baseband;QPSK Modulator;QPSK Modulator Baseband;QPSK Receiver Constellation ;QPSK Receiver Constellations ;QPSK Receiver Eye Diagram;QPSK Rx;QPSK Tx;QPSK Tx Channel QPSK Rx;QPSK TxRx;QPSKSystem;RAM;RAM Status Indicator;RRC Filter;RRC Receive Filter;RRC Transmit Filter;Raise Power to ;Rate Handle;Read Address Generator;Real-Imag to Complex;Reciprocal;Ref;Reference;Relational Operator;Repeat;Reset Generator;RxDataI_Out;RxDataIn;RxDataQ_Out;RxData_In;RxData_Out;RxDecodedMsgCtrlIn;RxDecodedMsgData;RxDecodedMsgValid;RxIn;RxVIn;RxValidOut;RxValid_In;RxValid_Out;Send Payload Data;Serializer1D;Signal Specification;Simple Dual Port RAM;State Register;Store Reg;SubSystem;Subsystem;Sum;Switch;Symbol Counter;Symbol Synchronizer;SyncPulse;Terminator;ThresholdLimiter;Timing Adjust;To Workspace;TxDataI_In;TxDataI_Out;TxDataOut;TxDataQ_In;TxDataQ_Out;TxDataValidOut;TxData_In;TxData_Out;TxMsgCtrlIn;TxMsgDataOut;TxMsgValidOut;TxValidOut;TxValid_In;TxValid_Out;Underflow;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample;addrValid;avgEst;bitCount;bitErrors;bitReceived;bits;bitsCtrl;bitsOut;bitsValid;channel;char;charOut;charValid;coarseFreq;corr;countOut;ctrlOut;data;data read Address;data write Address;dataActive;dataDone;dataEnd;dataIOut;dataIn;dataOut;dataQOut;dataReady;dataStart;dataValid;datain;dec;displayReset;divide by ;done;e;empty;enable;endIn;endOut;err;estOut;estimate;estimatedCoarseCFO;estin;expOut;extMsgActive;externalDataActive;externalMsg;externalMsgValid;externalRst;frameNumber;full;functionValues;gain;inc;insertCFO;insertCPO;internalRst;interpolant;manualRst;mu;nSynced;ncount;normCoarseFreqEst;normFreqEst;normFreqOut;normalisedFreq;normalisedPhase;normalizedFreqEst;numOfFramesSynced;nxtBit;out;overAir;overAirDataIn;overAirValidIn;packetValid;phaseInc;pickData;pickPreamble;pop;preamble;preambleActive;preambleDone;preambleValid;push;rd;read EOF;readAddr;readEOF;ready;readyToRead;reset;resetcounter;rst;rstCS;rxBus;rxCtrlOut;rxDataOut;rxDiagBus;sample discard controller;scaled;start;startIn;startOut;strobe;success;switch;syncPulse;syncPulseIn;syncPulseOut;tData;tValid;take preamble;takePreamble;threshold;thresholdExceeded;timing Reference;timing Reference Long;timingOffset;timingOffsetValid;tready;txDataOut;txDiagBus;txValidOut;u;userBits;userBitsValid;v;valid;validIn;validOut;wr;write EOF;writeEOF;writeEnb;x;y

BLOCKTYPE:
ArithShift;Assertion;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Complex to Magnitude-Angle;ComplexToRealImag;Constant;ConstellationDiagram;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;Display;DownSample;EnablePort;Extract Bits;EyeDiagram;From;Gain;Goto;HDL Counter;Inport;Logic;LookupNDDirect;Lookup_n-D;Math;MultiPortSwitch;Mux;NCO;Outport;Product;QPSK Demodulator Baseband;QPSK Modulator Baseband;RealImagToComplex;RelationalOperator;Repeat;S-Function;Scope;Serializer1D;SignalSpecification;Simple Dual-port RAM;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample

BLOCKTYPE_FREQUENCY:
1;3;2;1;4;4;4;3;2;23;2;6;17;2;45;2;365;8;3;1;9;6;9;1;2;10;2;26;230;43;4;2;8;3;1;3;203;19;1;1;1;4;14;8;1;1;1;2;25;12;21;6;24;12;10

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Embedded Coder;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_QPSK_hostUDPReceive
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_QPSK_hostUDPReceive.slx
BLOCKTYPE_FREQUENCY: 2;2;1;1;7;1;4;3;1;6;11;1;1;4;1;1;1;1;3
CHECKSUM: D04DADAF2C2D8C52A7A5919391FD37F8
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
2^32-1 will be treated as NaN in double when converted to double Copyright 2023 The MathWorks, Inc.  QPSK Transmit and Receive Host UDP Receive Model

BLOCK:
 Demux ; Receive Message; SFunction ; Terminator ;Bit Slice;Compare To Constant;Constant;Constellation Diagram;Data Type Conversion;Display;Enable;Gain;In;Length;MATLAB Function;Real-Imag to Complex;Reference;Selector;Serializer1D;Status Signals;StatusSignals;SubSystem;Subsystem;Switch;UDP Receive Constellation;UDP Receive Message;UDP Receive Status;Visualize Constellation;bitErrors;bit_Errors;bit_errors;bitsReceived;bits_Received;captureASCII;estimatedCoarseCFO;estimated_CoarseCFO;numOfFrameSynced;num_OfFramesSynced;packetBits;printData;u

BLOCKTYPE:
Bit Slice;Compare To Constant;Constant;ConstellationDiagram;DataTypeConversion;Demux;Display;EnablePort;Gain;Inport;Outport;RealImagToComplex;S-Function;Selector;Serializer1D;Switch;Terminator;ToWorkspace;UDP Receive


MODELNAME: soc_QPSK_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_QPSK_proc.slx
BLOCKTYPE_FREQUENCY: 4;1;1;1;8;6;1;1;1;24;2;3;34;4;6;3;1;1;3;4;4;1;1
CHECKSUM: 5F59E5DEFA8D81F0373189FD61E25368
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Select RF data (1) or FPGA data (0)  The burst data sent from the processing system will be stored in the RAM in the memory channel of SDR IIO radio. The data stored will be poped out as a stream data.   This subsystem does an equivalent operation to simulate the input and output behaviour of the memory channel of the SDR IIO radio. stream write

BLOCK:
Asynchronous Task Specification;Bit Concat;Burst Data;Burst to Stream Conversion Equivalent;CFO;CPO;Cast To Double;Complex to Real-Imag;Constant;Constellation Read ;Constellation Read Event;Constellation done;ConstellationData;ConstellationMsg;Data Type Conversion;Decoded Msg Read Event;DecodedMsg;DecodedMsg Read;DecodedMsg done;DecodedMsgData;Delay;Enable;Event Listener;Event driven;External Message;In;Initialize Function;Logical Operator;Manual Switch;Reference;Register Read;Register Write;Stream Read;Stream Write;SubSystem;Subsystem;Switch;Terminator;TxMsg;TxMsg Read ;TxMsg Read Event;TxMsg Write ;TxMsg Write Event;TxMsg done;TxMsgData;TxMsgWrite done;TxWrite dataout;UDP Write;Vector Concatenate;Zynq and FMCOMMS2/3/4 Receiver;Zynq and FMCOMMS2/3/4 Transmitter;bitErrors;bitsReceived;burstDataIn;data;displayReset;display_Reset;done;enbExt;estimatedCoarseCFO;externalDataActive;external_DataActive;external_DataActiveToggle;initial reset;insertCFO;insertCPO;insert_CFO;insert_CPO;msg;numOfFramesSynced;overAir;rstCS;rst_CS;statusUDPReport;streamDataIOut;streamDataQOut

BLOCKTYPE:
AsynchronousTaskSpecification;Bit Concat;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;EnablePort;EventListener;Inport;Logic;ManualSwitch;Outport;Register Read;Register Write;Stream Read;Stream Write;Switch;Terminator;TriggerPort;UDP Write;comm.internal.SDRRxZC706FMC234RFSL;comm.internal.SDRTxZC706FMC234RFSL

PRODUCT:
Embedded Coder;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_QPSK_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_QPSK_top.slx
BLOCKTYPE_FREQUENCY: 1;1;3;2;1;3;1;1;6;4;24;2;15;1;1;1;1;1;1;5;1;4
CHECKSUM: 6B0807BF8B5C354E72466F7433C22AB4
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_QPSK_fpga.slx___Model_Block___soc_QPSK_proc.slx___Model_Block___
ANNOTATION:
 Copyright 2020 The MathWorks, Inc.  QPSK Transmit and Receive  FPGA Memory Processor External I/O  Copyright 2023 The MathWorks, Inc. External I/O

BLOCK:
 Demux ; SFunction ; Terminator ;AD9361Rx;AD9361Tx;Bit Slice;Channel;Constellation Diagram;Constellation Stream to Software;Constellation done;ConstellationData;ConstellationMsg;ConstellationReadTaskEvent;Data Type Conversion;Decoded Msg Stream to Software;DecodedMsg;DecodedMsg done;DecodedMsgData;DecodedMsgReadTaskEvent;Enable;ExternalMsg to PL Stream;FPGA Algorithm;IO Data Sink;In;MATLAB Function;Processor;Processor-Frame based processing;RFIn;RFOut;Real-Imag to Complex;Reference;Register Write;RxConstellation UDP Write;RxDecodedMsg UDP Write;Serializer1D;Simple delay channel;Status UDP Write;SubSystem;Task Manager;Terminator;Tx Msg Stream to Software;TxDataReadTaskEvent;TxDataWriteTaskEvent;TxMessage UDP Write;TxMsg;TxMsg done;TxMsgData;TxMsgWrite done;TxWrite dataout;UDP Write;UDP Write ;Visualize Constellation;bitErrors;bitsReceived;captureASCII;data;displayReset;estimatedCoarseCFO;externalDataActive;insertCFO;insertCPO;numOfFramesSynced;overAir;packetBits;printData;rstCS;statusUDPReport;u

BLOCKTYPE:
AD9361 Rx Playback;AD9361 Tx Playback;AXI4-Stream to Software;Bit Slice;ConstellationDiagram;DataTypeConversion;Delay;Demux;EnablePort;IO Data Sink;Inport;ModelReference;Outport;RealImagToComplex;Register Channel;S-Function;Serializer1D;Software to AXI4-Stream;Task Manager;Terminator;ToWorkspace;UDP Write

PRODUCT:
Communications Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_aurora_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_aurora_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;2;5;2;1;10;1;3;3;9;3;1;15;4;1;3;1
CHECKSUM: 670F98385F9C61FB9E6F369D86B73ECE
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Bitconcat  As processor needs time in the order of milliseconds to complete a task, down sampling the data rate to meet the processor task duration.  Copyright 2022 The MathWorks, Inc.

BLOCK:
ADC Capture;AND;Add;Aurora 64B66B;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Constant;Counter Limited;DAC Tone Generation;Data Type Conversion;Delay;Downsampler;Enable;IP Core Register Read;Logical Operator;NCO;Reference;Selector;SubSystem;Subsystem;Terminator;Trigger;Write To Processor;adcData;adcTdata;adcTvalid;adcValid;captureDataOut;chCtrlIn;chCtrlOut;chData;chValid;count;dacData;dacValid;loopback;shift 16 bits;shift 32 bits;shift 48 bits;y

BLOCKTYPE:
Aurora 64B66B;Bit Concat;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Constant;Counter Limited;DataTypeConversion;Delay;EnablePort;Gain;IP Core Register Read;Inport;Logic;NCO;Outport;Selector;Sum;Terminator;TriggerPort


MODELNAME: soc_aurora_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_aurora_proc.slx
BLOCKTYPE_FREQUENCY: 1;1;3;5;1;4;2;3;4;3;5;1;1;1;1
CHECKSUM: 6D2A865DE8014C8B802C363608005E79
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Phase increment value for the corresponding sinusoidal tone frequency.  Bit slicing the input 64bit stream data into 4 16bit samples.  Reshaping the frame data to arrange it in a column vector of consecutive samples. Copyright 2020 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Constant;Data Type Conversion;DataIn;DataOut;DataTask;Event Listener;Extract Bits;Gain;Initialize Function;Processor Algorithm Wrapper;Reference;Register Write;Reshape;Slider Gain;Stream Read;SubSystem;Terminator;Trigger;Vector Concatenate;dataIn;dataOut;done

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;EventListener;Extract Bits;Gain;Inport;Outport;Register Write;Reshape;Slider Gain;Stream Read;Terminator;TriggerPort


MODELNAME: soc_aurora_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_aurora_top.slx
BLOCKTYPE_FREQUENCY: 1;1;2;2;2;1;1;1;2;1
CHECKSUM: 308E131D0F51035ED713F16038F40FF2
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_aurora_fpga.slx___Model_Block___soc_aurora_proc.slx___Model_Block___
ANNOTATION:
RF I/O IO Data/ Test bench Processor FPGA Memory  Copyright 2022 The MathWorks, Inc.  Transmit and Receive a Tone Using Aurora on RFSoC Device

BLOCK:
ADC Captured Scope Output;ADC Captured Signal;AXI4-Stream to Software;DAC Output;Delay;FPGA Data Capture;Processor;Processor - Frame based processing;RF Data Converter;Rate Transition;Reference;SubSystem;Task Manager;dataIn;dataOut;dataTask;done

BLOCKTYPE:
AXI4-Stream to Software;Delay;Inport;ModelReference;Outport;RF Data Converter;RateTransition;Scope;SpectrumAnalyzer;Task Manager


MODELNAME: soc_datacapture_4x4IQ_hostio
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4IQ_hostio.slx
BLOCKTYPE_FREQUENCY: 1;8;1;1;2;11;15;1;1;2;1;1;2;1;5;2;3;1;10;1;1;2;1;2;1;1;1;1;12;1
CHECKSUM: 39C230F0554E729EF730D7127A9ED9AE
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
4x4 IQ ADC/DAC Data capture model for host PC This model demonstrates capturing data from the FPGA for IQ mixer data. AXI4 register is used to switch between different ADC channels and collect frames of data at every time step of the simulation The DAC is driven by an NCO. Its frequency is also adjustable from this model as well. 

ANNOTATION:
 Select ADC Channels 0 - ADC Ch1 1 - ADC Ch2 2 - ADC Ch3 3 - ADC Ch4  If this is &gt;0 it means we lost samples internal DUT FIFO overflowed FIFO / AXI4 Stream MM2S monitor Stream Control NCO Control / Scaling  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Host Interface Model - 4x4 IQ Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC Captured Imaginary Out;ADC Captured Real Out;ADC Captured Scope Out;ADC_Channel_Select_AXI;ADC_Select;AXI4 Register IIO Write;AXI4- Stream IIO Read;AXI4TriggerCapture;Add;Bit Slice;Compare To Constant;Complex to Real-Imag;Constant;DAC1_ScaleVal;DAC2_ScaleVal;DAC3_ScaleVal;DAC4_ScaleVal;DAC_Concat;DAC_Scale;Data Type Conversion;DebugSource;Debug_Source;Delay;Display_Concat;Enable;FIFO_AlmostFullCount;Format_I;Format_Q;FramesCollected;Freq (MHz);From;Gain;Goto;Logical Operator;MHzScale;NCOFreq;NOT;PS_AutoTrigger;Pl_AutoTrigger;Read_Almost_Full;Real-Imag to Complex;Reference;Reshape;Selector;Simulink Function;StreamEn;SubSystem;TriggerFrequency;Vector Concatenate;dataIn;dataOut;dispIn;en;frameSize;iIn;iOut;qIn;qOut;u

BLOCKTYPE:
ArgIn;Bit Slice;Compare To Constant;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Display;EnablePort;From;Gain;Goto;Inport;Logic;Outport;RealImagToComplex;Reshape;S-Function;Scope;Selector;Slider Gain;SpectrumAnalyzer;Sum;Terminator;TriggerPort;soc.libiio.aximm.ReadHost;soc.libiio.aximm.WriteHost;soc.libiio.axistream.ReadHost


MODELNAME: soc_datacapture_4x4IQ_zcu111_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4IQ_zcu111_fpga.slx
BLOCKTYPE_FREQUENCY: 3;4;1;1;6;4;11;1;6;35;1;2;1;16;3;5;2;1;107;37;2;1;4;73;8;2;1;3;8;10;2;4
CHECKSUM: 3E306F06C8170E0DB832ABCC7B2174E9
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
HDL model for RFSoC ADC/DAC IQ 8x8 interfacing with the mixer enabled This model contains demonstrates how to interface to all 8 ADC and 8 DAC channels for the RFSoC. Please ensure that you run the initialization script to set the correct PLL clock rates. 

ANNOTATION:
Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input From RFDC ADC Tile1 Ch1/Ch2 DAC Tile 1: Ch1, 2, 3, 4 AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Tile 0 Ch1/Ch2 Copyright 2020 The MathWorks, Inc.

BLOCK:
ADC;AFull;AXI4_AFIFO_Full;AXIS_FIFO_Full;AXIS_FIFO_Num;Add;AlmostFull;AutoTrigEn;AutoTrigger;BackPressureCounterEn;Bit Concat;Bus Creator;Bus Selector;Ch;ChOut;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;Count;CountBackPressure;Data Type Conversion;DataCaptureEn;DataPushFrequency;DataSource;DebugSource;DefaultConsecFrames;DefaultRegister;Delay;Demux;Detect Increase;Display;EnableConsecutiveFrames;FWFT_FIFO;FrameSizeInput;From;Gain;GainScale;Goto;HDL Counter;HDL FIFO;IQ_SelectCh;I_Samples;In;Increment;Logical Operator;MM2S_Data;MM2S_Ready;MM2S_Valid;MaxCount;Multiport Switch;Mux;NCO HDL Optimized;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_Transmit;NCO_Vector_DAC0_I;NCO_Vector_DAC0_Q;NCO_incr_AXI;Out;PortSelect;Product;Q;Q_Samples;R;Reference;Relational Operator;RouteADC;S;S2MM_Data;S2MM_Tready;S2MM_Valid;SW_en;Sample;Sample1_I;Sample1_Q;Sample2_I;Sample2_Q;Sample3_I;Sample3_Q;Sample4_I;Sample4_Q;Scale;ScaleCh;Select;Signal Specification;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Tile0_Ch0_IQ_ValidIn;Tile0_Ch0_I_DataIn;Tile0_Ch0_Q_DataIn;Tile0_Ch1_IQ_ValidIn;Tile0_Ch1_I_DataIn;Tile0_Ch1_Q_DataIn;Tile1_Ch0_IQ_Valid;Tile1_Ch0_IQ_ValidIn;Tile1_Ch0_I_Data;Tile1_Ch0_I_DataIn;Tile1_Ch0_Q_Data;Tile1_Ch0_Q_DataIn;Tile1_Ch1_IQ_Valid;Tile1_Ch1_IQ_ValidIn;Tile1_Ch1_I_Data;Tile1_Ch1_I_DataIn;Tile1_Ch1_Q_Data;Tile1_Ch1_Q_DataIn;Tile1_Ch2_IQ_Valid;Tile1_Ch2_I_Data;Tile1_Ch2_Q_Data;Tile1_Ch3_IQ_Valid;Tile1_Ch3_I_Data;Tile1_Ch3_Q_Data;Transmit and Receive Tone;Trig;Trigger;TriggerCapture;TriggerFreq;Unit Delay;Valid;ValidOut;afull;cache_reg;data_i;data_o;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sr_latch

BLOCKTYPE:
Bit Concat;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;Mux;NCO;Outport;Product;RelationalOperator;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_datacapture_4x4IQ_zcu111_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4IQ_zcu111_top.slx
BLOCKTYPE_FREQUENCY: 2;10;1;1;2;1;2;20;1;21;3;1;2;11;4;5;13;2;3;1;12;2;1;1;1;1;1;1;12
CHECKSUM: C0B2E9F723B5651E697A3FCD23C8297E
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_datacapture_4x4IQ_zcu111_fpga.slx___Model_Block___
DESCRIPTION:
HDL model for RFSoC ADC/DAC IQ 8x8 interfacing with the mixer enabled This model contains demonstrates how to interface to all 8 ADC and 8 DAC channels for the RFSoC. Please ensure that you run the initialization script to set the correct PLL clock rates. 

ANNOTATION:
0 - no debug source 1 - debug source  Select 0 - Ch1 IQ 1 - Ch2 IQ  NCO Tone Adjustment  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;<IQ>;ADC Captured Scope Out;ADC Captured Spectrum Out;ADC0_Valid;AXI4Stream_DMA_MM2S;AXI4Stream_DMA_S2MM;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CompactBits;Compare To Constant;Complex to Real-Imag;Constant;Data Type Conversion;DebugSource;Demux;Enable;FIFO_Full;FPGA;FixPt Data Type Propagation;Freq (MHz);From;Gain;Goto;In;Incr;Logical Operator;MATLAB Function;Manual Switch;NCO Tone Adjust;OFF;ON;Out;PlotData;Real-Imag to Complex;Reference;SelectCh;Signal Specification;Sine Wave;StreamEn;SubSystem;Subsystem;TData;Terminator;Tlast;Vector Concatenate;iDataIn;iDataOut;mm2sData;mm2sValid;packed_in;qDataIn;qDataOut;s2mmData;s2mmReady;s2mmValid;scale;tData;vector_out

BLOCKTYPE:
Bit Concat;Bit Slice;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Concatenate;Constant;Data Type Propagation;DataTypeConversion;Demux;Display;EnablePort;From;Gain;Goto;Inport;Logic;ManualSwitch;ModelReference;Outport;RealImagToComplex;S-Function;Scope;SignalSpecification;Sine Wave;Slider Gain;SpectrumAnalyzer;Terminator

PRODUCT:
DSP System Toolbox;Embedded Coder;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_datacapture_4x4IQ_zcu216_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4IQ_zcu216_fpga.slx
BLOCKTYPE_FREQUENCY: 3;4;1;1;6;4;11;1;6;35;1;2;1;16;3;5;2;1;107;37;2;1;4;73;8;2;1;3;8;10;2;4
CHECKSUM: 894DA39C4279E18752486722733047A3
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
HDL model for RFSoC ADC/DAC IQ 8x8 interfacing with the mixer enabled This model contains demonstrates how to interface to all 8 ADC and 8 DAC channels for the RFSoC. Please ensure that you run the initialization script to set the correct PLL clock rates. 

ANNOTATION:
Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input From RFDC ADC Tile1 Ch1/Ch2 DAC Tile 1: Ch1, 2, 3, 4 AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Tile 0 Ch1/Ch2 Copyright 2020 The MathWorks, Inc.

BLOCK:
ADC;AFull;AXI4_AFIFO_Full;AXIS_FIFO_Full;AXIS_FIFO_Num;Add;AlmostFull;AutoTrigEn;AutoTrigger;BackPressureCounterEn;Bit Concat;Bus Creator;Bus Selector;Ch;ChOut;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;Count;CountBackPressure;Data Type Conversion;DataCaptureEn;DataPushFrequency;DataSource;DebugSource;DefaultConsecFrames;DefaultRegister;Delay;Demux;Detect Increase;Display;EnableConsecutiveFrames;FWFT_FIFO;FrameSizeInput;From;Gain;GainScale;Goto;HDL Counter;HDL FIFO;IQ_SelectCh;I_Samples;In;Increment;Logical Operator;MM2S_Data;MM2S_Ready;MM2S_Valid;MaxCount;Multiport Switch;Mux;NCO HDL Optimized;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_Transmit;NCO_Vector_DAC0_I;NCO_Vector_DAC0_Q;NCO_incr_AXI;Out;PortSelect;Product;Q;Q_Samples;R;Reference;Relational Operator;RouteADC;S;S2MM_Data;S2MM_Tready;S2MM_Valid;SW_en;Sample;Sample1_I;Sample1_Q;Sample2_I;Sample2_Q;Sample3_I;Sample3_Q;Sample4_I;Sample4_Q;Scale;ScaleCh;Select;Signal Specification;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Tile0_Ch0_IQ_Valid;Tile0_Ch0_IQ_ValidIn;Tile0_Ch0_I_Data;Tile0_Ch0_I_DataIn;Tile0_Ch0_Q_Data;Tile0_Ch0_Q_DataIn;Tile0_Ch1_IQ_Valid;Tile0_Ch1_IQ_ValidIn;Tile0_Ch1_I_Data;Tile0_Ch1_I_DataIn;Tile0_Ch1_Q_Data;Tile0_Ch1_Q_DataIn;Tile0_Ch2_IQ_Valid;Tile0_Ch2_IQ_ValidIn;Tile0_Ch2_I_Data;Tile0_Ch2_I_DataIn;Tile0_Ch2_Q_Data;Tile0_Ch2_Q_DataIn;Tile0_Ch3_IQ_Valid;Tile0_Ch3_IQ_ValidIn;Tile0_Ch3_I_Data;Tile0_Ch3_I_DataIn;Tile0_Ch3_Q_Data;Tile0_Ch3_Q_DataIn;Transmit and Receive Tone;Trig;Trigger;TriggerCapture;TriggerFreq;Unit Delay;Valid;ValidOut;afull;cache_reg;data_i;data_o;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sr_latch

BLOCKTYPE:
Bit Concat;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;Mux;NCO;Outport;Product;RelationalOperator;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_datacapture_4x4realDDR_hostio
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4realDDR_hostio.slx
BLOCKTYPE_FREQUENCY: 1;4;1;11;10;1;1;5;1;2;3;1;1;1;5;1;2;1;1;1;1;1;4;11;1
CHECKSUM: 734788E38E8B8BA9339CFC65FD296F64
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
8x8 ADC/DAC Data capture model for host PC This model demonstrates capturing data from the FPGA. AXI4 register is used to switch between different ADC channels and collect frames of data at every time step of the simulation The DAC is driven by an NCO. Its frequency is also adjustable from this model as well. 

ANNOTATION:
Select ADC Channels 1 through 4 here  If this is &gt;0 it means we lost samples internal DUT FIFO overflowed FIFO / AXI4 Stream MM2S monitor Stream Control NCO Control / Scaling Copyright 2020 The MathWorks, Inc.  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Host Interface Model - 4x4 Real DDR4  Selecting ADC Channels 0 - ADC Ch1 1 - ADC Ch2 2 - ADC Ch3 3 - ADC Ch4 

BLOCK:
 Demux ; SFunction ; Terminator ;ADC Captured Scope Out;ADC Captured Spectrum Out;ADC_Channel;ADC_Channel_Select_AXI;AXI4 Register IIO Write;AXI4- Stream IIO Read;AXI4TriggerCapture;Add;Bit Slice;Constant;DAC1_ScaleVal;DAC2_ScaleVal;DAC3_ScaleVal;DAC4_ScaleVal;DAC_Scale;Data Type Conversion;Delay;DisplayData;Enable;FIFO_AlmostFullCount;FIFO_Full;FIFO_Num;FormatData;Frame Size;Frame Valid;FramesCollected;Freq (MHz);Gain;MHzScale;Manual Switch;NCOFreq;NOT;PS_AutoTrigger;Read_Almost_Full;Read_FIFO_Full;Read_FIFO_Num;Read_Tready_Low_Count;Reference;ResetDUT;Reshape;S2MM_TreadyLowCount;Simulink Function;StreamEn;SubSystem;Trigger Mode;Vector Concatenate;dataIn;dataOut;dispData;en;u

BLOCKTYPE:
ArgIn;Bit Slice;Concatenate;Constant;DataTypeConversion;Delay;Demux;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;Outport;Reshape;S-Function;Scope;Slider Gain;SpectrumAnalyzer;Sum;Terminator;TriggerPort;soc.libiio.aximm.ReadHost;soc.libiio.aximm.WriteHost;soc.libiio.axistream.ReadHost


MODELNAME: soc_datacapture_4x4realDDR_zcu111_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4realDDR_zcu111_fpga.slx
DESCRIPTION: HDL model for RFSoC ADC/DAC DDR4 data capture
BLOCKTYPE_FREQUENCY: 5;2;1;6;2;2;6;10;2;16;62;3;4;1;45;3;31;2;2;155;66;1;4;153;16;1;3;4;1;13;9;15;4;7
CHECKSUM: F32A04CDB6D68A9D576BFBB7B1B90384
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input This will wait for WrReady to go online first before enabling TriggerOut Ignore Trigger Captures if we are still reading DDR out  AXI4 MM Writes AXI4 MM Diagonstics axim_rd_m2s - DDR Read AXI4 Stream Master DMA  axim_rd_s2m - DDR Read Ack axim_wr_m2s - DDR Write axim_wr_s2m - DDR Write Ack Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Check to see if TLAST pulse got lost in the FIFO due to overflows. If there is a constant difference then it means TLAST was dropped due to back-pressure and the FIFO filling up to capacity. The AXIS frame is now corrupted Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Tile 1 & 2 for DAC AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Channel 0 AXI4 MM Read Registers Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;<wr_complete>;ADC_Data;ADC_SelectCh;ADC_Valid;AXI4S_Master_FIFO ;AXI4Trigger;AXI4_AXI4S_TlastCheck;AXI4_AccumulatedWrRdyCount;AXI4_AckLow_Count;AXI4_CaptureFIFONum;AXI4_FIFOCapture_Overflow;AXI4_FIFODMA_Overflow;AXI4_ReadCompleteCount;AXI4_S2MM_TreadyLowCount;AXI4_Trigger;AXI4_WastedWriteCycles;AXI4_WriteCompleteCount;AXIS_DMA_FIFO_AFull;AXIS_Data;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;AXIS_Valid;Add;AlmostFull;BckPrssre;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CaptureFIFONum;CaptureFIFONumReg;CaptureOverflowCount;CaptureValid;Ch;ChOut;Compare To Constant;Compare To Zero;Constant;CounterOut;DDR Read Conroller;DDR Write Conroller;DDRWrStart;DDR_Capture_Logic;DDR_WrStart;DDR_Wr_Comp;Data Type Conversion;DataCaptureEn;DataCaptureLogic;DebugCapture;DebugCaptureDefaultReg;DebugCaptureRegister;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;FIFOCapture_Afull;FIFO_AFull;FIFO_DataAvail;FrameSize;FrameSizeDefaultReg ;FrameSizeInput;From;Gain;Goto;HDL Counter;HDL FIFO;In;Increment;Logical Operator;MATLAB Function;MM2S_Data;MM2S_Ready;MM2S_Valid;Multiport Switch;NCO HDL Optimized;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_Process;NCO_Valid;NCO_Vector_DAC;NCO_incr_AXI;NOT;Out;OverflowCaptureCount;OverflowDMACount;PortSelect;Product;Q;R;ReadCompleteCount;ReadDone;Ready;Reference;Relational Operator;Reset;RouteADC;Rst;S;S2MM_Data;S2MM_TLast;S2MM_Tready;S2MM_TreadyLowCount;S2MM_Valid;Scale;ScaleCh;Signal Conversion;Signal Specification;SoC Bus Selector;StreamEn;SubSystem;Subsystem;Switch;TLAST_Check;TLAST_Out;TLastTAG;Terminator;Tile0_ADC0_Data;Tile0_ADC0_Valid;Tile0_ADC1_Data;Tile0_ADC1_Valid;Tile1_ADC0_Data;Tile1_ADC0_Valid;Tile1_ADC1_Data;Tile1_ADC1_Valid;Tile1_DAC0_Data;Tile1_DAC0_Valid;Tile1_DAC1_Data;Tile1_DAC1_Valid;Tile1_DAC2_Data;Tile1_DAC2_Valid;Tile1_DAC3_Data;Tile1_DAC3_Valid;ToggleTLAST;Transmit and Receive Tone;Trigger;TriggerCapture;TriggerOut;Unit Delay;Valid;ValidateTLAST;WastedWriteCycles;WrNotRdy;WrReady;WrValid;WriteCompleteCount;afull;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_rd_valid;axim_wr_data;axim_wr_m2s;axim_wr_s2m;axis_master_ready;burst_len;cache_reg;capture_fifo_num;capture_fifo_rd_ack;count_out;data_i;data_o;ddr_read_done;ddr_write_done;debug_state;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;ram_addr;rd_ack;rd_ack_i;rd_ack_low_count;rd_addr;rd_aready;rd_avalid;rd_dvalid;rd_len;sr_latch;start;valid_out;wasted_cycle_cnt;wr_addr;wr_complete;wr_data;wr_len;wr_rdy;wr_rdy_counter;wr_ready;wr_valid

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;NCO;Outport;Product;RelationalOperator;S-Function;SignalConversion;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay

PRODUCT:
DSP HDL Toolbox;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_datacapture_4x4realDDR_zcu111_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4realDDR_zcu111_top.slx
DESCRIPTION: HDL model for RFSoC ADC/DAC DDR4 data capture
BLOCKTYPE_FREQUENCY: 5;1;12;4;5;4;2;20;1;38;20;9;1;1;13;3;8;5;3;1;1;75;31;1;3;1;1;61;2;1;5;3;1;1;1;1;1;1;5;2;22;2;4
CHECKSUM: CECA4388FC963BC500E500FD4459ADD2
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_datacapture_4x4realDDR_zcu111_fpga.slx___Model_Block___
ANNOTATION:
This subsystem will artifically induce wr_ready toggling behavior AXI4 Data Capture Trigger  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ; ackIn==;<rd_avalid>;<rd_len>;ADC Captured Scope Out;ADC0_Tready;ADC0_Valid;AXI4Stream_DMA_MM2S;AXI4Stream_DMA_S2MM;AckGen;Add;Bit Concat;Bit Shift;Bit Slice;Bus Creator;Bus Selector;CaptureADC_Data;CaptureRamp_Data;CompactBits;Compare To Constant;Constant;DAC_Output_Tile;DDR;Data;Data Type Conversion;Delay;Demux;Detect Increase;DetectWrLen;Display;DoneLoading;Enable;FPGA;FrameCount;FrameSize;Freq (MHz);From;Gain;Goto;HDL FIFO;In;Incr;Logical Operator;MATLAB Function;MATLAB System;Manual Switch;Mod;ModDiv;NCO Tone Adjust;OFF;ON;Out;PlotDACData;PlotData;Pulse Generator;Q;R;RdCmdQueue;Reference;Repeating Sequence Stair;S;SampleCount;ShouldBeMultipleOfFrameSize;ShouldDisplayZero;Signal Conversion;Signal From Workspace;Sine Wave;Stop Simulation;StopAtTLast;StreamEn;SubSystem;Subsystem;Switch;TData;TLAST;TLast;TREADY;TValid;Terminator;Tile1 DAC Scope Out;Tile1 DAC Spectrum Out;Time Scope;ToPlot;ToggleWrReady;Unit Delay;ValAddEnb;ValidIn;Valid_in;Validate_DataTransfer;ValwrLenCnt;Vector Concatenate;WrRdy;WrReadyCount;WrReadySim;Wr_control;ack;ackIn;ackIn Posedge Detect;ackIn_d;ackIn_d1==;ackOut;afull;axiWrLen;axiWrLen!=;axiWrLen-1==cnt & axiWrLen!=0 ;axiWrLen==cnt+;axi_addr;axi_rd_add;axi_rd_data;axi_rd_dready;axi_rd_len;axi_rd_m2s;axi_rd_ready;axi_rd_s2m;axi_rd_val;axi_wr_ack;axi_wr_add;axi_wr_data;axi_wr_en;axi_wr_enb;axi_wr_len;axi_wr_length;axi_wr_m2s;axi_wr_s2m;axi_wr_val;axim_ack;axim_rd_addr;axim_rd_addr_FIFO;axim_rd_aready;axim_rd_aready_behavior;axim_rd_avalid;axim_rd_avalid_FIFO;axim_rd_dvalid;axim_rd_len;axim_rd_len_FIFO;cache_reg;dacData;data_i;data_o;ddr_ack_d;ddr_rdy;ddr_ready;ddr_reday_d;ddr_wr_rdy;dtci;edgeDet;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;if cnt < axiWrLen;load_done;load_init_data;num;num_i;num_o;out_reg;pop_o;push;ram_addr;ram_rd_addr;ram_rd_val;ram_wr_add;ram_wr_addr;ram_wr_data;ram_wr_enb;ram_wr_enb cond;rdDone;rdDonePulse;rdLogic;rd_ack;rd_ack_i;rd_control;rd_done;rd_rdy;rdy_out;rst;scale;sr_latch;valAddEnb;wrEnb;wrLogic;wr_ack;wr_addr-;wr_enb;wr_len;wr_leng

BLOCKTYPE:
Bit Concat;Bit Shift;Bit Slice;BusCreator;BusSelector;Compare To Constant;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;DiscretePulseGenerator;Display;EnablePort;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MATLABSystem;ManualSwitch;Math;ModelReference;Outport;RelationalOperator;Repeating Sequence Stair;S-Function;Scope;Signal From Workspace;SignalConversion;Sine Wave;Slider Gain;SpectrumAnalyzer;Stop;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay

PRODUCT:
DSP System Toolbox;Embedded Coder;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_datacapture_4x4realDDR_zcu216_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_4x4realDDR_zcu216_fpga.slx
DESCRIPTION: HDL model for RFSoC ADC/DAC DDR4 data capture
BLOCKTYPE_FREQUENCY: 5;2;1;6;2;2;6;10;2;16;62;3;4;1;45;3;31;2;2;155;66;1;4;153;16;1;3;4;1;13;9;15;4;7
CHECKSUM: FE31ABC85E7628DF96CF64ECDB934F5C
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input This will wait for WrReady to go online first before enabling TriggerOut Ignore Trigger Captures if we are still reading DDR out  AXI4 MM Writes AXI4 MM Diagonstics axim_rd_m2s - DDR Read AXI4 Stream Master DMA  axim_rd_s2m - DDR Read Ack axim_wr_m2s - DDR Write axim_wr_s2m - DDR Write Ack Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Check to see if TLAST pulse got lost in the FIFO due to overflows. If there is a constant difference then it means TLAST was dropped due to back-pressure and the FIFO filling up to capacity. The AXIS frame is now corrupted Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Tile 1 & 2 for DAC AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Channel 0 AXI4 MM Read Registers Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;<wr_complete>;ADC_Data;ADC_SelectCh;ADC_Valid;AXI4S_Master_FIFO ;AXI4Trigger;AXI4_AXI4S_TlastCheck;AXI4_AccumulatedWrRdyCount;AXI4_AckLow_Count;AXI4_CaptureFIFONum;AXI4_FIFOCapture_Overflow;AXI4_FIFODMA_Overflow;AXI4_ReadCompleteCount;AXI4_S2MM_TreadyLowCount;AXI4_Trigger;AXI4_WastedWriteCycles;AXI4_WriteCompleteCount;AXIS_DMA_FIFO_AFull;AXIS_Data;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;AXIS_Valid;Add;AlmostFull;BckPrssre;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CaptureFIFONum;CaptureFIFONumReg;CaptureOverflowCount;CaptureValid;Ch;ChOut;Compare To Constant;Compare To Zero;Constant;CounterOut;DDR Read Conroller;DDR Write Conroller;DDRWrStart;DDR_Capture_Logic;DDR_WrStart;DDR_Wr_Comp;Data Type Conversion;DataCaptureEn;DataCaptureLogic;DebugCapture;DebugCaptureDefaultReg;DebugCaptureRegister;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;FIFOCapture_Afull;FIFO_AFull;FIFO_DataAvail;FrameSize;FrameSizeDefaultReg ;FrameSizeInput;From;Gain;Goto;HDL Counter;HDL FIFO;In;Increment;Logical Operator;MATLAB Function;MM2S_Data;MM2S_Ready;MM2S_Valid;Multiport Switch;NCO HDL Optimized;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_Process;NCO_Valid;NCO_Vector_DAC;NCO_incr_AXI;NOT;Out;OverflowCaptureCount;OverflowDMACount;PortSelect;Product;Q;R;ReadCompleteCount;ReadDone;Ready;Reference;Relational Operator;Reset;RouteADC;Rst;S;S2MM_Data;S2MM_TLast;S2MM_Tready;S2MM_TreadyLowCount;S2MM_Valid;Scale;ScaleCh;Signal Conversion;Signal Specification;SoC Bus Selector;StreamEn;SubSystem;Subsystem;Switch;TLAST_Check;TLAST_Out;TLastTAG;Terminator;Tile0_ADC0_Data;Tile0_ADC0_Valid;Tile0_ADC1_Data;Tile0_ADC1_Valid;Tile0_ADC2_Data;Tile0_ADC2_Valid;Tile0_ADC3_Data;Tile0_ADC3_Valid;Tile0_DAC0_Data;Tile0_DAC0_Valid;Tile0_DAC1_Data;Tile0_DAC1_Valid;Tile0_DAC2_Data;Tile0_DAC2_Valid;Tile0_DAC3_Data;Tile0_DAC3_Valid;ToggleTLAST;Transmit and Receive Tone;Trigger;TriggerCapture;TriggerOut;Unit Delay;Valid;ValidateTLAST;WastedWriteCycles;WrNotRdy;WrReady;WrValid;WriteCompleteCount;afull;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_rd_valid;axim_wr_data;axim_wr_m2s;axim_wr_s2m;axis_master_ready;burst_len;cache_reg;capture_fifo_num;capture_fifo_rd_ack;count_out;data_i;data_o;ddr_read_done;ddr_write_done;debug_state;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;ram_addr;rd_ack;rd_ack_i;rd_ack_low_count;rd_addr;rd_aready;rd_avalid;rd_dvalid;rd_len;sr_latch;start;valid_out;wasted_cycle_cnt;wr_addr;wr_complete;wr_data;wr_len;wr_rdy;wr_rdy_counter;wr_ready;wr_valid

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;NCO;Outport;Product;RelationalOperator;S-Function;SignalConversion;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay

PRODUCT:
DSP HDL Toolbox;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_datacapture_8x8IQMTS_hostio
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8IQMTS_hostio.slx
BLOCKTYPE_FREQUENCY: 1;8;3;15;20;1;1;2;2;4;2;10;1;1;2;1;2;1;1;1;1;15;1
CHECKSUM: 3BBA6DDE67BD610F93C089DE9736809D
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
8x8 IQ ADC/DAC Data capture model for host PC MTS Data capture example. Use this to examine the phase alignment accross different channels

ANNOTATION:
Selects I or Q: I = 0 Q = 1  Comparison Channels: 0 to 7  If this is &gt;0 it means we lost samples internal DUT FIFO overflowed FIFO / AXI4 Stream MM2S monitor Stream Control NCO Control / Scaling  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Host Interface Model - 8x8 IQ MTS Copyright 2020 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC Captured Imaginary Spectrum Out;ADC Captured Real Spectrum Out;ADC Captured Scope Out;ADC_Select_ChA;ADC_Select_ChB;AXI4- Stream IIO Read;AXI4TriggerCapture;Add;Bit Slice;Constant;DAC1_ScaleVal;DAC2_ScaleVal;DAC3_ScaleVal;DAC4_ScaleVal;DAC5_ScaleVal;DAC6_ScaleVal;DAC7_ScaleVal;DAC8_ScaleVal;DAC_Concat;DAC_Scale;Data Type Conversion;Delay;FIFO_AlmostFullCount;Format_I;Format_Q;FramesCollected;Freq (MHz);Gain;IQ_Select_I_or_Q ;MHzScale;NCOFreq;PS_AutoTrigger;Read_Almost_Full;Reference;Reshape;Select_ChA;Select_ChB;Select_I_or_Q;Selector;Simulink Function;StreamEn;SubSystem;TriggerCapture;Vector Concatenate;dataIn;en;frameSize;iDataIn;iDataOut;qDataIn;qDataOut;u

BLOCKTYPE:
ArgIn;Bit Slice;Concatenate;Constant;DataTypeConversion;Delay;Demux;Display;Gain;Inport;Outport;Reshape;S-Function;Scope;Selector;Slider Gain;SpectrumAnalyzer;Sum;Terminator;TriggerPort;soc.libiio.aximm.ReadHost;soc.libiio.aximm.WriteHost;soc.libiio.axistream.ReadHost


MODELNAME: soc_datacapture_8x8IQMTS_zcu111_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8IQMTS_zcu111_fpga.slx
BLOCKTYPE_FREQUENCY: 3;11;34;1;9;12;15;1;33;75;1;1;1;23;3;4;1;1;200;37;4;1;4;104;8;1;1;8;1;3;11;8;2;4
CHECKSUM: 0E30575160FF3022B0827C0A95D8E8A4
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
Example MTS model with 8 ADC and DAC channels connected ADC/DAC inports/outports with master/slave DMA connection. To be used for MTS demonstrations which allows alignment of any arbitrary I and Q channel accross all 8 ADC channels (4 tiles). The same DAC NCO waveform is transmitted to all Tiles

ANNOTATION:
Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input AXI4-Stream DMA Slave AXI4-Stream DMA Master Copyright 2020 The MathWorks, Inc.

BLOCK:
AFull;AXI4_AFIFO_Full;AXIS_FIFO_Full;AXIS_FIFO_Num;Add;AlmostFull;BackPressureCounterEn;Bit Concat;Bus Creator;Bus Selector;Ch;ChOut;ChScale;ChSelect_A;ChSelect_B;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;Count;CountBackPressure;DTC_10_;DTC_11_;DTC_12_;DTC_13_;DTC_14_;DTC_15_;DTC_16_;DTC_17_;DTC_18_;DTC_19_;DTC_1_;DTC_20_;DTC_21_;DTC_22_;DTC_23_;DTC_24_;DTC_2_;DTC_3_;DTC_4_;DTC_5_;DTC_6_;DTC_7_;DTC_8_;DTC_9_;Data Type Conversion;DataCaptureEn;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;EnableConsecutiveFrames;FWFT_FIFO;For Each;FrameSizeInput;From;Gain;GainScale;Goto;HDL Counter;HDL FIFO;IQ_Valid;I_Samples;I_or_Q;I_or_Q_select;In;Logical Operator;MultiplyForEachChannel;Multiport Switch;Mux;NCO HDL Optimized;NCOIncrement;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_DAC_Ch4_AXI;NCO_DAC_Ch5_AXI;NCO_DAC_Ch6_AXI;NCO_DAC_Ch7_AXI;NCO_Out;NCO_Transmit;NCO_Vector_DAC_IQ;NCO_incr_AXI;Out;Product;Q;Q_Samples;R;Real-Imag to Complex;Reference;Relational Operator;RouteADC;S;Sample;Sample1_I;Sample1_Q;Sample2_I;Sample2_Q;Sample3_I;Sample3_Q;Sample4_I;Sample4_Q;Scale;Selector;Signal Specification;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Tile0 ADC Mixer Ch0-I Data;Tile0 ADC Mixer Ch0-IQ Valid;Tile0 ADC Mixer Ch0-Q Data;Tile0 ADC Mixer Ch1-I Data;Tile0 ADC Mixer Ch1-IQ Valid;Tile0 ADC Mixer Ch1-Q Data;Tile0 DAC Mixer Ch0-I Data;Tile0 DAC Mixer Ch0-IQ Valid;Tile0 DAC Mixer Ch0-Q Data;Tile0 DAC Mixer Ch1-I Data;Tile0 DAC Mixer Ch1-IQ Valid;Tile0 DAC Mixer Ch1-Q Data;Tile0 DAC Mixer Ch2-I Data;Tile0 DAC Mixer Ch2-IQ Valid;Tile0 DAC Mixer Ch2-Q Data;Tile0 DAC Mixer Ch3-I Data;Tile0 DAC Mixer Ch3-IQ Valid;Tile0 DAC Mixer Ch3-Q Data;Tile1 ADC Mixer Ch0-I Data;Tile1 ADC Mixer Ch0-IQ Valid;Tile1 ADC Mixer Ch0-Q Data;Tile1 ADC Mixer Ch1-I Data;Tile1 ADC Mixer Ch1-IQ Valid;Tile1 ADC Mixer Ch1-Q Data;Tile1 DAC Mixer Ch0-I Data;Tile1 DAC Mixer Ch0-IQ Valid;Tile1 DAC Mixer Ch0-Q Data;Tile1 DAC Mixer Ch1-I Data;Tile1 DAC Mixer Ch1-IQ Valid;Tile1 DAC Mixer Ch1-Q Data;Tile1 DAC Mixer Ch2-I Data;Tile1 DAC Mixer Ch2-IQ Valid;Tile1 DAC Mixer Ch2-Q Data;Tile1 DAC Mixer Ch3-I Data;Tile1 DAC Mixer Ch3-IQ Valid;Tile1 DAC Mixer Ch3-Q Data;Tile2 ADC Mixer Ch0-I Data;Tile2 ADC Mixer Ch0-IQ Valid;Tile2 ADC Mixer Ch0-Q Data;Tile2 ADC Mixer Ch1-I Data;Tile2 ADC Mixer Ch1-IQ Valid;Tile2 ADC Mixer Ch1-Q Data;Tile3 ADC Mixer Ch0-I Data;Tile3 ADC Mixer Ch0-IQ Valid;Tile3 ADC Mixer Ch0-Q Data;Tile3 ADC Mixer Ch1-I Data;Tile3 ADC Mixer Ch1-IQ Valid;Tile3 ADC Mixer Ch1-Q Data;Transmit and Receive Tone;Trigger;TriggerCapture;Unit Delay;ValidOut;afull;axi_mm2s_tdata;axi_mm2s_tready;axi_mm2s_tready_dtc;axi_mm2s_tvalid;axi_s2mm_tdata;axi_s2mm_tdata_dtc;axi_s2mm_tready;axi_s2mm_tvalid;axi_s2mm_tvalid_dtc;cache_reg;data_i;data_o;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sample;scaleFactor;sr_latch

BLOCKTYPE:
Bit Concat;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;Conversion Inherited;DataTypeConversion;Delay;Detect Increase;Display;ForEach;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;Mux;NCO;Outport;Product;RealImagToComplex;RelationalOperator;Selector;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_datacapture_8x8IQMTS_zcu111_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8IQMTS_zcu111_top.slx
BLOCKTYPE_FREQUENCY: 2;26;1;6;21;38;22;2;1;1;2;24;4;3;1;15;2;1;31;3;1;3;1;9;2;1
CHECKSUM: 494CDE13C632E15396BC2D11B99AAD45
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_datacapture_8x8IQMTS_zcu111_fpga.slx___Model_Block___
DESCRIPTION:
Example MTS model with 8 ADC and DAC channels connected ADC/DAC inports/outports with master/slave DMA connection. To be used for MTS demonstrations which allows alignment of any arbitrary I and Q channel accross all 8 ADC channels (4 tiles). The same DAC NCO waveform is transmitted to all Tiles

ANNOTATION:
 ch1qData Trigger every 0.5 sec by default AXI4-MM Write  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Copyright 2020 The MathWorks, Inc.

BLOCK:
ADC Captured Scope Out;ADC0_Valid;Bit Concat;Bit Slice;CompactBits;Compare To Zero;Constant;DAC1 Scope Out;DAC1 Spectrum Out;DAC2 Scope Out;DAC2 Spectrum Out;DACscale;Data Type Conversion;DataPushFrequency;Delay;Demux;Detect Increase;Display;Enable;FPGA;Freq (MHz);From;Gain;Goto;I;In;Incr;Manual Switch;MaxCount;NCO Tone Adjust;OFF;ON;Out;Out22_;PlotData;Q;Real-Imag to Complex;Reference;Relational Operator;SW_en;Sine Wave;Slider Gain;StreamEn;SubSystem;Subsystem;Switch;Trig;Trigger;Trigger Count;Vector Concatenate;axi_mm2s_tdata;axi_mm2s_tdata_dtc;axi_mm2s_tready_dtc;axi_mm2s_tvalid;axi_mm2s_tvalid_dtc;axi_s2mm_tready;ch1dacIData;ch1dacIDataOut;ch1qData;ch1qDataOut;iDataIn;iDataOut;qDataIn;qDataOut;s2mmData;s2mmValid

BLOCKTYPE:
Bit Concat;Bit Slice;Compare To Zero;Concatenate;Constant;DataTypeConversion;Delay;Demux;Detect Increase;Display;EnablePort;From;Gain;Goto;HDL Counter;Inport;ManualSwitch;ModelReference;Outport;RealImagToComplex;RelationalOperator;Scope;Sine Wave;Slider Gain;SpectrumAnalyzer;Switch


MODELNAME: soc_datacapture_8x8IQMTS_zcu216_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8IQMTS_zcu216_fpga.slx
BLOCKTYPE_FREQUENCY: 3;11;34;1;9;12;15;1;33;75;1;1;1;23;3;4;1;1;200;37;4;1;4;104;8;1;1;8;1;3;11;8;2;4
CHECKSUM: 5124B550BB62D9D94CA1AFD4CC0CB130
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input AXI4-Stream DMA Slave AXI4-Stream DMA Master Copyright 2020 The MathWorks, Inc.

BLOCK:
AFull;AXI4_AFIFO_Full;AXIS_FIFO_Full;AXIS_FIFO_Num;Add;AlmostFull;BackPressureCounterEn;Bit Concat;Bus Creator;Bus Selector;Ch;ChOut;ChScale;ChSelect_A;ChSelect_B;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;Count;CountBackPressure;DTC_10_;DTC_11_;DTC_12_;DTC_13_;DTC_14_;DTC_15_;DTC_16_;DTC_17_;DTC_18_;DTC_19_;DTC_1_;DTC_20_;DTC_21_;DTC_22_;DTC_23_;DTC_24_;DTC_2_;DTC_3_;DTC_4_;DTC_5_;DTC_6_;DTC_7_;DTC_8_;DTC_9_;Data Type Conversion;DataCaptureEn;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;EnableConsecutiveFrames;FWFT_FIFO;For Each;FrameSizeInput;From;Gain;GainScale;Goto;HDL Counter;HDL FIFO;IQ_Valid;I_Samples;I_or_Q;I_or_Q_select;In;Logical Operator;MultiplyForEachChannel;Multiport Switch;Mux;NCO HDL Optimized;NCOIncrement;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_DAC_Ch4_AXI;NCO_DAC_Ch5_AXI;NCO_DAC_Ch6_AXI;NCO_DAC_Ch7_AXI;NCO_Out;NCO_Transmit;NCO_Vector_DAC_IQ;NCO_incr_AXI;Out;Product;Q;Q_Samples;R;Real-Imag to Complex;Reference;Relational Operator;RouteADC;S;Sample;Sample1_I;Sample1_Q;Sample2_I;Sample2_Q;Sample3_I;Sample3_Q;Sample4_I;Sample4_Q;Scale;Selector;Signal Specification;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Tile0 ADC Mixer Ch0-I Data;Tile0 ADC Mixer Ch0-IQ Valid;Tile0 ADC Mixer Ch0-Q Data;Tile0 ADC Mixer Ch1-I Data;Tile0 ADC Mixer Ch1-IQ Valid;Tile0 ADC Mixer Ch1-Q Data;Tile0 ADC Mixer Ch2-I Data;Tile0 ADC Mixer Ch2-IQ Valid;Tile0 ADC Mixer Ch2-Q Data;Tile0 ADC Mixer Ch3-I Data;Tile0 ADC Mixer Ch3-IQ Valid;Tile0 ADC Mixer Ch3-Q Data;Tile0 DAC Mixer Ch0-I Data;Tile0 DAC Mixer Ch0-IQ Valid;Tile0 DAC Mixer Ch0-Q Data;Tile0 DAC Mixer Ch1-I Data;Tile0 DAC Mixer Ch1-IQ Valid;Tile0 DAC Mixer Ch1-Q Data;Tile0 DAC Mixer Ch2-I Data;Tile0 DAC Mixer Ch2-IQ Valid;Tile0 DAC Mixer Ch2-Q Data;Tile0 DAC Mixer Ch3-I Data;Tile0 DAC Mixer Ch3-IQ Valid;Tile0 DAC Mixer Ch3-Q Data;Tile1 ADC Mixer Ch0-I Data;Tile1 ADC Mixer Ch0-IQ Valid;Tile1 ADC Mixer Ch0-Q Data;Tile1 ADC Mixer Ch1-I Data;Tile1 ADC Mixer Ch1-IQ Valid;Tile1 ADC Mixer Ch1-Q Data;Tile1 ADC Mixer Ch2-I Data;Tile1 ADC Mixer Ch2-IQ Valid;Tile1 ADC Mixer Ch2-Q Data;Tile1 ADC Mixer Ch3-I Data;Tile1 ADC Mixer Ch3-IQ Valid;Tile1 ADC Mixer Ch3-Q Data;Tile1 DAC Mixer Ch0-I Data;Tile1 DAC Mixer Ch0-IQ Valid;Tile1 DAC Mixer Ch0-Q Data;Tile1 DAC Mixer Ch1-I Data;Tile1 DAC Mixer Ch1-IQ Valid;Tile1 DAC Mixer Ch1-Q Data;Tile1 DAC Mixer Ch2-I Data;Tile1 DAC Mixer Ch2-IQ Valid;Tile1 DAC Mixer Ch2-Q Data;Tile1 DAC Mixer Ch3-I Data;Tile1 DAC Mixer Ch3-IQ Valid;Tile1 DAC Mixer Ch3-Q Data;Transmit and Receive Tone;Trigger;TriggerCapture;Unit Delay;ValidOut;afull;axi_mm2s_tdata;axi_mm2s_tready;axi_mm2s_tready_dtc;axi_mm2s_tvalid;axi_s2mm_tdata;axi_s2mm_tdata_dtc;axi_s2mm_tready;axi_s2mm_tvalid;axi_s2mm_tvalid_dtc;cache_reg;data_i;data_o;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sample;scaleFactor;sr_latch

BLOCKTYPE:
Bit Concat;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;Conversion Inherited;DataTypeConversion;Delay;Detect Increase;Display;ForEach;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;Mux;NCO;Outport;Product;RealImagToComplex;RelationalOperator;Selector;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay


MODELNAME: soc_datacapture_8x8real_hostio
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8real_hostio.slx
BLOCKTYPE_FREQUENCY: 1;4;1;12;10;1;1;5;1;2;3;1;1;1;5;1;2;1;1;1;1;1;4;12;1
CHECKSUM: F75CABB8F042ABCF78188DBFFAC6FECF
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
DESCRIPTION:
8x8 ADC/DAC Data capture model for host PC This model demonstrates capturing data from the FPGA. AXI4 register is used to switch between different ADC channels and collect frames of data at every time step of the simulation The DAC is driven by an NCO. Its frequency is also adjustable from this model as well. 

ANNOTATION:
Select ADC Channels 1 through 8 here  If this is &gt;0 it means we lost samples internal DUT FIFO overflowed FIFO / AXI4 Stream MM2S monitor Stream Control NCO Control / Scaling Copyright 2020 The MathWorks, Inc.  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device Host Interface Model - 8x8 Real  Selecting ADC Channels 0 - ADC Ch1 1 - ADC Ch2 2 - ADC Ch3 3 - ADC Ch4 4 - ADC Ch5 5 - ADC Ch6 6 - ADC Ch7 7 - ADC Ch8

BLOCK:
 Demux ; SFunction ; Terminator ;ADC Captured Scope Out;ADC Captured Spectrum Out;ADC_Channel;ADC_Channel_Select_AXI;AXI4 Register IIO Write;AXI4- Stream IIO Read;AXI4TriggerCapture;Add;Bit Slice;Constant;DAC1_ScaleVal;DAC2_ScaleVal;DAC3_ScaleVal;DAC4_ScaleVal;DAC_Scale;Data Type Conversion;Delay;DisplayData;Enable;FIFO_AlmostFullCount;FIFO_Full;FIFO_Num;FormatData;Frame Size;Frame Valid;FramesCollected;Freq (MHz);Gain;MHzScale;Manual Switch;NCOFreq;NOT;PS_AutoTrigger;Pl_AutoTrigger;Read_Almost_Full;Read_FIFO_Full;Read_FIFO_Num;Read_Tready_Low_Count;Reference;ResetDUT;Reshape;S2MM_TreadyLowCount;Simulink Function;StreamEn;SubSystem;Trigger Frequency;Vector Concatenate;dataIn;dataOut;dispData;en;u

BLOCKTYPE:
ArgIn;Bit Slice;Concatenate;Constant;DataTypeConversion;Delay;Demux;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;Outport;Reshape;S-Function;Scope;Slider Gain;SpectrumAnalyzer;Sum;Terminator;TriggerPort;soc.libiio.aximm.ReadHost;soc.libiio.aximm.WriteHost;soc.libiio.axistream.ReadHost


MODELNAME: soc_datacapture_8x8real_zcu111_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8real_zcu111_fpga.slx
BLOCKTYPE_FREQUENCY: 8;1;2;7;5;10;1;7;54;2;1;11;3;5;2;1;114;37;1;4;83;16;2;16;1;4;8;6;2;4;4
CHECKSUM: 92CD4A5303C40BFE7786B3F9C6D605A7
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input Tile 1 & 2 for DAC AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Channel 0 Copyright 2020 The MathWorks, Inc.

BLOCK:
ADC_SelectCh;AFull;AXI4_FIFO_Full;AXI4_FIFO_Num;AXIS_FIFO_Full;AXIS_FIFO_Num;Add;AutoTrigEn;AutoTrigger;BackPressureCounterEn;Bus Creator;Bus Selector;Ch;ChOut;Compare To Constant;Compare To Zero;ConsecFrames;Constant;Data Type Conversion;DataCaptureEn;DataPushFrequency;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;EnableConsecutiveFrames;FIFO_AFullCount;FWFT_FIFO;FrameSizeInput;From;Gain;Goto;HDL Counter;HDL FIFO;In;Increment;Logical Operator;MM2S_Data;MM2S_Ready;MM2S_Valid;MaxCount;Multiport Switch;NCO HDL Optimized;NCOInput;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_Process;NCO_Valid;NCO_Vector_DAC;NCO_incr_AXI;Out;PortSelect;Product;Q;R;Reference;Relational Operator;RouteADC;S;S2MM_Data;S2MM_Tready;S2MM_TreadyLowCount;S2MM_Valid;SW_en;Scale;ScaleCh;Selector;Signal Specification;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Tile0_ADC0_Data;Tile0_ADC0_Valid;Tile0_ADC1_Data;Tile0_ADC1_Valid;Tile0_DAC0_Data;Tile0_DAC0_Valid;Tile0_DAC1_Data;Tile0_DAC1_Valid;Tile0_DAC2_Data;Tile0_DAC2_Valid;Tile0_DAC3_Data;Tile0_DAC3_Valid;Tile1_ADC0_Data;Tile1_ADC0_Valid;Tile1_ADC1_Data;Tile1_ADC1_Valid;Tile1_DAC0_Data;Tile1_DAC0_Valid;Tile1_DAC1_Data;Tile1_DAC1_Valid;Tile1_DAC2_Data;Tile1_DAC2_Valid;Tile1_DAC3_Data;Tile1_DAC3_Valid;Tile2_ADC0_Data;Tile2_ADC0_Valid;Tile2_ADC1_Data;Tile2_ADC1_Valid;Tile3_ADC0_Data;Tile3_ADC0_Valid;Tile3_ADC1_Data;Tile3_ADC1_Valid;Transmit and Receive Tone;Trig;Trigger;TriggerCapture;TriggerFreq;Unit Delay;Valid;ValidOut;Vector Concatenate;Vector To DAC;afull;cache_reg;data_i;data_o;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sr_latch

BLOCKTYPE:
BusCreator;BusSelector;Compare To Constant;Compare To Zero;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;NCO;Outport;Product;RelationalOperator;Selector;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay;Vector To DAC


MODELNAME: soc_datacapture_8x8real_zcu111_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8real_zcu111_top.slx
BLOCKTYPE_FREQUENCY: 8;12;3;19;49;1;8;6;2;9;36;3;1;1;14;4;1;1;2;1;13
CHECKSUM: 3FF57778A8416FF0C56A4380EF3569C9
PRODUCT: DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_datacapture_8x8real_zcu111_fpga.slx___Model_Block___
ANNOTATION:
Copyright 2020 The MathWorks, Inc.  Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device

BLOCK:
ADC Captured Scope Out;ADC Input;ADC Input signal;ADC0_Valid;AFull;AXI4 Read;AXI4FIFO_Full;AXI4FIFO_Num;AXI4Stream_DMA_MM2S;AXI4Stream_DMA_S2MM;Add;Bit Concat;Bit Slice;CompactBits;Constant;DAC_Output_Tile;Data Type Conversion;Delay;Demux;Enable;FIFO_AFullCount;FIFO_Full;FIFO_Num;FPGA;Frame Size;Gain;In;Manual Switch;Mod;NCO Freq (MHz);OFF;ON;Out;PlotDACData;PlotData;Reference;ShouldDisplay;ShouldDisplayZero;StreamEn;SubSystem;Subsystem;TData;TReady_Lcount;TReady_LowCount;Terminator;Tile0 DAC Scope Out;Tile0 DAC Spectrum Out;Tile1 DAC Scope Out;Tile1 DAC Spectrum Out;TriggerFreq;Vector Concatenate;dac1Data;dac1Valid;dac2Data;dac2Valid;dac3Data;dac3Valid;dac4Data;dac4valid;dac5Data;dac5Valid;dac6Data;dac6Valid;dac7Data;dac7Valid;dac8Data;dac8Valid;dacData;dacdata;dataIn;dataOut;mm2sData;mm2sReady;mm2sValid;s2mmData;s2mmReady;s2mmValid;scale

BLOCKTYPE:
Bit Concat;Bit Slice;Concatenate;Constant;DataTypeConversion;Delay;Demux;Display;EnablePort;Gain;Inport;ManualSwitch;Math;ModelReference;Outport;Scope;Sine Wave;Slider Gain;SpectrumAnalyzer;Sum;Terminator


MODELNAME: soc_datacapture_8x8real_zcu216_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_datacapture_8x8real_zcu216_fpga.slx
BLOCKTYPE_FREQUENCY: 8;1;2;7;5;10;1;7;54;2;1;11;3;5;2;1;114;37;1;4;83;16;2;16;1;4;8;6;2;4;4
CHECKSUM: D00E693C1770801D0185F9A56BD3C19C
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Give it default non-zero value at start-up time Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input Tile 1 & 2 for DAC AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Channel 0 Copyright 2020 The MathWorks, Inc.

BLOCK:
ADC_SelectCh;AFull;AXI4_FIFO_Full;AXI4_FIFO_Num;AXIS_FIFO_Full;AXIS_FIFO_Num;Add;AutoTrigEn;AutoTrigger;BackPressureCounterEn;Bus Creator;Bus Selector;Ch;ChOut;Compare To Constant;Compare To Zero;ConsecFrames;Constant;Data Type Conversion;DataCaptureEn;DataPushFrequency;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Display;EnableConsecutiveFrames;FIFO_AFullCount;FWFT_FIFO;FrameSizeInput;From;Gain;Goto;HDL Counter;HDL FIFO;In;Increment;Logical Operator;MM2S_Data;MM2S_Ready;MM2S_Valid;MaxCount;Multiport Switch;NCO HDL Optimized;NCOInput;NCO_DAC_Ch0_AXI;NCO_DAC_Ch1_AXI;NCO_DAC_Ch2_AXI;NCO_DAC_Ch3_AXI;NCO_Process;NCO_Valid;NCO_Vector_DAC;NCO_incr_AXI;Out;PortSelect;Product;Q;R;Reference;Relational Operator;RouteADC;S;S2MM_Data;S2MM_Tready;S2MM_TreadyLowCount;S2MM_Valid;SW_en;Scale;ScaleCh;Selector;Signal Specification;StreamEn;SubSystem;Subsystem;Switch;TData;TDataOut;TReady;TValid;Terminator;Tile0_ADC0_Data;Tile0_ADC0_Valid;Tile0_ADC1_Data;Tile0_ADC1_Valid;Tile0_ADC2_Data;Tile0_ADC2_Valid;Tile0_ADC3_Data;Tile0_ADC3_Valid;Tile0_DAC0_Data;Tile0_DAC0_Valid;Tile0_DAC1_Data;Tile0_DAC1_Valid;Tile0_DAC2_Data;Tile0_DAC2_Valid;Tile0_DAC3_Data;Tile0_DAC3_Valid;Tile1_ADC0_Data;Tile1_ADC0_Valid;Tile1_ADC1_Data;Tile1_ADC1_Valid;Tile1_ADC2_Data;Tile1_ADC2_Valid;Tile1_ADC3_Data;Tile1_ADC3_Valid;Tile1_DAC0_Data;Tile1_DAC0_Valid;Tile1_DAC1_Data;Tile1_DAC1_Valid;Tile1_DAC2_Data;Tile1_DAC2_Valid;Tile1_DAC3_Data;Tile1_DAC3_Valid;Transmit and Receive Tone;Trig;Trigger;TriggerCapture;TriggerFreq;Unit Delay;Valid;ValidOut;Vector Concatenate;Vector To DAC;afull;cache_reg;data_i;data_o;dtci;empty_i;empty_o;full;fwft_logic;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;push;rd_ack;rd_ack_i;sr_latch

BLOCKTYPE:
BusCreator;BusSelector;Compare To Constant;Compare To Zero;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;MultiPortSwitch;NCO;Outport;Product;RelationalOperator;Selector;SignalSpecification;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay;Vector To DAC


MODELNAME: soc_dvbs2fmcomms_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_dvbs2fmcomms_fpga.slx
CHECKSUM: FE853582D4F7029D09930C13588E5C76
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2)  Add Block is used to obtain integer index to Lookup Table  HDL AWGN Generator assumes input signal power is unity. As the Es value is maintained unity in the input waveform but not the signal power, EsNodB is directly connected to snrdB to generate noise to maintain proper EsNodB.  Fixed point precision loss warnings are supressed in Mask Init Callback  force MODCOD to 0 until synchronization is done  Set this value to zero to disable correction  Let Z be the complex phase estimate and Xbar be the data and X be the corrected data. X = Xbar * conj(Z) * (1/abs(Z))  Wrap on overflow with data type signed and 1 intergral bit will wrap the output to lie in between -1 to 1 Differential Detection Compute Energy Compute Energy Compute Energy  The initial output of these outports are set to 0 as this is an enabled subsystem Hold pilotEnable signal Hold pilotsEnable signal after endOfPLSC Proportional-Plus-Integrator Loop Filter, Infinite DC Response to guarantee convergence  Copyright 2023 The MathWorks, Inc.  Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;1-D Lookup Table;AWGN;Add;AddADn;AddAUp;AddBCtr;AddBDn;AddBUp;Bias;Bit Concat;Bit Flipping and Averaging;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;CFO;CPO;CWswitch;Channel;Coarse Frequency Estimator;Coarse Phase Corrector;Coarse Phase Estimator;Coarse Phase Synchronizer;Code Word LUT 1 to ;Code Word LUT 33 to ;Compare To Constant;Complex Multiplier;Complex to Magnitude-Angle HDL Optimized;Complex to Real-Imag;Compute Euclidean Distance;Compute R(m) for 1 to ;Compute R(m) for 13 to ;Compute R(m) for 7 to ;Compute R(m)_;ConcatandExtract;Conj;ConstData;ConstValid;Constant;Corr Add;Corr Subtract;Correlator;CwEdMetric;DVB-S2 PL Header Recovery HDL;Data Type Conversion;Data Type Duplicate;Delay;Delta;Demux;Digital Automatic Gain Control;Direct Digital Synthesis;Discrete FIR Filter;Discrete FIR Filter HDL Optimized;Divide by ;Downsample;E;Ed;En;EnNoise;Enable;Enable MODCOD ;Error Detector;EsNodB;Euclidean Distance Sum Up;Extract Bits;FEC;FECFrame;Fine Frequency Synchronizer;Fine Gain Control;Fine Phase Synchronizer;For Each;For Each Subsystem;Frame Synchronizer;Frequency Error Detector;From;Function Impl;FunctionEvaluation;GTED;Gain;Gardner TED;Gaussian Noise With Given Variance;Get Min Index;Goto;HDL AWGN Generator;HDL Counter;In;Information Decoder;Input Sample Counter;Integer Delay;Integer to Bit Convertor;Integrator Gain;Interpolation Control;Interpolation Filter;K;L and R Algorithm 18 point;LS;LUT;LUT Based Tx;LUTAddr;Logical Operator;Loop Filter;MATLAB Function;ML Decoder;MS;Math Function;Modified L and R Algorithm;Moving Average;Moving Average ;Moving Sum;Multiport Switch;Mux;NCO HDL Optimized;No HDL;Out;OverAir;PL;PL Data Descrambler;PL Data Descrambler and Pilot Valid Indicator;PL Frame Demultiplexer;PL Header Decoder;PL Header Recovery;PL Scramble Sequence Mapper LUT;PL Scrambler Gold Sequence Generator;PLSC Correlator;PLSC Descrambler;PLSC Valid Counter;PLSCCorr;PLSCCorrOut;PLSCDiag;PLSCValid;Phase Error Detector;Pilot Blks Counter;Pilot Valid Indicator;Pilot and Sync Pulse Indicator;PilotIdx Counter;Power Q and Beta Offset Rotation;PrevEst;Product;ProductCtr;ProductDn;ProductUp;RRC Receive Matched Filter;RangeReconstruction;RangeReduction;Rate Handle;Real-Imag to Complex;Reciprocal;Ref;Reference;Relational Operator;Repeat;RxDataI_In;RxDataIn;RxDataQ_In;RxValid_In;SOF Correlator;SOFCorrDelayed;SOFCorrOut;Shift Arithmetic;SinCos;Sine HDL Optimized;Source Encoding;Spectrum Analyzer;SqrtEval;SqrtImplementation;StreamFromFMC;StreamToFMC;SubSystem;Subsystem;Subtract;Sum;Switch;Symbol Synchronizer;Synchronizer and PL Header Decoder;TausURNG;TausUniformRandGen;Terminator;Threshold Scaling;ThresholdLimiter;Time Frequency and Coarse Phase Synchronizer;Time and Coarse Frequency Synchronizer;To Workspace;Tx-LUT_Channel_Rx;TxDataI_Out;TxDataOut;TxDataQ_Out;TxSymData;TxSymValid;TxValidOut;TxValid_Out;Underflow;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Unit Variance Gaussian Noise;Unwrapping algorithm;Upsample;ValidFromPS;ValidToFMC;ValueOut;Variance Estimator;VisualizeCorrelationSignals;X PN Generator M_n;X PN Generator M_nplus;Y PN Generator M_;a;avgOut;awgn;b;bits6Out;c;coarseFreqEst;complexEst;complexEstimate;constDataI;constDataQ;constValid;consteData;consteSwitch;consteValid;constedata;constevalid;corrValue;currentEst;dB to Linear Scale Converter;dValid;data;dataIn;dataOut;decodedFECFrame;decodedMODCOD;diagBus;e;enNoise;enable;enableNoise;enb;enbCCFO;enbFCPO;enbMODCOD;endOfLUT;endOfPLSC;endOfPLSCIn;endOfPLSc;endOfSOF;endOfSOFIn;err;estOut;estValid;estVar;estimate;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;fecFrame;fineFreqEst;finePhaseEn;forBit;freqEst;functionValues;g;g1(16,15);gain;hValid;has Pilots;hasPilots;headerInfo;idxIn;idxOut;indexIndicater;indexIndicator;indexIndicatorIn;indexIndicatorOut;indices;inputCount;interpolant;isdummy;leadingZeroDetector;log;logImplementation;mod;modcod;modcodIn;modcodOut;modcodidx;mu;nEstCoarseFreq;nEstFineFreq;nEstFreq;nframesSynced;noiseVar;normCoaFreqEst;normFineFreqEst;normFreqEst;normalizedEst;out;outputConstellation;overAir;pass;passIn;passOut;pi/2 BPSK Soft Bit Generator;pilotBlkCount;pilotConstel;pilotEnable;pilotIdx;pilotIdxOut;pilotValid;pilotValidIn;pilotValidOut;pilotidx;reset;resetIn;resetOut;rst;rstCCFO;rstDisp;rstDisplay;rstFCPO;rstOut;rxExtData;rxExtValid;rxIn;s;scaled;snrdb;softBit;sqrt(noisePow/2);strobe;sum;switch;symbSyncDataOut;symbSyncValidOut;synbSyncDiag;threshold;thresholdExceeded;txDataOut;txLUT;txOut;txValidOut;u;u0(16,16);u0(48,48);u1(16,16);v;valid;validIn;validOut;valueIn;var;varOut;x;xMn;xMnp;x_e;x_f;xph;y;yM;y_e;y_f;z;zvalid

BLOCKTYPE:
ArithShift;Bias;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Complex to Magnitude-Angle;ComplexToRealImag;Constant;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Discrete FIR Filter;DownSample;EnablePort;Extract Bits;ForEach;From;Gain;Goto;HDL Counter;Inport;Logic;LookupNDDirect;Lookup_n-D;Math;MultiPortSwitch;Mux;NCO;Outport;PN Sequence Generator;Product;RealImagToComplex;RelationalOperator;Repeat;S-Function;Sine and Cosine HDL optimized block;SpectrumAnalyzer;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Resettable Synchronous;Unit Delay Enabled Synchronous;Upsample

BLOCKTYPE_FREQUENCY:
14;1;4;19;2;21;1;1;7;6;107;3;60;39;91;32;2213;17;4;11;4;25;14;134;49;61;52;440;98;6;34;31;12;11;5;395;4;102;26;8;11;5;2;1;195;34;19;2;28;36;6

PRODUCT:
Communications Toolbox;DSP HDL Toolbox;DSP System Toolbox;Embedded Coder;Fixed-Point Designer;HDL Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_dvbs2fmcomms_host
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_dvbs2fmcomms_host.slx
BLOCKTYPE_FREQUENCY: 2;1;7;1;20;7;2;4;13;5;23;1;7;2;2;1
CHECKSUM: 8519CDBA4CCB585C506AC1EC36900C63
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Copyright 2023 The MathWorks, Inc.  SoC Blockset DVB-S2 PL Header Recovery Host UDP Control &amp; Receive Model  Copyright 2023 The MathWorks, Inc.

BLOCK:
Bit Slice;CFO;CPO;Constant;Constellation Diagram;Control Scope;Data Type Conversion;Display;Enable;EsNodB;Gain;Host UDP;In;Manual Switch;Real-Imag to Complex;Reference;Selector;Status Signals;StatusSignals;SubSystem;To Workspace;UDP Receive Constellation;UDP Receive Status;UDP Send;Vector Concatenate;Visualize Constellation;constellation;decodedFECFrame;decodedMODCOD;enableNoise;enbCCFO;enbConstellation;enbFCPO;estVar;modcod;nEstCoarseFreq;nEstFineFreq;nEstFreq;nFramesSynced;outputConstellation;overAir;rstDisplay;switch

BLOCKTYPE:
Bit Slice;Concatenate;Constant;ConstellationDiagram;DataTypeConversion;Display;EnablePort;Gain;Inport;ManualSwitch;Outport;RealImagToComplex;Selector;ToWorkspace;UDP Receive;UDP Send


MODELNAME: soc_dvbs2fmcomms_hwtop
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_dvbs2fmcomms_hwtop.slx
ANNOTATION: SoC Blockset DVB-S2 PL Header Recovery Hardware Model Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;2;1;1;8;1;3;1;7;1;4;2;5;1;1;1;1
CHECKSUM: 2FC690FEA4E31438452E708D0ABF1B67
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_dvbs2fmcomms_fpga.slx___Model_Block___
BLOCK:
AD9361Rx;AD9361Tx;Bit Slice;CFO;CPO;Channel;Constant;Constellation Diagram;Data Type Conversion;Display;Enable;EsNodB;FPGA;Gain;Manual Switch;RFIn;RFOut;Real-Imag to Complex;Reference;Simple delay channel;SoC Bus Creator;SoC Bus Selector;SubSystem;Terminator;Visualize Constellation;modcod;stream1ToPS;switch

BLOCKTYPE:
AD9361 Rx Playback;AD9361 Tx Playback;Bit Slice;Bus Creator;Bus Selector;Constant;ConstellationDiagram;DataTypeConversion;Delay;Display;EnablePort;Gain;Inport;ManualSwitch;ModelReference;Outport;RealImagToComplex;Terminator

PRODUCT:
Communications Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_dvbs2fmcomms_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_dvbs2fmcomms_proc.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;17;1;1;20;27;7;10;10;1;1;1;1;2;1;1
CHECKSUM: 41ED61B8E0B3D9F1D3F2711B5B130558
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Asynchronous Task Specification;CantrolFromHostToPS;ControlFromHost;Data;Data Type Conversion;Enable;Event Listener;Event driven;Reference;Register Read;Register Write;Selector;StatusFromPSToHost;Stream Read;StreamToHost;SubSystem;Subsystem;Terminator;UDP Read;UDP Write;Vector Concatenate;Zynq and FMCOMMS2/3/4 Receiver;Zynq and FMCOMMS2/3/4 Transmitter;c;constellationToHost;controlFromHost;controlFromPSToFMC;dataTask;done;doneToPL;msg;s;statusToHost;statusUDPReport;streamFromPL;streamToHost

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;DataTypeConversion;EnablePort;EventListener;Inport;Outport;Register Read;Register Write;Selector;Stream Read;Terminator;TriggerPort;UDP Read;UDP Write;comm.internal.SDRRxZC706FMC234RFSL;comm.internal.SDRTxZC706FMC234RFSL


MODELNAME: soc_dvbs2fmcomms_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_dvbs2fmcomms_top.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;2;2;1;15;2;15;1;1;2;1;2
CHECKSUM: DC367CAF7D508EB6F83D4F0ACE03E45A
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_dvbs2fmcomms_fpga.slx___Model_Block___soc_dvbs2fmcomms_proc.slx___Model_Block___
ANNOTATION:
 SoC Blockset DVB-S2 PL Header Recovery Hardware Model  Copyright 2023 The MathWorks, Inc. FPGA Processor External I/O Memory External I/O

BLOCK:
AD9361Rx;AD9361Tx;Channel;Constant;ControlFromHost;Enable;FPGA;IO Data Sink;IO Data Source;PS;Processor;RFIn;RFOut;Reference;Register Write;Simple delay channel;StatusToHost;SubSystem;Task Manager;Terminator;UDP Read;UDP Write;UDP Write ;c;constData to Software;constDataToHost;controlFromHost;data;done;event;msg;s;statusToHost;streamToHost

BLOCKTYPE:
AD9361 Rx Playback;AD9361 Tx Playback;AXI4-Stream to Software;Constant;Delay;EnablePort;IO Data Sink;IO Data Source;Inport;ModelReference;Outport;Register Channel;Task Manager;Terminator;UDP Read;UDP Write


MODELNAME: soc_edge_detection_fpga_frame
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_edge_detection_fpga_frame.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE: Concatenate;Constant;Edge Detection;Gain;Inport;Outport;Product;RateTransition;Selector;Sum;Switch
BLOCKTYPE_FREQUENCY: 1;5;1;1;13;8;2;4;2;2;3
CHECKSUM: F17363F767D147F758C9D4FBFF3F5AED
PRODUCT: Computer Vision Toolbox;Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Add;CbCrIn;CbCrOut;Constant;CtrlIn;CtrlOut;DIPSwitch;Edge Detection;Edges;FrameOut;Gain;LED;Overlay;Product;PushButton;Rate Transition;Reference;Selection Subsystem;Selector;SubSystem;Switch;Vector Concatenate;YOut;cAlpha;cThreshold;dsGrayscale;frameIn;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;pbEdgeOnly


MODELNAME: soc_edge_detection_fpga_pixel
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_edge_detection_fpga_pixel.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;3;1;7;25;1;27;19;2;4;2;4;1;2;1
CHECKSUM: 5A2FB36BAA980D453317A448348B1551
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Add;AlwaysReady;Bit Concat;Bit Slice;CbCr;CbCrIn;CbCrOut;Constant;CtrlIn;CtrlOut;DIPSwitch;Delay;Edge Detection;Edge Detection Wrapper;Edge Detector;EdgeIn;EdgeOut;Edges;FPGA Algorithm;Image Overlay;LED;Overlay;OverlayOut;Pixel Control Bus Selector;Pixel Stream Aligner;Product;PushButton;Rate Transition;Reference;Selection Subsystem;SubSystem;Switch;Terminator;Threshold;Video Stream Connector;Video Stream FIFO;YIn;YOut;alpha;cAlpha;cThreshold;ctrlIn;ctrlOut;dsGrayscale;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;pbEdgeOnly;pixelIn;pixelOut;rdyFromDown;rdyToUp

BLOCKTYPE:
Bit Concat;Bit Slice;BusSelector;Constant;Delay;Edge Detector;Inport;Outport;Product;RateTransition;Sum;Switch;Terminator;Video Stream Connector;visionhdl.PixelStreamAligner

PRODUCT:
Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices;Vision HDL Toolbox


MODELNAME: soc_edge_detection_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_edge_detection_top.slx
BLOCKTYPE: DIP Switch;HDMI Rx;HDMI Tx;Inport;LED;ModelReference;Outport;Push Button
BLOCKTYPE_FREQUENCY: 1;1;1;4;1;2;3;1
CHECKSUM: 6BBE04044B336B42D1E5DBF49A47FDC8
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 To add your FPGA Algorithm, open the referenced models and replace contents of subsystem marked in green FPGA External I/O   Edge Detection and Image Overlay Copyright 2023 The MathWorks, Inc. External I/O 

BLOCK:
DIP Switch;FPGA;Frame based processing;HDMI Rx;HDMI Tx;LED;Pixel based processing;Push Button;Reference;SubSystem;dsGrayscale;hdmiCtrlIn;hdmiCtrlOut;hdmiDataIn;hdmiDataOut;pbEdgeOnly

EXTERNALFILE_REFERENCE:
soc_edge_detection_fpga_frame.slx___Model_Block___soc_edge_detection_fpga_pixel.slx___Model_Block___


MODELNAME: soc_frequency_hopping_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_frequency_hopping_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;2;1;8;2;1;10;2;1;2;1;8;37;7;1;62;2;1;2;10;1;3;1
CHECKSUM: 2116F533C78EBC6CAE70C366916DC1E1
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Default is 1 sec in case of 256 MHz  NCO Frequency Value (48-bit) -Fs/2 0x8000_0000_0000 -Fs/4 0xc000_0000_0000 0 0x0000_0000_0000 Fs/4 0x3FFF_FFFF_FFFF Fs/2 0x7FFF_FFFF_FFFF  NCO Phase Value (18-bit) -180 0x2_0000 -90 0x3_0000 0 0x0_0000 90 0x0_FFFF 180 0x1_FFFF  NCO Frequency Value (48-bit) -Fs/2 0x8000_0000_0000 -Fs/4 0xc000_0000_0000 0 0x0000_0000_0000 Fs/4 0x3FFF_FFFF_FFFF Fs/2 0x7FFF_FFFF_FFFF  NCO Phase Value (18-bit) -180 0x2_0000 -90 0x3_0000 0 0x0_0000 90 0x0_FFFF 180 0x1_FFFF  Not modeling ready since HDL coder models it during IP core generation.  Not modeling TLAST since HDL coder models it during IP core generation. Copyright 2022 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Bit Concat;Bus Creator;Bus Selector;Compare To Constant;Complex to Real-Imag;Constant;Counter Limited;Data Type Conversion;Delay;Downsampler;Enable;Equal;FH Controller;FH Receiver;FH Transmitter;Frequency Hopping;Gain;HDL Counter;IP Core Register Read;Logical Operator;MATLAB Function;MixerFreq;NCO Frequency Updater;NCO HDL Optimized;NCOFrequency;NCOPhase;NCOPhaseReset;NCOUpdateBusy;NCOUpdateEnable;NCOUpdateReq;OR;RFDC Bus Creator;Reference;Selector;SubSystem;Subsystem;Switch;Terminator;Tone Generation;Trigger;Update NCO Frequency;adc1QData;adcCtrl;adcIData;adcMixerFreq;adcNCOFrequency;adcNCOPhase;adcNCOPhaseReset;adcNCOUpdateBusy;adcNCOUpdateEnable;adcNCOUpdateReq;adcQData;adcTdata;adcTrigger;adcTvalid;adcValid;captureDataOut;chCtrlIn;chCtrlOut;chIData;chQData;chValid;count;dacCtrl;dacIData;dacMixerFreq;dacNCOFrequency;dacNCOPhase;dacNCOPhaseReset;dacNCOUpdateBusy;dacNCOUpdateEnable;dacNCOUpdateReq;dacQData;dacTrigger;dacValid;en;fStart;fStep;fStop;out;y

BLOCKTYPE:
Bit Concat;Bus Creator;Bus Selector;Compare To Constant;ComplexToRealImag;Constant;Counter Limited;DataTypeConversion;Delay;Demux;EnablePort;Gain;HDL Counter;IP Core Register Read;Inport;Logic;NCO;Outport;RFDC Bus Creator;RelationalOperator;S-Function;Selector;Switch;Terminator;TriggerPort


MODELNAME: soc_frequency_hopping_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_frequency_hopping_proc.slx
BLOCKTYPE_FREQUENCY: 1;2;8;5;1;4;2;3;4;1;8;6;1;1;1;1
CHECKSUM: 5A8C3C9E9A23FE8BB0CE1DF51A42D08D
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Phase increment value for the corresponding sinusoidal tone frequency.  Bit 5: Enable write to phase reset Bit 4: Enable write to NCO phase bits 17:16 Bit 3: Enable write to NCO phase bits 15:0 Bit 2: Enable write to NCO frequency bits 47:32 Bit 1: Enable write to NCO frequency bits 31:16 Bit 0: Enable write to NCO frequency bits 15:0  Bit slicing the input 64bit stream data into 4 16bit samples.  Reshaping the frame data to arrange it in a column vector of consecutive samples. Copyright 2022 The MathWorks, Inc.

BLOCK:
Asynchronous Task Specification;Constant;Data Type Conversion;DataIn;DataOut;DataTask;Event Listener;Extract Bits;Gain;Initialize Function;Processor Algorithm Wrapper;Real-Imag to Complex;Reference;Register Write;Reshape;Slider Gain;Stream Read;SubSystem;Terminator;Trigger;Vector Concatenate;dataIn;dataOut;done

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;EventListener;Extract Bits;Gain;Inport;Outport;RealImagToComplex;Register Write;Reshape;Slider Gain;Stream Read;Terminator;TriggerPort


MODELNAME: soc_frequency_hopping_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_frequency_hopping_top.slx
BLOCKTYPE_FREQUENCY: 1;2;3;1;4;1;2;4;11;2;2;7;3;1;1;1;2;2;1;1;1
CHECKSUM: 9AFA61F47CA265A12167130C2F61E574
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_frequency_hopping_fpga.slx___Model_Block___soc_frequency_hopping_proc.slx___Model_Block___
ANNOTATION:
 Frequency Hopping on RFSoC Device RF I/O  FPGA Memory Processor Testbench  Copyright 2022 The MathWorks, Inc.

BLOCK:
ADC Captured Signal;ADC Mixer;ADC_ RealTimeCtrlIn;AXI4-Stream to Software;Bus Selector;Complex Mixer;Complex to Real-Imag;DAC Mixer;DAC Mixer Output;DAC_ RealTimeCtrlIn;Data Type Conversion;Delay;Demux;FPGA;Fine Oscillator;Lowpass Filter;MIxer;PhaseIncr;Processor;Processor - Frame based processing;Product;RF Data Converter;Rate Transition;Real-Imag to Complex;Reference;Selector;SubSystem;Sum;Task Manager;Vector Concatenate;adcMixerOut;adcRealTimeCtrlIn;dacMixerIn;dacMixerOut;dacRealTimeCtrlIn;dataIn;dataOut;dataTask;din;done;dout;getRealFreqVal;mixerIn;mixerOut;osc

BLOCKTYPE:
AXI4-Stream to Software;BusSelector;ComplexToRealImag;Concatenate;DataTypeConversion;Delay;Demux;Gain;Inport;ModelReference;NCO;Outport;Product;RF Data Converter;RateTransition;RealImagToComplex;Selector;SpectrumAnalyzer;Sum;Task Manager;dsp.simulink.LowpassFilter

PRODUCT:
DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_mmWave_datacapture_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_mmWave_datacapture_top.slx
BLOCKTYPE_FREQUENCY: 1;1;3;2;1;3;1;1;1;1;1
CHECKSUM: 0F1A25074711F84A1153AD7E0A5797F1
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_mmWave_datacapture_fpga.slx___Model_Block___soc_mmWave_datacapture_proc.slx___Model_Block___
ANNOTATION:
IO Data/ Test bench Processor  Copyright 2022 The MathWorks, Inc.  Transmit and Receive a Tone Using OTAVA DTRX2 mmWave RF Card Memory FPGA RF

BLOCK:
ADC Captured Scope Output;ADC Captured Signal;AXI4-Stream to Software;Delay;FPGA Data Capture;OTAVA DTRX;Processor;Processor - Frame based processing;RF Data Converter;RF Loopback;RFIn;RFOut;Rate Transition;Reference;SubSystem;Task Manager;dataIn;dataOut;dataTask;done

BLOCKTYPE:
AXI4-Stream to Software;Delay;Inport;ModelReference;OTAVA DTRX2;Outport;RF Data Converter;RateTransition;Scope;SpectrumAnalyzer;Task Manager


MODELNAME: soc_multiChannelTransceiver
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_multiChannelTransceiver.slx
BLOCKTYPE_FREQUENCY: 1;4;4;6;3;10;2;2;2;2;25;1;32;1;6;6;2;3;2;4
CHECKSUM: 1E3CFAB1DDC883179B87B066C9114F50
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Stream To Software Channel 2 Transceiver Channel 1 Transceiver  Multi Channel Transceiver Using Xilinx RFSoC Device  Copyright 2023 The MathWorks, Inc.

BLOCK:
AND;Bit Concat;Bit Slice;Channel 1 Captured Data;Channel 2 Captured Data;Colored Noise;Complex To Real-Imag;Complex to Real-Imag;Constant;DAC Channel 1 Output;DAC Channel 2 Output;Data Type Conversion;Delay;FIR Decimator;FIR Interpolator;Gain;HDL Counter;IData;In;Out;QData;RF Channel;RF Data Converter;Real-Imag to Complex;Reference;Rx Algorithm;Rx Algorithm Wrapper;Single Port RAM System;Stream To Channels;Stream To SW;SubSystem;Sum;Terminator;Transceiver Algorithm;Tx;Tx Source;adcT1Ch0IData;adcT1Ch0QData;adcT1Ch0Valid;adcT2Ch1IData;adcT2Ch1QData;adcT2Ch1Valid;ch1Data;ch1IData;ch1QData;ch1Valid;ch2Data;ch2IData;ch2QData;ch2Valid;dacT0Ch1IData;dacT0Ch1QData;dacT0Ch1Valid;dacT1Ch0IData;dacT1Ch0QData;dacT1Ch0Valid;dataIn;dataOut;rxData;rxValid;streamToSWData;streamToSWValid;valid;validOut

BLOCKTYPE:
Bit Concat;Bit Slice;ComplexToRealImag;Constant;DataTypeConversion;Delay;FIR Decimator;FIR Interpolator;Gain;HDL Counter;Inport;Logic;Outport;RF Data Converter;RealImagToComplex;SpectrumAnalyzer;Sum;Terminator;dsp.simulink.ColoredNoise;hdl.RAM

PRODUCT:
DSP HDL Toolbox;DSP System Toolbox;Embedded Coder;Simulink;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_radar_signal_detector_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_radar_signal_detector_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;1;3;1;2;1;9;3;4;11;1;73;10;1;6;1;1;4;5;12;98;12;1;1;79;4;5;1;4;6;1;1;3;9;6;1
CHECKSUM: C885FBA5142ED1E2CC2258CB91A1957A
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Have to use one FIFO outside of For Each subsystem for the Empty signal, otherwise we get feedback loop error Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AND;Add;Bit Concat;Channel Counter;Channel Frame Counter;Channelizer;Compare To Constant;Compare To Zero;Compare Tree Stage ;Compare to Threshold;Complex to Real-Imag;Compute Power;Constant;Constrain Word Length;Data Type Conversion;Data Type Duplicate;Data Type Propagation;Decrement Stored Integer;Delay;Demux;Detect Rise Positive;Detector;Discard Second Half Channels;Empty;FIFO Serialize Control;For Each;For Each Subsystem;From;Gain 1/windowSize;Generate Enable Vector;Goto;HDL Counter;HDL FIFO;IP Core Register Read;In;Logical Operator;Matrix Concatenate;Maximum;Min;Moving Average;NCO;NCO LFM Generator;NOT;OR;Out;Output Capture;Output Capture Control;Pack to 32bit;Packet Control Fcn;Phase Inc Counter;Pop;Product;Propagate DT;Pulse Generator;Pulse Generator Control;Push;RAMDelay;Reference;Relational Operator;Reshape;Select 1st half frame;Select 2nd half frame;Selector;Serialize x;SoC Bus Creator;SoC Bus Selector;State Control;Stream FIFO;Stream Packet Controller;SubSystem;Switch;Switch_load;System Time;TDATA FIFO;TLAST FIFO;Terminator;To DMA;Unit Delay Enabled Synchronous;Vector FIFO;Wait for Accumulator Init;Wideband Detector;activeIn;adcData;adcValid;adjust_frames_per_packet;average_out;average_out_delayed;capture_enable;capture_length;channelizer_out;count;dacData;dacValid;data;dataIn;dataOut;data_in;data_in_delayed;data_out;empty;enb;end_in;end_out;frame_end;frame_in;frame_out;frame_start;frames_per_packet;idx;idx_in;idx_out;last_in;last_out;load;load_val;max_idx;num_pulses;over_thresh;pop;pow_in;pow_out;pri_cycles;pulse_width_cycles;ready_in;ready_out;s2mmCtrlM2S;s2mmCtrlS2M;s2mmData;sel;start;start_in;start_out;step;system_time;timeout_limit_in;tx_active;valid;validIn;validOut;valid_in;valid_out

BLOCKTYPE:
Bit Concat;Bit Shift;Bus Creator;Bus Selector;Channelizer;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Constrain Word Length;Data Type Propagation;DataTypeConversion;DataTypeDuplicate;Delay;Demux;Detect Rise Positive;ForEach;From;Goto;HDL Counter;HDL_FIFO;IP Core Register Read;Inport;Logic;MinMax;NCO;Outport;Product;RelationalOperator;Reshape;S-Function;Selector;StateControl;Stored Integer Value Decrement;Sum;Switch;Terminator;Unit Delay Enabled Synchronous

PRODUCT:
DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_radar_signal_detector_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_radar_signal_detector_proc.slx
ANNOTATION: Copyright 2023 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;6;1;4;12;1;1;7;1;1;1
CHECKSUM: 92A8A3A52FB3C2862B420758D6A22D50
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
Compare To Zero;Data Type Conversion;Decrement Stored Integer;Divide;Enable;FreqEnd;FreqStart;Gain;NOT;NumPulses;PRI;PulseWidth;Reference;Register Write;SubSystem;Subtract;Unit Delay;Update Parameters

BLOCKTYPE:
Compare To Zero;DataTypeConversion;EnablePort;Gain;Inport;Logic;Product;Register Write;Stored Integer Value Decrement;Sum;UnitDelay


MODELNAME: soc_radar_signal_detector_pulsegen_interface
BLOCKTYPE: Constant;ModelReference;SliderBlock;Sum;Task Manager
BLOCKTYPE_FREQUENCY: 6;1;1;1;1
CHECKSUM: 10B20149C958515B24E0E437FFAB105D
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_radar_signal_detector_proc.slx___Model_Block___
PATH:
toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_radar_signal_detector_pulsegen_interface.slx

BLOCK:
Add;Ending Frequency Offset;Number of Pulses;Output gain;Pulse Generator Update;Pulse Repetition Interval;Pulse Width;Reference;Slider;Starting Frequency;Task Manager


MODELNAME: soc_radar_signal_detector_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_radar_signal_detector_top.slx
BLOCKTYPE_FREQUENCY: 1;17;6;1;1;1;1;4;1;7;2;3;1;1;11;1;1;3;1;3
CHECKSUM: 1AAF39F4AE97795FAC14E00043E7DD38
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 Wideband Radar Signal Detection and CaptureUsing Xilinx RFSoC Device Copyright 2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;AXI4-Stream to Software;Add;Constant;DMA Read Sim;Data Type Conversion;Decrement Stored Integer;Delay;Divide;Enable;Enabled Subsystem;Ending Frequency Offset;Event Listener;FPGA;Gain;IO Data Sink;In;Initialize Function;Loopback Channel;Number of Pulses;Out;Output gain;Processor;Pulse Generator Update;Pulse Repetition Interval;Pulse Width;RF Data Converter;Read DMA Packet;Reference;Register Write;Starting Frequency;SubSystem;Subtract;Task Manager;Terminator;dmaData;dmaRdDone;dmaRdEvent;dmaRdMsg

BLOCKTYPE:
AXI4-Stream to Software;Constant;DataTypeConversion;Delay;Demux;EnablePort;EventListener;Gain;IO Data Sink;Inport;ModelReference;Outport;Product;RF Data Converter;Register Write;S-Function;Stored Integer Value Decrement;Sum;Task Manager;Terminator

EXTERNALFILE_REFERENCE:
soc_radar_signal_detector_fpga.slx___Model_Block___soc_radar_signal_detector_proc.slx___Model_Block___


MODELNAME: soc_range_doppler_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_range_doppler_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;1;1;2;2;4;2;12;4;2;13;2;53;12;4;2;1;2;2;1;4;8;77;3;3;3;1;74;1;4;6;1;3;1;6;11;2;2;1;11;3;15;3
CHECKSUM: 852B53596BD8F236285AFF3D369FF29F
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 Xilinx devices: - Set D1 = 1 or 2 to trade off speed &amp; FF resources - Set D2-D5 = 1 to fully leverage DSP48 pipelines - Use sync reset Intel FPGAs: - Set D1 = 1 or 2 depending on device family - Set D5 = 1; D2, D3, D4 = 0 - Use async reset  Modulo arithmetic Assumes subtraction result range is from -MAX_DELAY to MAX_DELAY-2  2x Vector FIR Account for pipeline delays in transmitter Copyright 2021 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;ADC Interface;AND;Add;Bit Concat;Bit Slice;Compare To Constant;Compare To Zero;Complex to Real-Imag;Constant;D1_;D2_;D3_;D4_;D5_;DAC Interface;DMA Interface;Data Type Conversion;Data Type Duplicate;Data Type Propagation;Delay;Demux;Direct Lookup Table (n-D);Extract Bits;Filter Delay;For Each;From;Generate Tx Signal;Goto;HDL Complex Multiply 3Mult5Add;HDL Counter;HW RAM Delay;Hamming Window;I;IP Core Register Read;In;Logical Operator;MATLAB Function;Matched Filter;Multiple Target Emulator;Multiport Switch;NCO HDL Optimized;Out;Pack Complex Vector;Pack Data;Pack Vector;Pack Vector I;Pack Vector Q;Pipeline Delay;PipelineDelay;Product;Q;RAM_ctrl;Radar Target Emulator;Range Doppler Tx-Rx;Range Processing;RangeDimCounter;Real-Imag to Complex;Reference;Relational Operator;Reshape;RxActive;Scope;Set Complexity;Signal Specification;Simple Dual Port RAM;SoC Bus Creator;SoC Bus Selector;Stream FIFO;SubSystem;Subtract;Subtract pipeline delay cycles;Sum;Sum Channels;Sum of Elements;Switch;System Controller;System Controller Fcn;Terminator;Tx Signal LUT;TxActive;Unit Delay;Unpack Data;Unpack Vector;Unpack Vector I;Unpack Vector Q;Variable Delay RAM Based;Variable Delay RAM-based;Vector Concatenate;VelDimCounter;active;adc1IDataIn;adc1QDataIn;adc1Validin;adc2IDataIn;adc2QDataIn;adc2ValidIn;ch;cpi_length;cpi_start;d;dac7IDataOut;dac7QDataOut;dac7ValidOut;dac8IData;dac8QData;dac8Valid;dataIOut;dataIn;dataOut;dataQOut;data_in;data_out;delay;din;dmaS2MMCtrlIn;dmaS2MMCtrlOut;dmaS2MMDataOut ;dout;emIDataIn;emIDataOut;emQDataIn;emQDataOut;emValidOut;emValidin;enable;gain;idx;inc;pack_vector;pack_vector_complex;packed_in;rd_addr;rd_addr_ctrl;readyIn;ref;rxIData;rxQData;rxValid;rx_active;rx_delay_cycles;s2mm_dma_data;s2mm_dma_ready;s2mm_dma_valid;sub_filter_even;sub_filter_odd;tlast no-op;txIData;txQData;txValid;tx_active;u;validIn;validOut;valid_in;valid_out;vec_out;wr_addr;wr_addr_ctrl;wr_en;y

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Convert packed word to vector.;Data Type Propagation;DataTypeConversion;DataTypeDuplicate;Delay;Demux;DiscreteFir;Extract Bits;ForEach;From;Goto;HDL Complex Multiplier (3 Multiply, 5 Add);HDL Counter;IP Core Register Read;Inport;Logic;LookupNDDirect;MultiPortSwitch;NCO;Outport;Pack Complex Vector;Pack Vector;Product;RAM-based variable delay;RealImagToComplex;RelationalOperator;Reshape;S-Function;Scope;SignalSpecification;Simple Dual-port RAM;Sum;Switch;Terminator;UnitDelay

PRODUCT:
DSP HDL Toolbox;Fixed-Point Designer;MATLAB;Signal Processing Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_range_doppler_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_range_doppler_proc.slx
BLOCKTYPE_FREQUENCY: 1;2;1;1;6;7;3;1;2;1;1;6;1;33;1;2;34;1;3;1;8;1;4;7;2;2;1;1;9;1;2;1;1;1
CHECKSUM: 08141175FC888E2A68BE325C10401042
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Apply gain factor to account for lack of RF amplifier x2 when specifying as one-way propagation delay Copyright 2021 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;Abs;Asynchronous Task Specification;Bitwise OR;CODEGEN;CPI_Length;CPI_Start;DMAReadFcn;Data;Data ;Data Type Conversion;Display;Dist;Dist to Gain;Divide;Doppler Processing;Enable;Enabled;Exit;Extract Bits;FFT;For Iterator;For Loop;Free Space Path Loss;Freq2Inc;Gain;Ground;HWSW Message Send;In;MATLAB Function;Message;Out;Position;Process CPI;RCS;Radar Target Pos/Vel Update;RadarTargetUpdateFcn;Range to Delay;Rate Transition;Real-Imag to Complex;Reference;Register Write;Relational Operator;Reshape;Rx_Delay_Cycles;SIM;Scope;Selector;Send to Host;Speed to Inc;Speed2Doppler;Square;Stop Simulation;Stream Read;SubSystem;Target_CfgID;Target_Info;Terminator;Time to Clock Cycles;To Workspace;Transpose;Trigger;Tx_Gain;UDP Packet Handler;UDP Read;UDP Write;UDPRxFcn;Unpack Complex;Unpack Data;Unpack uint32 samples;Update Target Info Config;Variant;Velocity;Width;cfgID;cpiData;dmaRdData;dmaRdDone;dmaRdTask;enabled;idx;length;packet;targetDists;targetInfoIn;targetPosition;targetSpeeds;targetVelocity;u;udpRxData;udpRxTask;udpTxData;udpTxMsg;y

BLOCKTYPE:
Abs;AsynchronousTaskSpecification;Bitwise Operator;Constant;DataTypeConversion;Demux;Display;EnablePort;Extract Bits;FFT;ForIterator;Gain;Ground;Inport;MATLABSystem;Math;Outport;Product;RateTransition;RealImagToComplex;Register Write;RelationalOperator;Reshape;S-Function;Scope;Selector;Stop;Stream Read;Terminator;ToWorkspace;TriggerPort;UDP Read;UDP Write;Width

PRODUCT:
DSP System Toolbox;Embedded Coder;Fixed-Point Designer;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_range_doppler_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_range_doppler_top.slx
ANNOTATION: Pulse-Doppler Radar Using Xilinx RFSoC Device Copyright 2021-2022 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;4;2;1;4;1;1;12;2;11;1;1;2;1;1;2
CHECKSUM: F91AFDE3228D4BEA71F616A85F3171F1
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_range_doppler_fpga.slx___Model_Block___soc_range_doppler_proc.slx___Model_Block___
BLOCK:
 Demux ; SFunction ; Terminator ;AXI4-Stream to Software;Colored Noise;Data Type Conversion;Delay;FPGA;Gain;Host UDP Interface;Host UDP control;IO Data Sink;IO Data Source;In;Loop back;Loopback Channel ;Out;Processor;Processor Model;RF Data Converter;Reference;SubSystem;Sum;Task Manager;adc;dac;dmaRdData;dmaRdDone;dmaRdEvent;rx_data;rx_length;rx_valid;tx_data;tx_length;tx_valid;udpRxData;udpRxEvent;udpRxMsg;udpTxData;udpTxMsg

BLOCKTYPE:
AXI4-Stream to Software;DataTypeConversion;Delay;Demux;Gain;IO Data Sink;IO Data Source;Inport;ModelReference;Outport;RF Data Converter;S-Function;Sum;Task Manager;Terminator;dsp.simulink.ColoredNoise

PRODUCT:
DSP System Toolbox;Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_rfsoc_IQ_datacapture_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_rfsoc_IQ_datacapture_fpga.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 49;1;1;16;1;2;16;32;19;2;2;102;1;4;1;18;231;2;1;2;187;32;16;2;1
CHECKSUM: CFC441F0B9FE32A917EA85809ACB9FC3
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
ADC Capture;ADCSelect;ADC_Valid;ADC_data;AND;Bit Concat;Bus Creator;Bus Selector;Channel1_Scaling;Channel2_Scaling;Channel3_Scaling;Channel4_Scaling;Channel5_Scaling;Channel6_Scaling;Channel7_Scaling;Channel8_Scaling;Compare To Constant;Compare To Zero;Complex to Real-Imag;Concatenate_IO_Data_;Constant;Counter Limited;DAC Tone Generation;Data Type Conversion;Delay;Downsampler;Enable;First sample Im;First sample Re;Gain;IP Core Register Read;IP Core Register Read_;In;Logical Operator;Multiport Switch;NCO;NCO10_Valid;NCO10_tData_I;NCO10_tData_Q;NCO11_Valid;NCO11_tData_I;NCO11_tData_Q;NCO12_Valid;NCO12_tData_I;NCO12_tData_Q;NCO13_Valid;NCO13_tData_I;NCO13_tData_Q;NCO14_Valid;NCO14_tData_I;NCO14_tData_Q;NCO15_Valid;NCO15_tData_I;NCO15_tData_Q;NCO16_Valid;NCO16_tData_I;NCO16_tData_Q;NCO1_Valid;NCO1_tData_I;NCO1_tData_Q;NCO2_Valid;NCO2_tData_I;NCO2_tData_Q;NCO3_Valid;NCO3_tData_I;NCO3_tData_Q;NCO4_Valid;NCO4_tData_I;NCO4_tData_Q;NCO5_Valid;NCO5_tData_I;NCO5_tData_Q;NCO6_Valid;NCO6_tData_I;NCO6_tData_Q;NCO7_Valid;NCO7_tData_I;NCO7_tData_Q;NCO8_Valid;NCO8_tData_I;NCO8_tData_Q;NCO9_Valid;NCO9_tData_I;NCO9_tData_Q;NCO_Vector_samples;NCO_tDataI;NCO_tDataQ;Product;Reference;Second sample Im;Second sample Re;SubSystem;Subsystem;Switch;Terminator;Trigger;adc;adc10dataI;adc10dataQ;adc10valid;adc11dataI;adc11dataQ;adc11valid;adc12dataI;adc12dataQ;adc12valid;adc13dataI;adc13dataQ;adc13valid;adc14dataI;adc14dataQ;adc14valid;adc15dataI;adc15dataQ;adc15valid;adc16dataI;adc16dataQ;adc16valid;adc1data;adc1dataI;adc1dataQ;adc1valid;adc2dataI;adc2dataQ;adc2valid;adc3dataI;adc3dataQ;adc3valid;adc4dataI;adc4dataQ;adc4valid;adc5dataI;adc5dataQ;adc5valid;adc6dataI;adc6dataQ;adc6valid;adc7dataI;adc7dataQ;adc7valid;adc8dataI;adc8dataQ;adc8valid;adc9dataI;adc9dataQ;adc9valid;adcOut;adcSelect;adcT0Ch0IData;adcT0Ch0QData;adcT0Ch0Valid;adcT0Ch1IData;adcT0Ch1QData;adcT0Ch1Valid;adcT0Ch2IData;adcT0Ch2QData;adcT0Ch2Valid;adcT0Ch3IData;adcT0Ch3QData;adcT0Ch3Valid;adcT1Ch0IData;adcT1Ch0QData;adcT1Ch0Valid;adcT1Ch1IData;adcT1Ch1QData;adcT1Ch1Valid;adcT1Ch2IData;adcT1Ch2QData;adcT1Ch2Valid;adcT1Ch3IData;adcT1Ch3QData;adcT1Ch3Valid;adcT2Ch0IData;adcT2Ch0QData;adcT2Ch0Valid;adcT2Ch1IData;adcT2Ch1QData;adcT2Ch1Valid;adcT2Ch2IData;adcT2Ch2QData;adcT2Ch2Valid;adcT2Ch3IData;adcT2Ch3QData;adcT2Ch3Valid;adcT3Ch0IData;adcT3Ch0QData;adcT3Ch0Valid;adcT3Ch1IData;adcT3Ch1QData;adcT3Ch1Valid;adcT3Ch2IData;adcT3Ch2QData;adcT3Ch2Valid;adcT3Ch3IData;adcT3Ch3QData;adcT3Ch3Valid;adcTdata;adcTvalid;captureDataOut;chCtrlIn;chCtrlOut;chData;chValid;count;dacT0Ch0IData;dacT0Ch0QData;dacT0Ch0Valid;dacT0Ch1IData;dacT0Ch1QData;dacT0Ch1Valid;dacT0Ch2IData;dacT0Ch2QData;dacT0Ch2Valid;dacT0Ch3IData;dacT0Ch3QData;dacT0Ch3Valid;dacT1Ch0IData;dacT1Ch0QData;dacT1Ch0Valid;dacT1Ch1IData;dacT1Ch1QData;dacT1Ch1Valid;dacT1Ch2IData;dacT1Ch2QData;dacT1Ch2Valid;dacT1Ch3IData;dacT1Ch3QData;dacT1Ch3Valid;dacT2Ch0IData;dacT2Ch0QData;dacT2Ch0Valid;dacT2Ch1IData;dacT2Ch1QData;dacT2Ch1Valid;dacT2Ch2IData;dacT2Ch2QData;dacT2Ch2Valid;dacT2Ch3IData;dacT2Ch3QData;dacT2Ch3Valid;dacT3Ch0IData;dacT3Ch0QData;dacT3Ch0Valid;dacT3Ch1IData;dacT3Ch1QData;dacT3Ch1Valid;dacT3Ch2IData;dacT3Ch2QData;dacT3Ch2Valid;dacT3Ch3IData;dacT3Ch3QData;dacT3Ch3Valid;scaleIn;scaleOut;y

BLOCKTYPE:
Bit Concat;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Constant;Counter Limited;DataTypeConversion;Delay;EnablePort;Extract Bits;Gain;IP Core Register Read;Inport;Logic;MultiPortSwitch;NCO;Outport;Product;Switch;Terminator;TriggerPort


MODELNAME: soc_rfsoc_IQ_datacapture_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_rfsoc_IQ_datacapture_top.slx
BLOCKTYPE_FREQUENCY: 1;16;18;2;18;1;1;1;1;1
CHECKSUM: 957AFD052CE690A6161038EB821C8220
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
IO Data/ Test bench Processor Memory  Copyright 2020-2022 The MathWorks, Inc.  Transmit and Receive a Tone Using RFSoC Device FPGA RF I/O

BLOCK:
ADC Captured Scope Output;ADC Captured Signal;AXI4-Stream to Software;Delay;FPGA Data Capture;Processor;Processor - Frame based processing;RF Data Converter;RF Loopback;Rate Transition;Reference;SubSystem;Task Manager;adc10In;adc11In;adc12In;adc13In;adc14In;adc15In;adc16In;adc1In;adc2In;adc3In;adc4In;adc5In;adc6In;adc7In;adc8In;adc9In;dac10Out;dac11Out;dac12Out;dac13Out;dac14Out;dac15Out;dac16Out;dac1Out;dac2Out;dac3Out;dac4Out;dac5Out;dac6Out;dac7Out;dac8Out;dac9Out;dataIn;dataOut;dataTask;done

BLOCKTYPE:
AXI4-Stream to Software;Delay;Inport;ModelReference;Outport;RF Data Converter;RateTransition;Scope;SpectrumAnalyzer;Task Manager

EXTERNALFILE_REFERENCE:
soc_rfsoc_IQ_datacapture_fpga.slx___Model_Block___soc_rfsoc_IQ_datacapture_proc.slx___Model_Block___


MODELNAME: soc_rfsoc_datacapture
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_rfsoc_datacapture.slx
BLOCKTYPE_FREQUENCY: 1;8;10;2;10;1;1;1;2;1
CHECKSUM: 3CCA31BFCB20E5C0FA4A328E329F53BA
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_rfsoc_datacapture_fpga.slx___Model_Block___soc_rfsoc_datacapture_proc.slx___Model_Block___
ANNOTATION:
RF I/O IO Data/ Test bench Processor FPGA Memory  Copyright 2020-2022 The MathWorks, Inc.  Transmit and Receive a Tone Using RFSoC Device

BLOCK:
ADC Captured Scope Output;ADC Captured Signal;AXI4-Stream to Software;DAC Output;Delay;FPGA Data Capture;Processor;Processor - Frame based processing;RF Data Converter;RF Loopback;Rate Transition;Reference;SubSystem;Task Manager;adc1In;adc2In;adc3In;adc4In;adc5In;adc6In;adc7In;adc8In;dac1Out;dac2Out;dac3Out;dac4Out;dac5Out;dac6Out;dac7Out;dac8Out;dataIn;dataOut;dataTask;done


MODELNAME: soc_rfsoc_datacapture_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_rfsoc_datacapture_fpga.slx
BLOCKTYPE_FREQUENCY: 1;1;8;1;2;8;11;2;4;66;1;4;30;11;115;3;1;4;64;32;9;8;4;1
CHECKSUM: 762A16E1A558456155BACC23C29A41CD
PRODUCT: DSP HDL Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Bitconcat  As processor needs time in the order of milliseconds to complete a task, down sampling the data rate to meet the processor task duration.  Same sinusoid with different scaling is going to all the DAC channels.   Using 4 NCOs to generate 4 samples in one clock  Not modeling ready since HDL coder models it during IP core generation.  Copyright 2020 The MathWorks, Inc.  Not modeling TLAST since HDL coder models it during IP core generation.

BLOCK:
64BitSample;ADC Capture;AND;Add;Bit Concat;Bus Creator;Bus Selector;Channe4_Scaling;Channe7_Scaling;Channel Select;Channel1_Scaling;Channel2_Scaling;Channel3_Scaling;Channel5_Scaling;Channel6_Scaling;Channel8_Scaling;Compare To Constant;Compare To Zero;Constant;Counter Limited;DAC Tone Generation;Data Type Conversion;Delay;Downsampler;Enable;First sample;Fourth sample;Gain;IP Core Register Read;In;Logical Operator;NCO;NCO1_Valid;NCO1_tData;NCO2_Valid;NCO2_tData;NCO3_Valid;NCO3_tData;NCO4_Valid;NCO4_tData;NCO5_Valid;NCO5_tData;NCO6_Valid;NCO6_tData;NCO7_Valid;NCO7_tData;NCO8_Valid;NCO8_tData;NCO_Vector_samples;NCO_tData;Product;Reference;Sample;Second sample;SubSystem;Subsystem;Switch;Terminator;Third sample;Trigger;adc1DataIn;adc1Valid;adc2DataIn;adc2Valid;adc3DataIn;adc3Valid;adc4DataIn;adc4Valid;adc5DataIn;adc5Valid;adc6DataIn;adc6Valid;adc7DataIn;adc7Valid;adc8DataIn;adc8Valid;adcT0Ch0Data;adcT0Ch0Valid;adcT0Ch1Data;adcT0Ch1Valid;adcT1Ch0Data;adcT1Ch0Valid;adcT1Ch1Data;adcT1Ch1Valid;adcT2Ch0Data;adcT2Ch0Valid;adcT2Ch1Data;adcT2Ch1Valid;adcT3Ch0Data;adcT3Ch0Valid;adcT3Ch1Data;adcT3Ch1Valid;adcTdata;adcTvalid;captureDataOut;chCtrlIn;chCtrlOut;chData;chValid;count;dacT0Ch0Data;dacT0Ch0Valid;dacT0Ch1Data;dacT0Ch1Valid;dacT0Ch2Data;dacT0Ch2Valid;dacT0Ch3Data;dacT0Ch3Valid;dacT1Ch0Data;dacT1Ch0Valid;dacT1Ch1Data;dacT1Ch1Valid;dacT1Ch2Data;dacT1Ch2Valid;dacT1Ch3Data;dacT1Ch3Valid;scaleIn;scaleOut;shift 16 bits;shift 32 bits;shift 48 bits;y

BLOCKTYPE:
Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;Constant;Counter Limited;DataTypeConversion;Delay;EnablePort;Extract Bits;Gain;IP Core Register Read;Inport;Logic;MultiPortSwitch;NCO;Outport;Product;Sum;Switch;Terminator;TriggerPort


MODELNAME: soc_waveform_tx_zcu111_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_waveform_tx_zcu111_fpga.slx
BLOCKTYPE_FREQUENCY: 4;16;2;2;9;10;5;4;2;4;10;2;18;55;8;5;3;39;1;27;3;2;197;70;2;168;2;3;8;4;20;2;2;9;11;32;4;7
CHECKSUM: 58A1B13308EEE106BE2424805423AA6F
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious WrStart triggers DDR state machine OutputAddr and OutputLen is fed to DDR State Machine Samples are fed into FWFT FIFO with its rdy-valid signal attached.  if VALID_PULSE pulse out a frame start if WAIT_FOR_PULSE check if current/previous pulse differ If TLAST on next clock cycle if valid, pulse frame start detect on next clock cycle if ~valid, be in wait for start state  Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input Route DDR4 Read Data To DAC Start DDR Read After Wr Complete AXI4 MM Writes AXI4 MM Reads axim_rd_m2s - DDR Read AXI4 Stream Master DMA  axim_rd_s2m - DDR Read Ack axim_wr_m2s - DDR Write axim_wr_s2m - DDR Write Ack AXI4 Stream Slave DMA  AXI4 MM Write Registers Give it default non-zero value at start-up time  This is to prevent any left over samples in registers that are not valid Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious DAC: Tile1 Ch3  AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Channel 0 AXI4 MM Read Registers  Copyright 2021 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;<AXIS_Slave_Tlast>;<AXIS_Slave_Valid>;<DataOut>;<signal1>;AFull;AXI4 Master DDR4 Read CtrlIn;AXI4 Master DDR4 Read CtrlOut;AXI4 Master DDR4 Read Data;AXI4 Master DDR4 Write CtrlIn;AXI4 Master DDR4 Write CtrlOut;AXI4 Master DDR4 Write Data;AXI4-Stream DMA Master CtrlIn;AXI4-Stream DMA Master CtrlOut;AXI4-Stream DMA Master Data;AXI4-Stream DMA Master Ready;AXI4-Stream DMA Master Tlast;AXI4-Stream DMA Master Valid;AXI4-Stream DMA Slave CtrlIn;AXI4-Stream DMA Slave CtrlOut;AXI4-Stream DMA Slave Data;AXI4-Stream DMA Slave Ready;AXI4-Stream DMA Slave Tlast;AXI4-Stream DMA Slave Valid;AXI4M_WrComplete;AXI4RdCount;AXI4S;AXI4SDecode;AXI4S_Tready;AXI4WrCount;AXI4_AXISDecodeState;AXI4_DDR4State;AXI4_FIFOCapture_Overflow;AXI4_FIFO_AFULL;AXI4_FIFO_Full;AXI4_FIFO_Num;AXI4_RdCommplete;AXI4_RdGapCount;AXI4_ReadCompleteCount;AXI4_Slave_Ready;AXI4_WRIgnoredCmd;AXI4_WrAddrCmd;AXI4_WrLenCmd;AXI4_WrValidAccum;AXI4_WriteCompleteCount;AXIS_DMA_FIFO_AFull;AXIS_FIFO_Full;AXIS_FIFO_Num;AXIS_FrameInfo;AXIS_MM2S;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;AXIS_OutputAddr;AXIS_OutputLen;AXIS_Slave_Data;AXIS_Slave_TLast;AXIS_Slave_Valid;AccumulatedWrValid;Add;AutoTrigEn;AutoTrigger;AutoTriggerEnable;BackPressureCounterEn;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CaptureFIFONum;CaptureFIFONumReg;CaptureOverflowCount;ChScale;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;DAC_DDR4_Transmit;DAC_Mux;DAC_Write;DDR Read Conroller;DDR Write Conroller;DDR4WrAddr;DDR4WrLen;DDR4WrStart;DDR4_DAC_Data;DDR4_RdInfo;DDR4_Wr_State;DDRAddr;DDRWrLen;DDR_Capture_Logic;DDR_Wr_Comp;Data;Data Type Conversion;DataAvailable;DataCaptureEn;DataOut;DataPushFrequency;DebugBus;DebugInput;DebugReg;DebugRegisters;DecodeFrameInfo;DecodeState;Decode_AXIS_Frame;Decode_State_Machine;Decode_State_Machine_OLD;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Detect Start Of AXI4S Frame;DetectHeader;Display;EnableAuto;EnableConsecutiveFrames;EnumToInteger;FIFO_DataAvail;FWFT_FIFO;FormatData;FrameAddrWr;FrameLen;FrameSize;FrameSizeInput;FrameSizeRd;FrameStartDetect;From;Gain;Goto;HDL Counter;HDL FIFO;HDL_IP;IgnoreCmdPulse;IgnoredCmd;In;Increment;IntOut;IterationNum;Logical Operator;MATLAB Function;MM2S_Data;MM2S_Ready;MM2S_TLast;MM2S_Valid;MaxCount;MuteDAC;NCO HDL Optimized;NCOIncrement;NCO_DAC_Ch0_AXI;NCO_Process;NCO_Vector_DACI;NCO_Vector_DACQ;NCO_incr_AXI;NOT;NotIdle;OffsetAddr;Out;OutputAddr;OutputLen;Product;Q;R;RdAddr;RdData;RdFrameAddrInput;RdFrameAuto;RdFrameIterations;RdFrameManual;RdGapCount;RdIterations;RdLen;RdLoopActive;RdMode;RdStart;RdTrigger;RdTriggerMode;ReadActive;ReadCompleteCount;ReadFrameAddr;ReadFrameIterations;ReadFrameSize;ReadTriggerMode;Reference;Relational Operator;S;S2MM_Data;S2MM_TLast;S2MM_Tready;S2MM_Valid;SW_en;Scale;ScaleCh;SelectRdTriggerSource;Selector;Signal Conversion;Signal Specification;SoC Bus Creator;SoC Bus Selector;State;State Control;StateMachine;StateOutput;StoreLengthAddr;StreamEn;StreamEnable;SubSystem;Subsystem;Switch;TData;TDataIn;TDataOut;TLast;TLastTAG;TReady;TValid;Terminator;Tile0 ADC Ch0 IData;Tile0 ADC Ch0 QData;Tile0 ADC Ch0 Valid;Tile1 DAC Ch2 IData;Tile1 DAC Ch2 QData;Tile1 DAC Ch2 Valid;ToggleTLAST;Trig;Trigger;TriggerAuto;TriggerCapture;TriggerFreq;TriggerFrequency;TriggerManual;TriggerRisingEdge;Unit Delay;UseDUTNCO;Valid;ValidHeaderPkt;ValidOut;ValidPkt;Vector Concatenate;WrAddrCmd;WrLenCmd;WrStart;WrStartPulse;WrValid;WriteCompleteCount;WriteToDAC;adcIData;adcQData;adcValid;afull;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_wr_data;axim_wr_m2s;axim_wr_s2m;burst_len;cache_reg;count_out;data_i;data_o;ddr_read_done;ddr_write_done;debug_state;detect_increase;dtci;empty_i;empty_o;enb;full;fwft_logic;gap_counter;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;pulseOut;push;ram_addr;rd_ack;rd_ack_i;rd_addr;rd_addr_base;rd_aready;rd_avalid;rd_dvalid;rd_len;sr_latch;start;stateMeasure;state_machine;tlast;u;valid;valid_out;wasted_cycle_cnt;wr_addr;wr_complete;wr_data;wr_len;wr_ready;wr_valid;y

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;NCO;Outport;Product;RelationalOperator;S-Function;Selector;SignalConversion;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay

PRODUCT:
DSP HDL Toolbox;Embedded Coder;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_waveform_tx_zcu111_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_waveform_tx_zcu111_proc.slx
BLOCKTYPE_FREQUENCY: 2;1;13;1;1;1;1;2;1;11;34;2;13;1;1;1;1;4;2
CHECKSUM: FD830F686E753EBCB5DA8C43F278C917
PRODUCT: Embedded Coder;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
 AXI4 Rd Select 1 - read automatically after a write transaction is complete 0 - manual triggered reads with frame lengths and address  Copyright 2021 The MathWorks, Inc.

BLOCK:
 Demux ; Ground ; SFunction ; Terminator ;AXI4RdCount;AXI4WrCount;Asynchronous Task Specification;AutoTriggerEnable;Buffer;ChScale;Compare To Constant;Constant;Delay;Enable;Enable DUT DDR Read;Event Listener;FrameSize;Freq (MHz);Gain;Initialize Function;NCOIncrement;ReadActive;ReadFrameAddr;ReadFrameIterations;ReadFrameSize;ReadTriggerMode;Reference;Register Read;Register Write;Stream Read;Stream Write;StreamEnable;SubSystem;Subsystem;Terminator;Trigger;TriggerCapture;TriggerFrequency;UseDUTNCO;dataReadTask;dataWriteTask;done;msg;readDataIn;readDataOut;readDone;waveFormReader;writeDataOut;writeDone

BLOCKTYPE:
AsynchronousTaskSpecification;Compare To Constant;Constant;Delay;Demux;EnablePort;EventListener;Gain;Ground;Inport;Outport;Register Read;Register Write;S-Function;Slider Gain;Stream Read;Stream Write;Terminator;TriggerPort


MODELNAME: soc_waveform_tx_zcu111_top
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_waveform_tx_zcu111_top.slx
BLOCKTYPE_FREQUENCY: 1;1;4;4;8;1;4;9;2;17;1;2;1;6;1;2;1
CHECKSUM: FD475E03FBA2E3B33205AACEAF714D5D
PRODUCT: Embedded Coder;Simscape;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_waveform_tx_zcu111_fpga.slx___Model_Block___soc_waveform_tx_zcu111_proc.slx___Model_Block___
ANNOTATION:
 Transmit a Signal Waveform Using DDR4 on Xilinx RFSoC Device  Copyright 2021-2023 The MathWorks, Inc.

BLOCK:
ADC Spectrum;AXI4 Random Access Memory;AXI4-Stream to Software;AXI4RdCount;AXI4WrCount;AutoTriggerEnable;Bit Slice;ChScale;DAC Spectrum;Data Type Conversion;Enable;Extract Bits;FPGA;FrameSize;NCOIncrement;Packed data;PlotDACData;Processor;Processor - Frame based processing;RT;ReadActive;ReadFrameAddr;ReadFrameIterations;ReadFrameSize;ReadTriggerMode;Real-Imag to Complex;Reference;Register Channel;Reshape;Software to AXI4-Stream;StreamEnable;SubSystem;Task Manager;TriggerCapture;TriggerFrequency;Unpack data;Unpacked data;UseDUTNCO;Vector Concatenate;dacIData;dacQData;dataReadTask;dataWriteTask;readDataIn;readDataOut;readDone;writeDataOut;writeDone

BLOCKTYPE:
AXI4 Random Access Memory;AXI4-Stream to Software;Bit Slice;Concatenate;DataTypeConversion;EnablePort;Extract Bits;Inport;ModelReference;Outport;RateTransition;RealImagToComplex;Register Channel;Reshape;Software to AXI4-Stream;SpectrumAnalyzer;Task Manager


MODELNAME: soc_waveform_tx_zcu216_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/soc_waveform_tx_zcu216_fpga.slx
BLOCKTYPE_FREQUENCY: 4;16;2;2;9;10;5;4;2;4;10;2;18;55;8;5;3;39;1;27;3;2;197;70;2;168;2;3;8;4;20;2;2;9;11;32;4;7
CHECKSUM: C24F29D138F5A7D187D1553F61215727
PRODUCT_BASECODE: XILINX_BLOCKSET
ANNOTATION:
Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious WrStart triggers DDR state machine OutputAddr and OutputLen is fed to DDR State Machine Samples are fed into FWFT FIFO with its rdy-valid signal attached.  if VALID_PULSE pulse out a frame start if WAIT_FOR_PULSE check if current/previous pulse differ If TLAST on next clock cycle if valid, pulse frame start detect on next clock cycle if ~valid, be in wait for start state  Trigger every 0.5 sec by default Pause counter when experiencing backpressure Handle edge-case if were at the max counter value and we have back-pressure, do not reset just yet. Wait for back pressure to clear then a reset can be applied Count to N samples specified by AXI-lite consec frames input Route DDR4 Read Data To DAC Start DDR Read After Wr Complete AXI4 MM Writes AXI4 MM Reads axim_rd_m2s - DDR Read AXI4 Stream Master DMA  axim_rd_s2m - DDR Read Ack axim_wr_m2s - DDR Write axim_wr_s2m - DDR Write Ack AXI4 Stream Slave DMA  AXI4 MM Write Registers Give it default non-zero value at start-up time  This is to prevent any left over samples in registers that are not valid Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious Overflows will occur if AXI4 Master does no respond in a timely manner to indicate it is safe to WRITE. FIFO will keep filling up while it waits and if enough time has passed during capture phase FIFO will overflow and drop samples A value of >0 indicates that the frame is not contigious DAC: Tile1 Ch3  AXI4-Stream DMA Slave AXI4-Stream DMA Master AXI4 MM Write Registers From RFDC ADC Channel 0 AXI4 MM Read Registers  Copyright 2021 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ;<AXIS_Slave_Tlast>;<AXIS_Slave_Valid>;<DataOut>;<signal1>;AFull;AXI4 Master DDR4 Read CtrlIn;AXI4 Master DDR4 Read CtrlOut;AXI4 Master DDR4 Read Data;AXI4 Master DDR4 Write CtrlIn;AXI4 Master DDR4 Write CtrlOut;AXI4 Master DDR4 Write Data;AXI4-Stream DMA Master CtrlIn;AXI4-Stream DMA Master CtrlOut;AXI4-Stream DMA Master Data;AXI4-Stream DMA Master Ready;AXI4-Stream DMA Master Tlast;AXI4-Stream DMA Master Valid;AXI4-Stream DMA Slave CtrlIn;AXI4-Stream DMA Slave CtrlOut;AXI4-Stream DMA Slave Data;AXI4-Stream DMA Slave Ready;AXI4-Stream DMA Slave Tlast;AXI4-Stream DMA Slave Valid;AXI4M_WrComplete;AXI4RdCount;AXI4S;AXI4SDecode;AXI4S_Tready;AXI4WrCount;AXI4_AXISDecodeState;AXI4_DDR4State;AXI4_FIFOCapture_Overflow;AXI4_FIFO_AFULL;AXI4_FIFO_Full;AXI4_FIFO_Num;AXI4_RdCommplete;AXI4_RdGapCount;AXI4_ReadCompleteCount;AXI4_Slave_Ready;AXI4_WRIgnoredCmd;AXI4_WrAddrCmd;AXI4_WrLenCmd;AXI4_WrValidAccum;AXI4_WriteCompleteCount;AXIS_DMA_FIFO_AFull;AXIS_FIFO_Full;AXIS_FIFO_Num;AXIS_FrameInfo;AXIS_MM2S;AXIS_Master_Data;AXIS_Master_TLAST;AXIS_Master_TReady;AXIS_Master_Valid;AXIS_OutputAddr;AXIS_OutputLen;AXIS_Slave_Data;AXIS_Slave_TLast;AXIS_Slave_Valid;AccumulatedWrValid;Add;AutoTrigEn;AutoTrigger;AutoTriggerEnable;BackPressureCounterEn;Bit Concat;Bit Slice;Bus Creator;Bus Selector;CaptureFIFONum;CaptureFIFONumReg;CaptureOverflowCount;ChScale;Compare To Constant;Compare To Zero;Complex to Real-Imag;ConsecFrames;Constant;DAC_DDR4_Transmit;DAC_Mux;DAC_Write;DDR Read Conroller;DDR Write Conroller;DDR4WrAddr;DDR4WrLen;DDR4WrStart;DDR4_DAC_Data;DDR4_RdInfo;DDR4_Wr_State;DDRAddr;DDRWrLen;DDR_Capture_Logic;DDR_Wr_Comp;Data;Data Type Conversion;DataAvailable;DataCaptureEn;DataOut;DataPushFrequency;DebugBus;DebugInput;DebugReg;DebugRegisters;DecodeFrameInfo;DecodeState;Decode_AXIS_Frame;Decode_State_Machine;Decode_State_Machine_OLD;DefaultConsecFrames;DefaultRegister;Delay;Detect Increase;Detect Start Of AXI4S Frame;DetectHeader;Display;EnableAuto;EnableConsecutiveFrames;EnumToInteger;FIFO_DataAvail;FWFT_FIFO;FormatData;FrameAddrWr;FrameLen;FrameSize;FrameSizeInput;FrameSizeRd;FrameStartDetect;From;Gain;Goto;HDL Counter;HDL FIFO;HDL_IP;IgnoreCmdPulse;IgnoredCmd;In;Increment;IntOut;IterationNum;Logical Operator;MATLAB Function;MM2S_Data;MM2S_Ready;MM2S_TLast;MM2S_Valid;MaxCount;MuteDAC;NCO HDL Optimized;NCOIncrement;NCO_DAC_Ch0_AXI;NCO_Process;NCO_Vector_DACI;NCO_Vector_DACQ;NCO_incr_AXI;NOT;NotIdle;OffsetAddr;Out;OutputAddr;OutputLen;Product;Q;R;RdAddr;RdData;RdFrameAddrInput;RdFrameAuto;RdFrameIterations;RdFrameManual;RdGapCount;RdIterations;RdLen;RdLoopActive;RdMode;RdStart;RdTrigger;RdTriggerMode;ReadActive;ReadCompleteCount;ReadFrameAddr;ReadFrameIterations;ReadFrameSize;ReadTriggerMode;Reference;Relational Operator;S;S2MM_Data;S2MM_TLast;S2MM_Tready;S2MM_Valid;SW_en;Scale;ScaleCh;SelectRdTriggerSource;Selector;Signal Conversion;Signal Specification;SoC Bus Creator;SoC Bus Selector;State;State Control;StateMachine;StateOutput;StoreLengthAddr;StreamEn;StreamEnable;SubSystem;Subsystem;Switch;TData;TDataIn;TDataOut;TLast;TLastTAG;TReady;TValid;Terminator;Tile0 ADC Ch0 IData;Tile0 ADC Ch0 QData;Tile0 ADC Ch0 Valid;Tile0 DAC Ch0 IData;Tile0 DAC Ch0 QData;Tile0 DAC Ch0 Valid;ToggleTLAST;Trig;Trigger;TriggerAuto;TriggerCapture;TriggerFreq;TriggerFrequency;TriggerManual;TriggerRisingEdge;Unit Delay;UseDUTNCO;Valid;ValidHeaderPkt;ValidOut;ValidPkt;Vector Concatenate;WrAddrCmd;WrLenCmd;WrStart;WrStartPulse;WrValid;WriteCompleteCount;WriteToDAC;adcIData;adcQData;adcValid;afull;axim_rd_data;axim_rd_m2s;axim_rd_s2m;axim_wr_data;axim_wr_m2s;axim_wr_s2m;burst_len;cache_reg;count_out;data_i;data_o;ddr_read_done;ddr_write_done;debug_state;detect_increase;dtci;empty_i;empty_o;enb;full;fwft_logic;gap_counter;hdl_fwft_fifo;num;num_i;num_o;out_reg;pop_o;pulseOut;push;ram_addr;rd_ack;rd_ack_i;rd_addr;rd_addr_base;rd_aready;rd_avalid;rd_dvalid;rd_len;sr_latch;start;stateMeasure;state_machine;tlast;u;valid;valid_out;wasted_cycle_cnt;wr_addr;wr_complete;wr_data;wr_len;wr_ready;wr_valid;y

BLOCKTYPE:
Bit Concat;Bit Slice;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;Compare To Zero;ComplexToRealImag;Concatenate;Constant;Conversion Inherited;DataTypeConversion;Delay;Demux;Detect Increase;Display;From;Gain;Goto;HDL Counter;HDL_FIFO;Inport;Logic;NCO;Outport;Product;RelationalOperator;S-Function;Selector;SignalConversion;SignalSpecification;StateControl;Sum;Switch;Terminator;Unit Delay Enabled;UnitDelay

PRODUCT:
DSP HDL Toolbox;Embedded Coder;Fixed-Point Designer;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_OFDM_fpga
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_OFDM_fpga.slx
CHECKSUM: 7233A1F99867211D0B22966106766F49
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: whdlOFDMRx.slx___Model_Block___whdlOFDMTx.slx___Model_Block___
ANNOTATION:
NO HDL Block NO HDL Block  Add Block is used to obtain integer index to Lookup Table Range of x_f=[1,4) S0 S1 S1 S0 S1 S1 Range of x_e=[1,2) NO HDL Block OFDM Transmit and Receive Status Signal Generator <!DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.0//EN http://www.w3.org/TR/REC-html40/strict.dtd> <html><head><meta name=qrichtext content=1 /><style type=text/css> p, li { white-space: pre-wrap; } </style></head><body align=left style= font-family:Arial; font-size:12px; font-weight:400; font-style:normal;> Copyright 2020-2023 The MathWorks, Inc.

BLOCK:
 Demux ; SFunction ; Terminator ; dBtoLinearConverter;1-D Lookup Table;AWGNGenerator;Add;Apply CFO;BER;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;CPECtrl;Capture Data Bits;Channel Control;Compare To Constant;Complex to Real-Imag;ConcatandExtract;Concatention;Constant;Constellation Formation;Conversion;Data Type Conversion;DataIn;DataOut;Delay;Demux;Diagnostic Decoder;Discrete FIR Filter HDL Optimized;Enable;EstimatedCFO;Extract Bits;FIR_Vector_Interp;Falling Edge Detector;From;Function Evaluation;FunctionEvaluation;Gain;GaussianNoiseWithReqVar;GaussianNoiseWithUnitVar;Goto;HDL Counter;In;Logical Operator;MATLAB Function;MT;NCO HDL Optimized;OFDM;OFDM Rx;OFDM Tx;OFDM TxRx;OFDMTx;OFDMTx Channel OFDMRx;Out;Polyphase ;Prepare Inputs;Prepare Outputs;Product;Range Reconstruction;RangeReconstruction;RangeReduction;Real-Imag to Complex;Reference;Relational Operator;RxDataI_In;RxDataQ_In;RxData_Out;RxValidOut;RxValid_In;Select Payload Data;Selector;Send Payload Data;Shift Arithmetic;Signal Conversion;Signal Specification;Sine HDL Optimized;SineCos;SqrtEval;SqrtImplementation;State Control;SubSystem;Subsystem;Subtract;Sum;Switch;TausURNG;TausUniformRandGen;Terminator;To Spectrum Analyzer;To Workspace;Tx Filtered Spectrum Analyzer;Tx Filtered Spectrum Analyzer_CCDF;Tx Filtered Spectrum Analyzer_Convert;Tx Filtered Spectrum Analyzer_PAPR;Tx Filtered Spectrum Analyzer_RelPwr;TxDataI_Out;TxDataQ_Out;TxValid_Out;Unit Delay Enabled Synchronous;ValidIn;ValidOut;Vector Concatenate;Vector Decimation;Vector Decimator;Vector Interpolation;Vectorization;White Gaussian Noise Generator;a;awgn;b;bitCount;bitErrors;chCtrlIn;chCtrlOut;chEqCtrl;codeRate;codeRateIndex;dPoints;dValid;dataIOut;dataI_in;dataIn;dataOut;dataPoints;dataQOut;dataQ_in;dataValid;datain_img;datain_real;dataout_img;dataout_real;decodedCodeRate;decodedModType;decodedRate;diagBus;din_img;din_real;displayReset;dout;e;enableCPECorrec;enableChanEqui;enableInternalLoopback;exp_e;exp_eIn;exp_eOut;exp_f;exp_fIn;exp_fOut;f;freq;freqOffsetEstimate;g;g1(16,15);hPoints;hValid;hView;headerCaptred;headerPoints;headerValid;headerView;impairmentControl;in;insertCFO;internalFeedback;leadingZeroDetector;log;logImplementation;modType;modTypeIndex;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived;nfreq;noise;noiseVar;nxtBit;out;packetValid;pass;passIn;passOut;ready;reset;resetcounter;rst;rxData;rxDataOut;rxValid;rxValidOut;snrdB;sqrt(noisePow/2);txData;txDataOut;txIData;txQData;txValid;txValidOut;txvalid;u;u0(16,16);u0(48,48);u1(16,16);userBits;userBitsValid;valid;validIn;validOut;vin;vout;whdlOFDMRx Model;x;x_e;x_f;y_e;y_f

BLOCKTYPE:
ArithShift;Bit Concat;Bit Shift;Bit Slice;Bitwise Operator;Bus Creator;Bus Selector;BusCreator;BusSelector;Compare To Constant;ComplexToRealImag;Concatenate;Constant;DataTypeConversion;Delay;Demux;Discrete FIR Filter;Display;EnablePort;Extract Bits;From;Gain;Goto;HDL Counter;Inport;Logic;Lookup_n-D;ModelReference;NCO;Outport;Product;RealImagToComplex;RelationalOperator;S-Function;Selector;SignalConversion;SignalSpecification;Sine and Cosine HDL optimized block;SpectrumAnalyzer;StateControl;Sum;Switch;Terminator;ToWorkspace;Unit Delay Enabled Synchronous;dsp.simulink.PowerMeter

BLOCKTYPE_FREQUENCY:
14;4;21;16;21;1;1;1;4;1;4;3;15;45;77;4;16;2;2;2;4;4;4;9;137;7;11;2;1;136;9;3;1;2;8;16;1;2;1;2;21;11;9;1;2;1

PRODUCT:
DSP HDL Toolbox;DSP System Toolbox;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_OFDM_hostUDPReceive
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_OFDM_hostUDPReceive.slx
ANNOTATION: Copyright 2020-2023 The MathWorks, Inc. OFDM Transmit and Receive Host UDP Receive Model
BLOCKTYPE_FREQUENCY: 2;1;7;10;2;1;3;20;1;10;2
CHECKSUM: AC0D41DD6A2D1A5E48CDDCE683D7A292
PRODUCT: Communications Toolbox;Simulink;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Denormalization ;Bit Slice;Constellation Diagram;Control Scope;Data Type Conversion;Display;Enable;EstimatedCFO;In;Real-Imag to Complex;Reference;Selector;Status Signals;StatusSignals;SubSystem;UDP Receive Constellation;UDP Receive Status;Visualize Constellation;decodedCodeRate;decodedModType;nDataCRCFail;nDataCRCPass;nFramesSynced;nHeaderCRCFail;nHeaderCRCPass;nbitErrors;nbitReceived

BLOCKTYPE:
Bit Slice;ConstellationDiagram;DataTypeConversion;Display;EnablePort;Gain;Inport;Outport;RealImagToComplex;Selector;UDP Receive


MODELNAME: soc_OFDM_hwtop
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_OFDM_hwtop.slx
BLOCKTYPE_FREQUENCY: 2;1;1;14;1;3;2;10;1;1;3;2;6;1;2;1;1;1
CHECKSUM: E9C92C30E435ABE58D4D9829AEFB09FB
PRODUCT_BASECODE: XILINX_BLOCKSET
EXTERNALFILE_REFERENCE: soc_OFDM_fpga.slx___Model_Block___
ANNOTATION:
<!DOCTYPE HTML PUBLIC -//W3C//DTD HTML 4.0//EN http://www.w3.org/TR/REC-html40/strict.dtd> <html><head><meta name=qrichtext content=1 /><style type=text/css> p, li { white-space: pre-wrap; } </style></head><body align=left style= font-family:Arial; font-size:12px; font-weight:400; font-style:normal;> Copyright 2020-2023 The MathWorks, Inc. External I/O  OFDM Transmit and Receive Hardware with RFSoC FPGA Tx Control  code rate: 0 =&gt; 1/2 1 =&gt; 2/3 2 =&gt; 3/4 3 =&gt; 5/6  packetValid Enable/disable valid data transmission  CFO Range -7400 to 7400 Hz   snr Range 0 to 63 dB Channel Control  channel will be applied only if enableInternalLoopback is true  Enable/disable Channel Equalization and CPE Correction Rx Control Display Control  Reset the Display Blocks and switch between header and data constellation

BLOCK:
Bit Slice;CFO;CodeRate;Constant;Constellation Diagram;Data Type Conversion;Delay;Display;DisplayReset;Enable;FPGA Algorithm;In;Logical Operator;Manual Switch;ModType;Normalized by fs;RF Data Converter;RF Loopback;Real-Imag to Complex;Reference;SNRdB;SoC Bus Creator;SoC Bus Selector;SubSystem;Terminator;Visualize Constellation;adc;dac;initial reset;input

BLOCKTYPE:
Bit Slice;Bus Creator;Bus Selector;Constant;ConstellationDiagram;DataTypeConversion;Delay;Display;EnablePort;Gain;Inport;Logic;ManualSwitch;ModelReference;Outport;RF Data Converter;RealImagToComplex;Terminator

PRODUCT:
Communications Toolbox;DSP System Toolbox;MATLAB;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices


MODELNAME: soc_OFDM_proc
PATH: toolbox/soc/supportpackages/xilinxsoc/xilinxsocexamples/whdl/soc_OFDM_proc.slx
ANNOTATION: Copyright 2020 The MathWorks, Inc.
BLOCKTYPE_FREQUENCY: 1;1;13;3;1;1;2;2;68;2;6;52;2;10;10;1;1;1;2
CHECKSUM: 294FF9174A3B1044DFE0CCD242539F9F
PRODUCT: Embedded Coder;Simulink;SoC Blockset;SoC Blockset Support Package for Xilinx Devices
PRODUCT_BASECODE: XILINX_BLOCKSET
BLOCK:
 Denormalization ;Asynchronous Task Specification;CFO;CodeRate;Constant;Data;Data Type Conversion;Decode Status Signals;Delay;Digital Clock;DisplayReset;Enable;EnableCPECCorrec;EnableChanEqui;EnableInternalLoopback;EstimatedCFO;Estimated_CFO;Event driven;HeaderView;In;InsertCFO;Logical Operator;Manual Switch;ModType;Normalized by fs;PacketValid;Processor Algorithm Periodic;Rate Transition;Read Event;ReadRegisters;Reference;Register Read;Register Write;RxData;RxUDPData;SNRdB;StatusReport;Stream Read;SubSystem;Subsystem;System Outputs;UDP Write;Vector Concatenate;WriteRegisters;codeRate;code_Rate;data;dataTask;decodedCodeRate;decodedModType;decoded_CodeRate;decoded_ModType;displayReset;display_Reset;done;enableCPECCorrec;enableCPECorrec;enableChanEqui;enableInternalLoopback;enableInternal_Loopback;enable_CPECCorrec;enable_ChanEqui;headerView;header_View;initial reset;insertCFO;insert_CFO;modType;mod_Type;msg;nDataCRCFail;nDataCRCPass;nDataCRC_Fail;nDataCRC_Pass;nFramesSynced;nFrames_Synced;nHeaderCRCFail;nHeaderCRCPass;nHeaderCRC_Fail;nHeaderCRC_Pass;nbitErrors;nbitReceived;nbit_Errors;nbit_Received;packetValid;packet_Valid;snr_dB;snrdB;statusUDPReport;valid

BLOCKTYPE:
AsynchronousTaskSpecification;Concatenate;Constant;DataTypeConversion;Delay;DigitalClock;EnablePort;Gain;Inport;Logic;ManualSwitch;Outport;RateTransition;Register Read;Register Write;Stream Read;System Outputs;TriggerPort;UDP Write


