Port Name | Bit Width | Routed to Capture Buffer | Available for Trigger Condition |
tp_Gate_B_Hi_tp | 1 | Yes | Yes |
tp_Gate_B_Lo_tp | 1 | Yes | Yes |
tp_Gate_C_Hi_tp | 1 | Yes | Yes |
tp_Gate_C_Lo_tp | 1 | Yes | Yes |
tp_Gate_A_Hi_tp | 1 | Yes | Yes |
tp_Gate_A_Lo_tp | 1 | Yes | Yes |
component FPGADataCapture
port(
clk: in std_logic;
clk_enable: in std_logic;
ready_to_capture: out std_logic;
tp_Gate_B_Hi_tp: in std_logic;
tp_Gate_B_Lo_tp: in std_logic;
tp_Gate_C_Hi_tp: in std_logic;
tp_Gate_C_Lo_tp: in std_logic;
tp_Gate_A_Hi_tp: in std_logic;
tp_Gate_A_Lo_tp: in std_logic);
end component;
u0: FPGADataCapture
port map(
clk=>clk,
clk_enable=>clk_enable,
ready_to_capture=>ready_to_capture,
tp_Gate_B_Hi_tp=>tp_Gate_B_Hi_tp,
tp_Gate_B_Lo_tp=>tp_Gate_B_Lo_tp,
tp_Gate_C_Hi_tp=>tp_Gate_C_Hi_tp,
tp_Gate_C_Lo_tp=>tp_Gate_C_Lo_tp,
tp_Gate_A_Hi_tp=>tp_Gate_A_Hi_tp,
tp_Gate_A_Lo_tp=>tp_Gate_A_Lo_tp);
ready_to_capture
output port open when datacapture
HDL IP is not capturing data continuously. . Generated File | Location |
MATLAB App launch script | hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\launchDataCaptureApp.m |
System object | hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\FPGADataCapture.m |
Generated File | Location |
Capture model | hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\FPGADataCapture_model.slx |