Table of Contents

Generation Summary

The FPGA Data Capture HDL IP generated successfully.

Port Name Bit Width Routed to Capture Buffer Available for Trigger Condition
tp_Gate_B_Hi_tp 1 Yes Yes
tp_Gate_B_Lo_tp 1 Yes Yes
tp_Gate_C_Hi_tp 1 Yes Yes
tp_Gate_C_Lo_tp 1 Yes Yes
tp_Gate_A_Hi_tp 1 Yes Yes
tp_Gate_A_Lo_tp 1 Yes Yes
FPGA vendor: Xilinx
Language: VHDL
Folder: hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture
Component name: FPGADataCapture
Sample depth: 65536
Maximum number of trigger stages: 10
Connection type: JTAG

Integrate Generated IP into Existing FPGA Design



Add the generated HDL files in the hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture directory into your FPGA project. The top-level of the IP core is FPGADataCapture.vhd.
Instantiate the HDL IP datacapture in your HDL code and connect it to the ports you generated for capture and triggers.
Copy and paste the following component declaration into your HDL. Then create the component instantiation based on this declaration.

component FPGADataCapture
port(
    clk: in std_logic;
    clk_enable: in std_logic;
    ready_to_capture: out std_logic;
    tp_Gate_B_Hi_tp: in std_logic;
    tp_Gate_B_Lo_tp: in std_logic;
    tp_Gate_C_Hi_tp: in std_logic;
    tp_Gate_C_Lo_tp: in std_logic;
    tp_Gate_A_Hi_tp: in std_logic;
    tp_Gate_A_Lo_tp: in std_logic);
end component;

Here is an example of the component instantiation code

u0: FPGADataCapture
port map(
    clk=>clk,
    clk_enable=>clk_enable,
    ready_to_capture=>ready_to_capture,
    tp_Gate_B_Hi_tp=>tp_Gate_B_Hi_tp,
    tp_Gate_B_Lo_tp=>tp_Gate_B_Lo_tp,
    tp_Gate_C_Hi_tp=>tp_Gate_C_Hi_tp,
    tp_Gate_C_Lo_tp=>tp_Gate_C_Lo_tp,
    tp_Gate_A_Hi_tp=>tp_Gate_A_Hi_tp,
    tp_Gate_A_Lo_tp=>tp_Gate_A_Lo_tp);

You can leave ready_to_capture output port open when datacapture HDL IP is not capturing data continuously. .
Note: To capture data at multiple trigger stages, set the clk_enable signal to high (1).

Finally, compile and deploy the integrated FPGA design:
  1. Compile the integrated FPGA design to generate a new FPGA programming file.
  2. Make sure that the JTAG cable is connected between your FPGA board and the host computer.
  3. Program the FPGA using the programming tool from FPGA vendor.

Capture Data

Capture Data into MATLAB

  1. Run the generated script hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\launchDataCaptureApp.m to open the Data Capture app.
  2. On the Trigger tab, select the number of trigger stages.
  3. On the Trigger tab, specify a trigger condition for each stage. For single stage, if you do not specify a condition, the default behavior is to capture data immediately.
  4. On the Data Types tab, specify data types for the captured signals.
  5. Click Capture Data to capture data into a workspace variable.
Command-Line Alternative:

You can use the generated System object directly. Set the data types and trigger condition using the methods and properties of the System object, then call the object to capture data. The generated script provides a starting point. You cannot edit the System object itself.
Generated File Location
MATLAB App launch script hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\launchDataCaptureApp.m
System object hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\FPGADataCapture.m
  1. In the generated model, open the FPGA Data Reader block.
  2. Click Launch Signal and Trigger Editor.
  3. On the Trigger tab, select the Number of trigger stages.
  4. On the Trigger tab, specify a trigger condition for each stage. For single stage, if you do not specify a condition, the default behavior is to capture data immediately.
  5. On the Data Types tab, specify data types for the captured signals.
  6. Run the model to capture data.
Generated File Location
Capture model hdl_prj\hdlsrc\pwmTestBench\fpga_data_capture\FPGADataCapture_model.slx