Summary

IP core name	mw_pwm_motcon2
IP core version	1.0
IP core folder	hdl_prj\ipcore\mw_pwm_motcon2_v1_0
IP core zip file name	mw_pwm_motcon2_v1_0.zip
Target platform	Generic Xilinx Platform
Target tool	Xilinx Vivado
Target language	VHDL
Model	pwmTestBench
Model version	6.4
HDL Coder version	3.19
IP core generated on	26-Nov-2021 09:28:11
IP core generated for	mw_pwm_motcon2

Target Interface Configuration

You chose the following target interface configuration for pwmTestBench :

Processor/FPGA synchronization mode: Free running

Target platform interface table:

Port Name	Port Type	Data Type	Target Platform Interfaces	Interface Mapping	Interface Options
En	Inport	boolean	External Port
Counter_Max	Inport	uint16	External Port
Compare_A	Inport	uint16	External Port
Compare_B	Inport	uint16	External Port
Compare_C	Inport	uint16	External Port
Dead_Time_Count	Inport	uint8	External Port
Inverter_En	Outport	boolean	External Port
Gate_A_Hi	Outport	boolean	External Port
Gate_A_Lo	Outport	boolean	External Port
Gate_B_Hi	Outport	boolean	External Port
Gate_B_Lo	Outport	boolean	External Port
Gate_C_Hi	Outport	boolean	External Port
Gate_C_Lo	Outport	boolean	External Port
Gate_B_Hi_tp	Test point	boolean	FPGA Data Capture - JTAG	Trigger and Data
Gate_B_Lo_tp	Test point	boolean	FPGA Data Capture - JTAG	Trigger and Data
Gate_C_Hi_tp	Test point	boolean	FPGA Data Capture - JTAG	Trigger and Data
Gate_C_Lo_tp	Test point	boolean	FPGA Data Capture - JTAG	Trigger and Data
Gate_A_Hi_tp	Test point	boolean	FPGA Data Capture - JTAG	Trigger and Data
Gate_A_Lo_tp	Test point	boolean	FPGA Data Capture - JTAG	Trigger and Data
TestPoint	Test point	boolean (3)	No Interface Specified

Register Address Mapping

The following AXI4-Lite bus accessible registers were generated for this IP core:

Register Name	Address Offset	Description
IPCore_Reset	0x0	write 0x1 to bit 0 to reset IP core
IPCore_Enable	0x4	enabled (by default) when bit 0 is 0x1
IPCore_Timestamp	0x8	contains unique IP timestamp (yymmddHHMM): 2111260928

The AXI4 slave write register readback is OFF for the IP core.
The register address mapping is also in the following C header file for you to use when programming the processor:
include\mw_pwm_motcon2_addr.h
The IP core name is appended to the register names to avoid name conflicts.

IP Core User Guide

Theory of Operation

This IP core is designed to be connected to an embedded processor with an AXI4-Lite interface. The processor acts as master, and the IP core acts as slave. By accessing the generated registers via the AXI4-Lite interface, the processor can control the IP core, and read and write data from and to the IP core.

For example, to reset the IP core, write 0x1 to the bit 0 of IPCore_Reset register. To enable or disable the IP core, write 0x1 or 0x0 to the IPCore_Enable register. To access the data ports of the MATLAB/Simulink algorithm, read or write to the associated data registers.



This IP core also support the External Port interface. To connect the external ports to the FPGA external IO pins, add FPGA pin assignment constraints in the Xilinx Vivado environment.

The AXI4 Slave port to pipeline register ratio selected as 35 in task 3.2 for this model. The default delay to read AXI4 register is one clock cycle. Depending on the selected ratio and IO connected to AXI4 interface, register pipelining is introduced in the read logic of AXI4 registers. For your model AXI4 pipeline register ratio setting 35 is larger than all the readable AXI4 slave registers. Total readable AXI4 slave registers are 1, so no pipelining is added to the AXI4 register read back logic.

Processor/FPGA Synchronization

The Free running mode means there is no explicit synchronization between embedded processor software execution (SW) and the IP core (HW). SW and HW runs independently. The data written from the processor to IP core takes effect immediately, and the data read from the IP core is the latest data available on the IP core output ports.



Xilinx Vivado Environment Integration

This IP Core is generated for the Xilinx Vivado environment. The following steps are an example showing how to integrate the generated IP core into Xilinx Vivado environment:

1. The generated IP core is a zip package file under the IP core folder. Please check the Summary section of this report for the IP zip file name and folder.
2. In the Vivado project, go to Project Settings -> IP -> Repository Manager, add the folder containing the IP zip file as IP Repository.
3. In Repository Manger, click the "Add IP" button to add IP zip file to the IP repository. This step adds the generated IP into the Vivado IP Catalog.
4. In the Vivado project, find the generated IP core in the IP Catalog under category "HDL Coder Generated IP". In you have a Vivado block design open, you can add the generated IP into your block design.
5. Connect the AXI4-Lite port of the IP core to the embedded processor's AXI master port.
6. Connect the clock and reset ports of the IP core to the global clock and reset signals.
7. Assign an Offset Address for the IP core in the Address Editor.
8. Connect external ports and add FPGA pin assignment constraints to constraint file.
9. Generate FPGA bitstream and download the bitstream to target device.

If you are targeting Xilinx Zynq hardwares supported by HDL Coder Support Package for Xilinx Zynq Platform, you can select the board you are using in the Target platform option in the Set Target > Set Target Device and Synthesis Tool task. You can then use Embedded System Integration tasks in HDL Workflow Advisor to help you integrate the generated IP core into Xilinx Vivado environment.

Use FPGA Data Capture

FPGA Data Capture Buffer Size: 65536
FPGA Data Capture Sequence Depth: 10
The FPGA Data Capture related files are located in hdl_prj\ipcore\mw_pwm_motcon2_v1_0\fpga_data_capture

Capture Data into MATLAB

1. Run the generated script launchDataCaptureApp to open the Data Capture app.
2. On the Triggers tab, specify a trigger condition. If you do not specify a condition, the default behavior is to capture data immediately.
3. On the Data Types tab, specify data types for the captured signals.
4. Press the Capture button to capture data into a workspace variable.

Capture Data into Simulink

1. In the generated model FPGADataCapture_model, open the FPGA Data Reader block.
2. Click the "Launch Signal and Trigger Editor" button.
3. On the Triggers tab, specify a trigger condition. If you do not specify a condition, the default behavior is to capture data immediately.
4. On the Data Types tab, specify data types for the captured signals.
5. Run the model to capture data.

IP Core File List

The IP core folder is located at:
hdl_prj\ipcore\mw_pwm_motcon2_v1_0
Following files are generated under this folder:

IP core zip file
mw_pwm_motcon2_v1_0.zip

IP core report
doc\pwmTestBench_ip_core_report.html

IP core HDL source files
hdl\vhdl\mw_pwm_motcon2_src_mw_pwm_motcon2_pkg.vhd
hdl\vhdl\mw_pwm_motcon2_src_Up_Down_Counter.vhd
hdl\vhdl\mw_pwm_motcon2_src_PWM.vhd
hdl\vhdl\mw_pwm_motcon2_src_PWM_Complementary_To_Individual_Gate.vhd
hdl\vhdl\mw_pwm_motcon2_src_Counter.vhd
hdl\vhdl\mw_pwm_motcon2_src_Detect_Rising_Edge.vhd
hdl\vhdl\mw_pwm_motcon2_src_PWM_Dead_Time_For_On_Delay.vhd
hdl\vhdl\mw_pwm_motcon2_src_PWM_AD_FMCMOTCON2.vhd
hdl\vhdl\mw_pwm_motcon2_src_mw_pwm_motcon2.vhd
hdl\vhdl\FPGADataCapture.vhd
hdl\vhdl\hdlverifier_capture_trigger_sequence.vhd
hdl\vhdl\hdlverifier_capture_trigger_condition.vhd
hdl\vhdl\hdlverifier_capture_trigger_combine.vhd
hdl\vhdl\hdlverifier_capture_comparator_1bit.vhd
hdl\vhdl\hdlverifier_jtag_vendor_ip0.vhd
hdl\vhdl\hdlverifier_synchronizer.vhd
hdl\vhdl\hdlverifier_jtag_register.vhd
hdl\vhdl\hdlverifier_data_jtag_rd.vhd
hdl\vhdl\hdlverifier_dcram.vhd
hdl\vhdl\hdlverifier_capture_jtag_core.vhd
hdl\vhdl\hdlverifier_capture_data.vhd
hdl\vhdl\hdlverifier_capture_core.vhd
hdl\vhdl\mw_pwm_motcon2_reset_sync.vhd
hdl\vhdl\mw_pwm_motcon2_dut.vhd
hdl\vhdl\fpga_data_capture.vhd
hdl\vhdl\mw_pwm_motcon2_addr_decoder.vhd
hdl\vhdl\mw_pwm_motcon2_axi_lite_module.vhd
hdl\vhdl\mw_pwm_motcon2_axi_lite.vhd
hdl\vhdl\mw_pwm_motcon2.vhd

IP core C header file
include\mw_pwm_motcon2_addr.h