classdef FILSimulation< matlab.System & coder.ExternalDependency
%FILSimulation connects MATLAB with a FPGA and cosimulate with it by 
%   writing inputs in the FPGA and reading outputs from the FPGA.
%   
%   hdlverifier.FILSimulation is a virtual class and cannot be instantiated
%   directly. In order to use it, launch the FILwizard (>filWizard) and 
%   generate your own custom FILSimulation derived class:
%
%   MYFIL = MyGeneratedFILSimulation
%
%   Step method syntax:
%
%   [out1, out2, ...] = step(MYFIL, in1, in2, ...) connect to the FPGA,
%   write in1, in2, ... to the FPGA and read out1, out2, ... from 
%   the FPGA
%
%   System objects may be called directly like a function instead of using
%   the step method. For example, y = step(MYFIL, x) and y = MYFIL(x) are
%   equivalent.
%
%   FILSimulation methods:
%
%   step        - See above description for use of this method
%   release     - Allow property value and input characteristics changes, and
%                 release connection to FPGA board
%   clone       - Create FILSimulation object with same property values
%   isLocked    - Locked status (logical)
%   programFPGA - Load the programming file in the FPGA
%
%   FILSimulation properties:
%
%   DUTName                  - DUT top level name
%   InputSignals             - Input paths in the HDL code
%   InputBitWidths           - Width in bit of the inputs
%   OutputSignals            - Output paths in the HDL code
%   OutputBitWidths          - Width in bit of the outputs
%   OutputDataTypes          - Data type of the outputs
%   OutputSigned             - Sign of the outputs
%   OutputFractionLengths    - Fraction lengths of the outputs
%   OutputDownsampling       - Downsampling factor and phase of the outputs
%   OverclockingFactor       - Overclocking factor of the hardware
%   SourceFrameSize          - Frame size of the source (only for HDL source block)
%   Connection               - Parameters for the connection with the board
%   FPGAVendor               - Name of the FPGA chip vendor
%   FPGABoard                - Name of the FPGA board
%   FPGAProgrammingFile      - Path of the Programming file for the FPGA
%   ScanChainPosition        - Position of the FPGA in the JTAG scan chain
%   DeviceTree               - Device tree file (only for Ethernet connection on Zynq)
%   IPAddress                - Board IP address (only for Ethernet connection on Zynq)
%   Username                 - Board username(only for Ethernet connection on Zynq)
%   Password                 - Board password (only for Ethernet connection on Zynq)
%   EthernetType             - Ethernet Interface is either PS Ethernet or USB Ethernet (only for Ethernet connection on Zynq)

 
%   Copyright 2012-2023 The MathWorks, Inc.

    methods
        function out=FILSimulation
        end

        function out=getDescriptiveName(~) %#ok<STOUT>
        end

        function out=isSupportedContext(~) %#ok<STOUT>
        end

        function out=programFPGA(~) %#ok<STOUT>
            %programFPGA Load the programming file in the FPGA
            %  programFPGA(MYFIL) loads the bit file through the JTAG cable for
            %  FPGA, or through the Ethernet cable for Zynq.
        end

        function out=updateBuildInfo(~) %#ok<STOUT>
            % We are not located in the std lib area--if we were
            % context.getStdLibInfo would be useful.
        end

    end
    properties
        %Connection Parameters for the connection with the FPGA board
        %  Array containing the parameters for the connection with the
        %  FPGA board: first element is the connection type ('UDP'), or 
        %  ('PCI Express'). If the connection type is UDP, the second
        %  element is the board IP address (string) and third element is 
        %  board MAC address (string). If the connection type is PCI
        %  Express, the second element is the rtIOStream library name and
        %  the third element is the rtIOStream initialization parameters. 
        %  The optional fourth element is protocol parameters.
        %  The default value of this property 
        %  is char('UDP','192.168.0.2','00-0A-35-02-21-8A').
        Connection;

        %DUTName DUT top level name
        %  String containing the name of the DUT top level
        DUTName;

        %DeviceTree Device tree file (only for Ethernet connection on Zynq)
        %  String containing the device tree file name. The default value
        %  of this property is an empty string.
        DeviceTree;

        %  Ethernet Interface is either PS Ethernet or USB Ethernet 
        %  Valid only for Ethernet connection on Zynq.
        %  The default value of this property is an empty string.
        EthernetType;

        %FPGABoard Name of the FPGA board
        %  String containing the FPGA board name. The default value
        %  of this property is an empty string.
        FPGABoard;

        %FPGAProgrammingFile Path of the Programming file for the FPGA
        %  String containing the path of the Programming file for the FPGA.
        %  The default value of this property is an empty string.
        FPGAProgrammingFile;

        FPGATool;

        %FPGAVendor Name of the FPGA chip vendor
        %  String containing the FPGA chip vendor name. The default value
        %  of this property is an empty string.
        FPGAVendor;

        %IPAddress Board IP address (only for Ethernet connection on Zynq)
        %  String containing the IP address for Zynq board.
        %  The default value of this property is '192.168.0.2'.
        IPAddress;

        %InputBitWidths Bit widths of the inputs
        %  Integer or vector of integer specifying the bit widths of
        %  the inputs. If only a scalar is provided all inputs have the
        %  same bit width, otherwise a vector of the same size as the
        %  number of input should be provided. The default value of
        %  this property is 0.
        InputBitWidths;

        %InputSignals Input port name in the HDL top level
        %  String or array of N string containing the input port name
        %  of each input in HDL. The default value of this property is an
        %  empty string.
        InputSignals;

        %OutputBitWidths Bit widths of the outputs
        %  Integer or vector of integer specifying the bit widths of
        %  the outputs. If only a scalar is provided all outputs have the
        %  same bit width, otherwise a vector of the same size as the
        %  number of output should be provided. The default value of
        %  this property is 0.
        OutputBitWidths;

        %OutputDataTypes Data type of the outputs
        %  String or array of N string specifying the data type of the 
        %  output ('logical', 'integer', 'fixedpoint', 'double', 'single').
        %  If only one string is provided all outputs have the same type,
        %  otherwise a array of string of the same size as the number of
        %  output should be provided.  The default value of this property
        %  is 'fixedpoint'.
        OutputDataTypes;

        %OutputDownsampling Downsampling factor and phase of the outputs
        %  Vector of 2 integers: The first integer specify the downsampling 
        %  factor and is positive; The second integer specify the phase and
        %  is null or positive and inferior to the downsampling factor. The
        %  default value of this property is [1,0].
        OutputDownsampling;

        %OutputFractionLengths Fraction lengths of the outputs
        %  Integer or vector of integer specifying the fraction length of
        %  the outputs. If only a scalar is provided all outputs have the
        %  same fraction length, otherwise a vector of the same size as the
        %  number of output should be provided. The default value of
        %  this property is 0.
        OutputFractionLengths;

        %OutputSignals Output port name in the HDL top level
        %  String or array of N string containing the output port name
        %  of each output in HDL. The default value of this property is an
        %  empty string.
        OutputSignals;

        %OutputSigned Sign of the outputs
        %  Boolean or vector of boolean specifying the sign of the outputs
        %  (true signed, false unsigned). If only a scalar is provided all
        %  outputs have the same sign, otherwise a vector of the same size
        %  as the number of output should be provided. The default value of
        %  this property is false.
        OutputSigned;

        %OverclockingFactor Overclocking factor of the hardware
        %  Positive integer specifying the overclocking factor for the
        %  hardware. The default value of this property is 1.
        OverclockingFactor;

        %Password Board password (only for Ethernet connection on Zynq)
        %  String containing the password for Zynq board.
        %  The default value of this property is 'root'.
        Password;

        %ScanChainPosition Position of the FPGA in the JTAG scan chain
        %  Positive integer specifying the Position of the FPGA in the 
        %  JTAG scan chain. The default value of this property is 1.
        ScanChainPosition;

        %SourceFrameSize Frame size of the source (only for HDL source block)
        %  Integer specifying the frame size of the source when the HDL is
        %  a source block (no input). The default value of this property is 1.
        SourceFrameSize;

        %Username Board username (only for Ethernet connection on Zynq)
        %  String containing the username for Zynq board.
        %  The default value of this property is 'root'.
        Username;

    end
end
