% Simulink Design Verifier 
% Version 24.1 (R2024a) 19-Nov-2023 
% 
%   sldvblockreplacement - Replace model blocks for analysis 
%   sldvcompat           - Check model for compatibility with analysis 
%   sldvextract          - Extract subsystem or subchart contents into new model for analysis 
%   sldvgencov           - Run analysis to obtain missing model coverage 
%   sldvmergeharness     - Merge test cases and initializations into one model 
%   sldvlogsignals       - Log simulation input port values 
%   sldvmakeharness      - Generate test harness model 
%   sldvharnessopts      - Generate default options for sldvmakeharness
%   sldvoptions          - Create design verification options object 
%   sldvreport           - Generate a report 
%   sldvrun              - Analyze model 
%   sldvruntest          - Simulate model using test cases
%   sldvsimdata          - Get simulation data in Dataset format
%   sldvruncgvtest       - Invoke Code Generation Verification (CGV) API and execute model
%   sldvruntestopts      - Generate simulation or execution options for sldvruntest or sldvruncgvtest
%   sldvtimer            - Identify, change, and display timer optimizations
%
% Deprecated functions
%   sldvlogdata          - Deprecated with sldvlogsignals
%   sldvharnessmerge     - Deprecated with sldvmergeharness
%
% Test and proof specification functions for Stateflow and MATLAB Function block
%   sldv.assume          - Specify a proof assumption
%   sldv.condition       - Specify a test condition
%   sldv.prove           - Specify a proof objective
%   sldv.test            - Specify a test objective

%   Copyright 2004-2023 The MathWorks, Inc. 
