function val = getEnableState(this, prop)
%GETENABLESTATE Get the enable state of the specified property widget.

%   Copyright 2009-2023 The MathWorks, Inc.
%     

val = false;
filtobj = this.filterObj;
archit = this.Architecture;

switch prop
    case 'CoefficientMemory'
        switch archit
            case {'Fully serial', 'Partly serial', 'Cascade serial'}
                if fdhdlcoderui.isfirfilter(filtobj)
                    if strcmpi(this.CoefficientSource, 'Processor Interface')
                        val = true;
                    end
                end
        end
%         setSerialArchSettings(this);        
    case 'CoefficientSource'
        if fdhdlcoderui.isfirfilter(filtobj) || fdhdlcoderui.isiirfilter(filtobj)      
            val = ~strcmpi(archit, 'Distributed arithmetic (DA)');
        end
        switch archit
            case {'Fully serial', 'Partly serial', 'Cascade serial'}
                if fdhdlcoderui.isfirfilter(filtobj)
                    if strcmpi(this.CoefficientSource, 'Processor Interface')
                        val = true;
                    end
                end
                if fdhdlcoderui.isiirfilter(filtobj)
                    val = false;
                end
        end
        
    case 'SerialPartition'
        val = strcmpi(archit, 'Partly serial') || strcmpi(archit, 'Cascade serial');
    case 'LUTPartition'
        val = strcmpi(archit, 'Distributed arithmetic (DA)');
    case 'DARadix'
        val = strcmpi(archit, 'Distributed arithmetic (DA)');
    case 'CoefMultipliers'
        if isa(filtobj, 'dsp.internal.mfilt.abstractcic') || ...
                isa(filtobj, 'dsp.internal.mfilt.holdinterp')
            val = false;
        else
            if (strcmpi(archit,  'Fully parallel'))
                val = true;
            end
        end        
    case 'FIRAdder'        
        if fdhdlcoderui.isfirfilter(filtobj) || ...
                fdhdlcoderui.ismultiratefir(filtobj) || ...
                fdhdlcoderui.isfarrow(filtobj) || ...
                (isa(filtobj, 'dsp.internal.mfilt.linearinterp') && ~isa(filtobj, 'dsp.internal.mfilt.holdinterp'))
            if strcmpi(archit, 'Fully parallel') || strcmpi(archit, 'Partly serial') || strcmpi(archit, 'Cascade serial')               
                val = true;
            elseif strcmpi(archit, 'Distributed arithmetic (DA)') 
                val = false;
                this.FIRAdderStyle = 'Tree';
            else
                val = false;
                this.FIRAdderStyle = 'Linear';              
            end
        elseif isa(filtobj, 'dsp.internal.mfilt.farrowsrc') || isa(filtobj,'mfilt.firsrc')                
            val = true;
        else
            val = false;
            this.FIRAdderStyle = 'Linear';
        end
        

        if val == true && this.AddPipelineRegisters == true
            val = false;
            this.FIRAdderStyle = 'Tree';
        end

        
    case 'AddPipelineRegisters'
        if fdhdlcoderui.isfirfilter(filtobj) || ...
                fdhdlcoderui.ismultiratefir(filtobj) || ...
                fdhdlcoderui.isfarrow(filtobj) || ...
                (isa(filtobj, 'dsp.internal.mfilt.linearinterp') && ~isa(filtobj, 'dsp.internal.mfilt.holdinterp'))                    
          switch archit
              case 'Fully parallel'
                  val = true;
              case 'Fully serial'
                  val = false;
                  this.AddPipelineRegisters = false;
              case 'Partly serial'
                  val = true;
              case 'Cascade serial'
                  val = false;
                  this.AddPipelineRegisters = false;
              case 'Distributed arithmetic (DA)'
                  if ~fdhdlcoderui.ismultiratefir(filtobj)
                      val = true;
                  else
                      val = false;
                      this.AddPipelineRegisters = false;
                  end              
          end
        else
            if isa(filtobj, 'dsp.internal.mfilt.farrowsrc') || isa(filtobj,'mfilt.firsrc')
                val = false;
                this.AddPipelineRegisters = false;
            else
                val = true;
            end
        end
    case 'Architecture'
        val = fdhdlcoderui.isfirfilter(filtobj) || fdhdlcoderui.ismultiratefir(filtobj) || ...
            fdhdlcoderui.issupportedsos(filtobj);               
end


% [EOF]
