function hB = plugin_board()
% Board definition

%   Copyright 2012-2014 The MathWorks, Inc.

% Construct board object
hB = hdlcoder.Board;

hB.BoardName    = 'Xilinx Zynq ZC706 evaluation kit';

% FPGA device information
hB.FPGAVendor   = 'Xilinx';
hB.FPGAFamily   = 'Zynq';
hB.FPGADevice   = 'xc7z045';
hB.FPGAPackage  = 'ffg900';
hB.FPGASpeed    = '-2';

% Tool information
hB.SupportedTool = {'Xilinx Vivado', 'Xilinx ISE'};

% FPGA JTAG chain position
hB.JTAGChainPosition = 2;

%% Add interfaces
% Standard "External Port" interface
hB.addExternalPortInterface( ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});

% Custom board external I/O interface
hB.addExternalIOInterface( ...
    'InterfaceID',    'LEDs General Purpose', ...
    'InterfaceType',  'OUT', ...
    'PortName',       'GPLEDs', ...
    'PortWidth',      4, ...
    'FPGAPin',        {'A17', 'W21', 'G2', 'Y21'}, ...
    'IOPadConstraint', {{'IOSTANDARD = LVCMOS15'}, {'IOSTANDARD = LVCMOS25'}, ...
                       {'IOSTANDARD = LVCMOS15'}, {'IOSTANDARD = LVCMOS25'}});

hB.addExternalIOInterface( ...
    'InterfaceID',    'Push Buttons', ...
    'InterfaceType',  'IN', ...
    'PortName',       'PushButtons', ...
    'PortWidth',      3, ...
    'FPGAPin',        {'AK25', 'K15', 'R27'}, ...
    'IOPadConstraint', {{'IOSTANDARD = LVCMOS25'}, {'IOSTANDARD = LVCMOS15'}, ...
                       {'IOSTANDARD = LVCMOS25'}});

hB.addExternalIOInterface( ...
    'InterfaceID',    'DIP Switches', ...
    'InterfaceType',  'IN', ...
    'PortName',       'GPDIP', ...
    'PortWidth',      4, ...
    'FPGAPin',        {'AB17', 'AC16', 'AC17', 'AJ13'}, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});

%% Add custom device tree
thirdPartyInstallDir = matlab.internal.get3pInstallLocation('xilinxlinuxbinaries.instrset');
dtsIncludeDir = fullfile(thirdPartyInstallDir, 'dts_repository', 'kernel_dtsi');
hB.addDeviceTreeIncludeDirectory(dtsIncludeDir);
hB.addDeviceTree('zynq-zc706.dtsi');

% LocalWords:  Zynq ZC xc ffg IOSTANDARD LVCMOS GPLE GPDIP
