function hB = plugin_board()
% Board definition

%   Copyright 2012-2014 The MathWorks, Inc.

% Construct board object
hB = hdlcoder.Board;

hB.BoardName    = 'Xilinx Zynq ZC702 evaluation kit';

% FPGA device information
hB.FPGAVendor   = 'Xilinx';
hB.FPGAFamily   = 'Zynq';
hB.FPGADevice   = 'xc7z020';
hB.FPGAPackage  = 'clg484';
hB.FPGASpeed    = '-1';

% Tool information
hB.SupportedTool = {'Xilinx Vivado', 'Xilinx ISE'};

% FPGA JTAG chain position
hB.JTAGChainPosition = 2;

%% Add interfaces
% Standard "External Port" interface
hB.addExternalPortInterface( ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});

% Custom board external I/O interface
hB.addExternalIOInterface( ...
    'InterfaceID',    'LEDs General Purpose', ...
    'InterfaceType',  'OUT', ...
    'PortName',       'GPLEDs', ...
    'PortWidth',      8, ...
    'FPGAPin',        {'E15', 'D15', 'W17', 'W5', 'V7', 'W10', 'P18', 'P17'}, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});

hB.addExternalIOInterface( ...
    'InterfaceID',    'Push Buttons', ...
    'InterfaceType',  'IN', ...
    'PortName',       'PushButtons', ...
    'PortWidth',      2, ...
    'FPGAPin',        {'G19', 'F19'}, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});

hB.addExternalIOInterface( ...
    'InterfaceID',    'DIP Switches', ...
    'InterfaceType',  'IN', ...
    'PortName',       'GPDIP', ...
    'PortWidth',      2, ...
    'FPGAPin',        {'W7', 'W6'}, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});

% LocalWords:  Zynq ZC xc IOSTANDARD LVCMOS GPLE GPDIP
