function hB = plugin_board()
% Board definition

%   Copyright 2012-2016 The MathWorks, Inc.

% Construct board object
hB = hdlcoder.Board;

hB.BoardName    = 'Xilinx Virtex-7 VC707 development board';

% FPGA device information
hB.FPGAVendor   = 'Xilinx';
hB.FPGAFamily   = 'Virtex7';
hB.FPGADevice   = 'xc7vx485t';
hB.FPGAPackage  = 'ffg1761';
hB.FPGASpeed    = '-2';

% Tool information
hB.SupportedTool = {'Xilinx Vivado'};

% FPGA JTAG chain position
hB.JTAGChainPosition = 1;

% MCS File Name is dutName_postFix
hB.TopLevelNamePostfix = 'topvc707';

% Custom board external I/O interface
hB.addExternalIOInterface( ...
    'InterfaceID',    'LEDs General Purpose', ...
    'InterfaceType',  'OUT', ...
    'PortName',       'GPLEDs', ...
    'PortWidth',      8, ...
    'FPGAPin',        {'AM39', 'AN39', 'AR37', 'AT37', 'AR35', 'AP41', 'AP42', 'AU39'}, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS18'});

hB.addExternalIOInterface( ...
    'InterfaceID',    'Push Buttons', ...
    'InterfaceType',  'IN', ...
    'PortName',       'PBs', ...
    'PortWidth',      8, ...
    'FPGAPin',        {'AV30', 'AY33','BA31','BA32', 'AW30', 'AY30', 'BA30', 'BB31'}, ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS18'});


hB.addEthernetMACInterface( ...
        'InterfaceType',  'SGMII',...
        'MACAddress','0x000A3502218A',...
        'IPAddress','192.168.0.2',...
        'NumChannels', 2,...
        'PortAddresses',[50101,50102],...
        'EthernetMACConstraintFile','../vc707_ethernet_sgmii.xdc');

% LocalWords: Virtex vc707