Index of /nchou/s/matlab-2024a/amd64_rhel7/old/toolbox/shared/hdlshared

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[DIR]+hdlcoderprops/2024-08-27 15:02 -  
[DIR]+hdlconnectivity/2024-08-27 15:02 -  
[DIR]+hdlshared/2024-08-27 15:02 -  
[DIR]@fdhdlcoderui/2024-08-27 15:02 -  
[DIR]@hdl/2024-08-27 15:02 -  
[DIR]@hdlfilter/2024-08-27 15:02 -  
[DIR]@hdlshared/2024-08-27 15:02 -  
[DIR]@multicycleconstraints/2024-08-27 15:02 -  
[DIR]@propset/2024-08-27 15:02 -  
[DIR]@reportdlg/2024-08-27 15:02 -  
[   ]Contents.m2011-05-10 20:38 162  
[TXT]PersistentHDLPropSet.p2023-11-20 08:55 163  
[TXT]PersistentHDLResource.p2023-11-20 08:55 163  
[TXT]WebBrowserHandleCollector.p2023-11-20 08:55 382  
[TXT]attachhdlcconfig.p2023-11-20 08:55 544  
[TXT]checkSDRProductRequirements.p2023-11-20 08:55 189  
[TXT]checksymmetry.p2023-11-20 08:55 226  
[TXT]conv2hdlsharedtypes.p2023-11-20 08:55 204  
[TXT]detachhdlcconfig.p2023-11-20 08:55 394  
[TXT]dumphdlentitysignals.p2023-11-20 08:55 611  
[TXT]getHDLWAPluginManager.p2023-11-20 08:55 263  
[TXT]gethdlcc.p2023-11-20 08:55 181  
[TXT]gethdlcconfigset.p2023-11-20 08:55 345  
[TXT]getpirsignaltype.p2023-11-20 08:55 264  
[TXT]getslsignaltype.p2023-11-20 08:55 123  
[TXT]getslsignaltypefromval.p2023-11-20 08:55 130  
[TXT]hasQuantizationError.p2023-11-20 08:55 576  
[TXT]hdlCellArray2Str.p2023-11-20 08:55 286  
[TXT]hdlComponent.p2023-11-20 08:55 1.2K 
[TXT]hdlDispWithTimeStamp.p2023-11-20 08:55 279  
[TXT]hdlGetCodegendir.p2023-11-20 08:55 283  
[TXT]hdlUniquifyTypeDefinitions.p2023-11-20 08:55 415  
[TXT]hdladd.p2023-11-20 08:55 754  
[TXT]hdladdclockenablesignal.p2023-11-20 08:55 162  
[TXT]hdladdclocksignal.p2023-11-20 08:55 215  
[TXT]hdladdinportsignal.p2023-11-20 08:55 254  
[TXT]hdladdoutportsignal.p2023-11-20 08:55 257  
[TXT]hdladdresetsignal.p2023-11-20 08:55 213  
[TXT]hdladdsub.p2023-11-20 08:55 408  
[TXT]hdladdtoentitylist.p2023-11-20 08:55 417  
[TXT]hdlassignforoutput.p2023-11-20 08:55 329  
[TXT]hdlbitop.p2023-11-20 08:55 1.4K 
[TXT]hdlblockdatatype.p2023-11-20 08:55 217  
[TXT]hdlcascadedecompose.p2023-11-20 08:55 1.0K 
[TXT]hdlclockenablesignals.p2023-11-20 08:55 166  
[TXT]hdlclocksignals.p2023-11-20 08:55 161  
[TXT]hdlcodeconcat.p2023-11-20 08:55 176  
[TXT]hdlcodegenmode.p2023-11-20 08:55 253  
[TXT]hdlcodegenmsgs.p2023-11-20 08:55 880  
[TXT]hdlcodeinit.p2023-11-20 08:55 267  
[TXT]hdlcoderconfigsetup.p2023-11-20 08:55 143  
[TXT]hdlcoeffmultiply.p2023-11-20 08:55 2.5K 
[TXT]hdlcompareval.p2023-11-20 08:55 1.5K 
[TXT]hdlconstantvalue.p2023-11-20 08:55 242  
[TXT]hdlcounter.p2023-11-20 08:55 521  
[TXT]hdlcreatescalarsignalsfromvectorsignal.p2023-11-20 08:55 271  
[TXT]hdldatatypeassignment.p2023-11-20 08:55 2.3K 
[TXT]hdldefarchheader.p2023-11-20 08:55 230  
[TXT]hdldefaultparameters.p2023-11-20 08:55 207  
[TXT]hdldeserializer.p2023-11-20 08:55 461  
[TXT]hdldisp.p2023-11-20 08:55 281  
[TXT]hdlentityfilenames.p2023-11-20 08:55 419  
[TXT]hdlentitynameexists.p2023-11-20 08:55 236  
[TXT]hdlentitynames.p2023-11-20 08:55 278  
[TXT]hdlentityportnames.p2023-11-20 08:55 168  
[TXT]hdlentityports.p2023-11-20 08:55 1.1K 
[TXT]hdlentitysignalsinit.p2023-11-20 08:55 190  
[TXT]hdlentitytop.p2023-11-20 08:55 204  
[TXT]hdlentitytopfilename.p2023-11-20 08:55 286  
[TXT]hdleqop.p2023-11-20 08:55 263  
[TXT]hdlexpandconnectiontovectorsignal.p2023-11-20 08:55 204  
[TXT]hdlexpandvectorsignal.p2023-11-20 08:55 1.0K 
[TXT]hdlfilteradd.p2023-11-20 08:55 412  
[TXT]hdlfilterlatency.p2023-11-20 08:55 628  
[TXT]hdlfiltermultiply.p2023-11-20 08:55 156  
[TXT]hdlfiltermultiplycsd.p2023-11-20 08:55 158  
[TXT]hdlfiltermultiplyfactoredcsd.p2023-11-20 08:55 162  
[TXT]hdlfiltersub.p2023-11-20 08:55 145  
[TXT]hdlfilterunaryminus.p2023-11-20 08:55 179  
[TXT]hdlfinalassignment.p2023-11-20 08:55 877  
[TXT]hdlfirinterpdamac.p2023-11-20 08:55 3.0K 
[TXT]hdlformatcomment.p2023-11-20 08:55 290  
[TXT]hdlgetallfromsltype.p2023-11-20 08:55 477  
[TXT]hdlgetblocklibpath.p2023-11-20 08:55 1.0K 
[TXT]hdlgetclockbundle.p2023-11-20 08:55 328  
[TXT]hdlgetcurrentclock.p2023-11-20 08:55 174  
[TXT]hdlgetcurrentclockenable.p2023-11-20 08:55 181  
[TXT]hdlgetcurrentreset.p2023-11-20 08:55 173  
[TXT]hdlgetdeviceinfo.p2023-11-20 08:55 172  
[TXT]hdlgetedascript.p2023-11-20 08:55 1.7K 
[TXT]hdlgetfilelink.p2023-11-20 08:55 275  
[TXT]hdlgetlintscript.p2023-11-20 08:55 1.5K 
[TXT]hdlgetmatlabsystemmap.p2023-11-20 08:55 277  
[TXT]hdlgetparameter.p2023-11-20 08:55 247  
[TXT]hdlgetpathtoquartus.p2023-11-20 08:55 431  
[TXT]hdlgetpathtoquartuspro.p2023-11-20 08:55 429  
[TXT]hdlgetporttypesfromsizes.p2023-11-20 08:55 382  
[TXT]hdlgetrunlink.p2023-11-20 08:55 233  
[TXT]hdlgetsignaltable.p2023-11-20 08:55 189  
[TXT]hdlgetsizesfromtype.p2023-11-20 08:55 118  
[TXT]hdlgetsltypefromsizes.p2023-11-20 08:55 216  
[TXT]hdlgettypesfromsizes.p2023-11-20 08:55 392  
[TXT]hdlinportsignals.p2023-11-20 08:55 203  
[TXT]hdlintdelay.p2023-11-20 08:55 668  
[TXT]hdlisclockenablesignal.p2023-11-20 08:55 212  
[TXT]hdlisclocksignal.p2023-11-20 08:55 208  
[TXT]hdlisinoutportsignal.p2023-11-20 08:55 179  
[TXT]hdlisinportsignal.p2023-11-20 08:55 153  
[TXT]hdlisoutportsignal.p2023-11-20 08:55 153  
[TXT]hdlispowerof2.p2023-11-20 08:55 303  
[TXT]hdlisresetsignal.p2023-11-20 08:55 208  
[TXT]hdlissignalscalar.p2023-11-20 08:55 111  
[TXT]hdlissignaltype.p2023-11-20 08:55 500  
[TXT]hdlissignalvector.p2023-11-20 08:55 176  
[TXT]hdllastinputsignal.p2023-11-20 08:55 216  
[TXT]hdllastoutputsignal.p2023-11-20 08:55 260  
[TXT]hdllastsignal.p2023-11-20 08:55 204  
[TXT]hdllegalizefieldname.p2023-11-20 08:55 228  
[TXT]hdllegalname.p2023-11-20 08:55 283  
[TXT]hdllegalnamersvd.p2023-11-20 08:55 228  
[TXT]hdllog.p2023-11-20 08:55 393  
[TXT]hdllogop.p2023-11-20 08:55 1.4K 
[TXT]hdllookuptable.p2023-11-20 08:55 1.4K 
[TXT]hdlmakecodegendir.p2023-11-20 08:55 250  
[TXT]hdlmulticoeffmultiply.p2023-11-20 08:55 1.4K 
[TXT]hdlmultiply.p2023-11-20 08:55 321  
[TXT]hdlmultiplycomplexcomplex.p2023-11-20 08:55 511  
[TXT]hdlmultiplycomplexreal.p2023-11-20 08:55 238  
[TXT]hdlmultiplycsd.p2023-11-20 08:55 1.6K 
[TXT]hdlmultiplyfactoredcsd.p2023-11-20 08:55 1.3K 
[TXT]hdlmultiplypowerof2.p2023-11-20 08:55 1.0K 
[TXT]hdlmultiplyrealreal.p2023-11-20 08:55 382  
[TXT]hdlmux.p2023-11-20 08:55 2.9K 
[TXT]hdlnewsignal.p2023-11-20 08:55 516  
[TXT]hdlonebitaddsub.p2023-11-20 08:55 2.4K 
[TXT]hdloutportsignals.p2023-11-20 08:55 204  
[TXT]hdlpngen.p2023-11-20 08:55 2.3K 
[TXT]hdlportdatatype.p2023-11-20 08:55 215  
[TXT]hdlprinttargetcodegenheaders.p2023-11-20 08:55 1.9K 
[TXT]hdlregsignal.p2023-11-20 08:55 327  
[TXT]hdlrelop.p2023-11-20 08:55 1.6K 
[TXT]hdlresetsignals.p2023-11-20 08:55 160  
[TXT]hdlringcounter.p2023-11-20 08:55 240  
[TXT]hdlsafeinput.p2023-11-20 08:55 420  
[TXT]hdlsaturate.p2023-11-20 08:55 228  
[TXT]hdlsequentialcontext.p2023-11-20 08:55 211  
[TXT]hdlserializer.p2023-11-20 08:55 448  
[TXT]hdlsetcurrentclock.p2023-11-20 08:55 253  
[TXT]hdlsetcurrentclockenable.p2023-11-20 08:55 335  
[TXT]hdlsetcurrentreset.p2023-11-20 08:55 251  
[TXT]hdlsetorextractbits.p2023-11-20 08:55 397  
[TXT]hdlsetpackagename.p2023-11-20 08:55 177  
[TXT]hdlsetparameter.p2023-11-20 08:55 191  
[TXT]hdlsetsignaltable.p2023-11-20 08:55 206  
[TXT]hdlsetuphlstoolpath.p2023-11-20 08:55 107  
[   ]hdlsetuptoolpath.m2022-08-29 14:15 2.1K 
[DIR]hdlshared_gui/2024-08-27 15:02 -  
[DIR]hdlshared_soc/2024-08-27 15:02 -  
[TXT]hdlshiftregister.p2023-11-20 08:55 238  
[TXT]hdlsignalassignment.p2023-11-20 08:55 2.1K 
[TXT]hdlsignalcomplex.p2023-11-20 08:55 295  
[TXT]hdlsignalfindname.p2023-11-20 08:55 276  
[TXT]hdlsignalforward.p2023-11-20 08:55 256  
[TXT]hdlsignalhandle.p2023-11-20 08:55 243  
[TXT]hdlsignalimag.p2023-11-20 08:55 459  
[TXT]hdlsignalisboolean.p2023-11-20 08:55 234  
[TXT]hdlsignaliscomplex.p2023-11-20 08:55 281  
[TXT]hdlsignalisdouble.p2023-11-20 08:55 316  
[TXT]hdlsignalname.p2023-11-20 08:55 359  
[TXT]hdlsignalnext.p2023-11-20 08:55 201  
[TXT]hdlsignalrate.p2023-11-20 08:55 169  
[TXT]hdlsignalsetvtype.p2023-11-20 08:55 205  
[TXT]hdlsignalsizes.p2023-11-20 08:55 297  
[TXT]hdlsignalsltype.p2023-11-20 08:55 190  
[TXT]hdlsignaltypeconvert.p2023-11-20 08:55 441  
[TXT]hdlsignalvector.p2023-11-20 08:55 440  
[TXT]hdlsignalvtype.p2023-11-20 08:55 221  
[TXT]hdlsignedtounsigned_dtc.p2023-11-20 08:55 519  
[TXT]hdlsliceconcat.p2023-11-20 08:55 659  
[TXT]hdlsub.p2023-11-20 08:55 1.1K 
[TXT]hdlsubsub.p2023-11-20 08:55 600  
[TXT]hdlsumofelements.p2023-11-20 08:55 3.3K 
[TXT]hdlsynthtoolenum.p2023-11-20 08:55 325  
[TXT]hdltapdelay.p2023-11-20 08:55 635  
[TXT]hdltypeconvert.p2023-11-20 08:55 232  
[TXT]hdlunaryminus.p2023-11-20 08:55 1.4K 
[TXT]hdluniqueentityname.p2023-11-20 08:55 301  
[TXT]hdluniquename.p2023-11-20 08:55 359  
[TXT]hdluniqueprocessname.p2023-11-20 08:55 264  
[TXT]hdlunitdelay.p2023-11-20 08:55 739  
[TXT]hdlvalidatestruct.p2023-11-20 08:55 223  
[TXT]hdlvectorblockdatatype.p2023-11-20 08:55 234  
[TXT]hdlvectorconstantassign.p2023-11-20 08:55 781  
[TXT]hdlvectorconstantspecialassign.p2023-11-20 08:55 903  
[TXT]hdlverilogmode.p2023-11-20 08:55 414  
[TXT]hdlverilogtimescale.p2023-11-20 08:55 148  
[TXT]hdlvhdlmode.p2023-11-20 08:55 405  
[TXT]hdlwordsize.p2023-11-20 08:55 551  
[TXT]hdlwritescripts.p2023-11-20 08:55 1.3K 
[TXT]isAdderFullPrecision.p2023-11-20 08:55 276  
[TXT]isCommUSRPInstalled.p2023-11-20 08:55 125  
[TXT]isNativeFloatingPointMode.p2023-11-20 08:55 212  
[TXT]isTargetFloatingPointMode.p2023-11-20 08:55 146  
[TXT]isVendorFloatingPointMode.p2023-11-20 08:55 192  
[TXT]makehdlconstantdecl.p2023-11-20 08:55 377  
[TXT]makehdlsignaldecl.p2023-11-20 08:55 967  
[TXT]makeverilogconstantdecl.p2023-11-20 08:55 460  
[TXT]makevhdlconstantdecl.p2023-11-20 08:55 269  
[TXT]pir.p2023-11-20 08:55 361  
[TXT]pirNetworkForFilterComp.p2023-11-20 08:55 230  
[TXT]pir_arr_factory_tc.p2023-11-20 08:55 127  
[TXT]pir_rec_factory_tc.p2023-11-20 08:55 128  
[   ]pir_udd.mexa642024-02-23 01:08 6.0K 
[TXT]pirgetvtype.p2023-11-20 08:55 419  
[TXT]pirhdlnewsignal.p2023-11-20 08:55 657  
[DIR]private/2024-08-27 15:02 -  
[TXT]resourceLog.p2023-11-20 08:55 298  
[TXT]uniquifyClockParams.p2023-11-20 08:55 574  
[TXT]verilogaddrealreal.p2023-11-20 08:55 1.3K 
[TXT]verilogaddrealrealbittrue.p2023-11-20 08:55 1.1K 
[TXT]verilogblockdatatype.p2023-11-20 08:55 197  
[TXT]verilogconstantvalue.p2023-11-20 08:55 1.1K 
[TXT]verilogcounter.p2023-11-20 08:55 2.1K 
[TXT]veriloggetvtype.p2023-11-20 08:55 365  
[TXT]verilogintdelay.p2023-11-20 08:55 2.0K 
[TXT]veriloglegalname.p2023-11-20 08:55 97  
[TXT]veriloglegalnamersvd.p2023-11-20 08:55 1.2K 
[TXT]verilogmultiplyrealreal.p2023-11-20 08:55 1.0K 
[TXT]verilogportdatatype.p2023-11-20 08:55 280  
[TXT]verilogringcounter.p2023-11-20 08:55 1.8K 
[TXT]verilogsaturate.p2023-11-20 08:55 1.4K 
[TXT]verilogsetorextractbits.p2023-11-20 08:55 784  
[TXT]verilogshiftregister.p2023-11-20 08:55 2.0K 
[TXT]verilogsubcomplexcomplex.p2023-11-20 08:55 153  
[TXT]verilogsubcomplexreal.p2023-11-20 08:55 154  
[TXT]verilogsubrealreal.p2023-11-20 08:55 1.3K 
[TXT]verilogsubrealrealbittrue.p2023-11-20 08:55 1.1K 
[TXT]verilogsubsubrealreal.p2023-11-20 08:55 928  
[TXT]verilogsubsubrealrealbittrue.p2023-11-20 08:55 925  
[TXT]verilogtapdelay.p2023-11-20 08:55 1.4K 
[TXT]verilogtypeconvert.p2023-11-20 08:55 2.4K 
[TXT]verilogunitdelay.p2023-11-20 08:55 1.5K 
[TXT]verilogvectorblockdatatype.p2023-11-20 08:55 186  
[TXT]verilogvectorportdatatype.p2023-11-20 08:55 261  
[TXT]vhdladdcomplexcomplex.p2023-11-20 08:55 149  
[TXT]vhdladdcomplexreal.p2023-11-20 08:55 150  
[TXT]vhdladdrealreal.p2023-11-20 08:55 1.1K 
[TXT]vhdladdrealrealbittrue.p2023-11-20 08:55 1.1K 
[TXT]vhdlblockdatatype.p2023-11-20 08:55 201  
[TXT]vhdlconstantvalue.p2023-11-20 08:55 1.5K 
[TXT]vhdlcounter.p2023-11-20 08:55 2.2K 
[TXT]vhdlcreateaggregate.p2023-11-20 08:55 911  
[TXT]vhdlentityinit.p2023-11-20 08:55 229  
[TXT]vhdlgetvtype.p2023-11-20 08:55 406  
[TXT]vhdlintdelay.p2023-11-20 08:55 2.3K 
[TXT]vhdlisstdlogicvector.p2023-11-20 08:55 381  
[TXT]vhdllegalname.p2023-11-20 08:55 271  
[TXT]vhdllegalnamersvd.p2023-11-20 08:55 866  
[TXT]vhdlmultiplyrealreal.p2023-11-20 08:55 1.0K 
[TXT]vhdlnzeros.p2023-11-20 08:55 220  
[TXT]vhdlpackageaddtypedef.p2023-11-20 08:55 188  
[TXT]vhdlpackageinit.p2023-11-20 08:55 291  
[TXT]vhdlportdatatype.p2023-11-20 08:55 254  
[TXT]vhdlringcounter.p2023-11-20 08:55 1.7K 
[TXT]vhdlsaturate.p2023-11-20 08:55 1.4K 
[TXT]vhdlsetorextractbits.p2023-11-20 08:55 893  
[TXT]vhdlshiftregister.p2023-11-20 08:55 2.0K 
[TXT]vhdlsubrealreal.p2023-11-20 08:55 1.1K 
[TXT]vhdlsubrealrealbittrue.p2023-11-20 08:55 1.1K 
[TXT]vhdlsubsubrealreal.p2023-11-20 08:55 807  
[TXT]vhdlsubsubrealrealbittrue.p2023-11-20 08:55 1.0K 
[TXT]vhdltapdelay.p2023-11-20 08:55 1.5K 
[TXT]vhdltypeconvert.p2023-11-20 08:55 2.8K 
[TXT]vhdlunitdelay.p2023-11-20 08:55 1.5K 
[TXT]vhdlvectorblockdatatype.p2023-11-20 08:55 568  
[TXT]vhdlvectorportdatatype.p2023-11-20 08:55 447