function filProgramFPGA(fpgaTool, programFile, varargin)
% filProgramFPGA programs FPGA for FPGA-in-the-Loop
%
%   filProgramFPGA('Xilinx ISE', PROGRAMFILE,CHAINPOSITION)
%   programs Xilinx FPGA at JTAG chain position CHAINPOSITION using the
%   programming file PROGRAMFILE. 
%
%   filProgramFPGA('Xilinx Vivado', PROGRAMFILE,CHAINPOSITION)
%   programs Xilinx FPGA at JTAG chain position CHAINPOSITION using the
%   programming file PROGRAMFILE and Xilinx Vivado tool. 
%
%   filProgramFPGA('Altera Quartus II',PROGRAMFILE,CHAINPOSITION) 
%   programs Altera FPGA at JTAG chain position CHAINPOSITION using the
%   specified FPGA programming file PROGRAMFILE.
%
%   filProgramFPGA('Microchip',PROGRAMFILE) 
%   programs Microchip FPGA using the specified FPGA programming file
%   PROGRAMFILE.
%

% Copyright 2010-2017 The MathWorks, Inc.

narginchk(2,5);

assert(ischar(programFile) || isstring(programFile),message('EDALink:loadFPGABitstream:InvalidBitstreamArgumentType'));

switch(fpgaTool)
    case {'Intel','Altera','Altera Quartus II','Altera Quartus','Altera QUARTUS II','Intel Quartus Pro'}
        programAlteraFPGA(programFile,varargin{:});
    case {'Xilinx','Xilinx ISE'}
        programXilinxFPGA(programFile,varargin{:});
    case {'Xilinx Vivado'}
        programXilinxFPGAUsingVivado(programFile,varargin{:});
    case {'Microchip','Microchip Libero SoC'}
        if exist('programMicrosemiFPGA','file')
            programMicrosemiFPGA(programFile,varargin{:});
        else
            error(message('EDALink:loadFPGABitstream:NoMicrosemiSPKG'));
        end
    otherwise
        error(message('EDALink:loadFPGABitstream:InvalidFpgaVendor',fpgaTool));
end
