% hdlcoder.ReferenceDesign
%
% Create reference design definition object for HDL Workflow Advisor
%
% Syntax
%
% hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado')
%
% Description
%
% hdlcoder.ReferenceDesign creates a reference design definition object
% for the synthesis tool specified in "SynthesisTool" parameter.
% hRD is returned as a reference design definition object.
%
% Example:
% % Construct reference design object
% hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado');
%
% hRD.ReferenceDesignName = 'My custom system';
% hRD.BoardName = 'My custom board';
%
% % Tool information
% hRD.SupportedToolVersion = {'2014.2'};
%
% %% Add custom design files
% % add custom Vivado design
% hRD.addCustomVivadoDesign( ...
% 'CustomBlockDesignTcl', 'system_top.tcl', ...
% 'BlockDesignName', 'system_top', ...
% 'VivadoBoardName', 'xilinx.com:zynq:zc702:1.0');
%
% %% Add interfaces
% % add clock interface
% hRD.addClockInterface( ...
% 'ClockConnection', 'clk_wiz_0/clk_out1', ...
% 'ResetConnection', 'proc_sys_reset_0/peripheral_aresetn');
%
% % add AXI4 and AXI4-Lite slave interfaces
% hRD.addAXI4SlaveInterface( ...
% 'InterfaceConnection', 'axi_interconnect_0/M00_AXI', ...
% 'BaseAddress', '0x40010000', ...
% 'MasterAddressSpace', 'processing_system7_0/Data');
%
% See also hdlcoder.Board
%

% Copyright 2014 The MathWorks, Inc.

function hRD = ReferenceDesign(varargin)

hRD = hdlturnkey.plugin.createReferenceDesign(varargin{:});

end

% LocalWords: Enclustra ZX xdc vlnv zynq zc AXI axi periph FCLK aresetn IPCORE
% LocalWords: EDK MHS EDKMHS mhs Prj qsys vivado altera wiz