classdef (StrictDefaults)template_src_fil <  hdlverifier.FILSimulation
%template_src_fil is a filWizard generated class used for FPGA-In-the-Loop
%   simulation with the REPLACE_WITH_DUTNAME DUT.
%   template_src_fil connects MATLAB with a FPGA and cosimulate with it by 
%   writing inputs in the FPGA and reading outputs from the FPGA.
%
%   MYFIL = template_src_fil
%
%   Step method syntax:
%
%   [out1, out2, ...] = step(MYFIL) connect to the FPGA, read out1, out2, ... 
%   from the FPGA 
%
%   template_src_fil methods:
%
%   step        - See above description for use of this method
%   release     - Allow property value and input characteristics changes, and
%                 release connection to FPGA board
%   clone       - Create template_src_fil object with same property values
%   isLocked    - Locked status (logical)
%   programFPGA - Load the programming file in the FPGA
%
%   template_src_fil properties:
%
%   DUTName                  - DUT top level name
%   OutputSignals            - Output paths in the HDL code
%   OutputBitWidths          - Width in bit of the outputs
%   OutputDataTypes          - Data type of the outputs
%   OutputSigned             - Sign of the outputs
%   OutputFractionLengths    - Fraction lengths of the outputs
%   OutputDownsampling       - Downsampling factor and phase of the outputs
%   OverclockingFactor       - Overclocking factor of the hardware
%   SourceFrameSize          - Frame size of the source (only for HDL source block)
%   Connection               - Parameters for the connection with the board
%   FPGAVendor               - Name of the FPGA chip vendor
%   FPGABoard                - Name of the FPGA board
%   FPGAProgrammingFile      - Path of the Programming file for the FPGA
%   ScanChainPosition        - Position of the FPGA in the JTAG scan chain
%
%   File Name: REPLACE_WITH_FILENAME
%   Created: REPLACE_WITH_DATESTR
% 
%   Generated by FIL Wizard

%#codegen

    properties (Nontunable)
        DUTName = REPLACE_WITH_DUTNAME;
    end
    
    methods
        function obj = template_src_fil
            
            %THE FOLLOWING PROTECTED PROPERTIES ARE SPECIFIC TO THE HW DUT
            %AND MUST NOT BE EDITED (RERUN THE FIL WIZARD TO CHANGE THEM)
            obj.OutputSignals = REPLACE_WITH_OUTPUTSIGNALS;
            obj.OutputBitWidths = REPLACE_WITH_OUTPUTBITWIDTHS;
            obj.Connection = REPLACE_WITH_CONNECTION; 
            obj.FPGAVendor = REPLACE_WITH_FPGAVENDOR;
            obj.FPGABoard = REPLACE_WITH_FPGABOARD;
            obj.ScanChainPosition = REPLACE_WITH_SCANCHAINPOSITION;
            REPLACE_WITH_DEVICETREE
            REPLACE_WITH_ETHERNETTYPE
            %THE FOLLOWING PUBLIC PROPERTIES ARE RELATED TO THE SIMULATION
            %AND CAN BE EDITED WITHOUT RERUNING THE FIL WIZARD
            obj.OutputSigned = REPLACE_WITH_OUTPUTSIGNED;
            obj.OutputDataTypes = REPLACE_WITH_OUTPUTDATATYPES;
            obj.OutputFractionLengths = REPLACE_WITH_OUTPUTFRACTIONLENGTHS;
            obj.OutputDownsampling = REPLACE_WITH_OUTPUTDOWNSAMPLING;
            obj.OverclockingFactor = REPLACE_WITH_OVERCLOCKINGFACTOR;
            obj.SourceFrameSize = REPLACE_WITH_SOURCEFRAMESIZE;
            obj.FPGAProgrammingFile = REPLACE_WITH_FPGAPROGRAMMINGFILE; 
            REPLACE_WITH_IPINFO
        end
    end
end




