% hdlcoder.Board
% 
% Create board definition object for HDL Workflow Advisor
%
% Syntax
%
%     hB = hdlcoder.Board
% 
% Description
% 
% hdlcoder.Board creates a board definition object for 
% IP Core Generation workflow in HDL Workflow Advisor.
% hB is returned as a board definition object.
% 
%   Example:
%      % Construct board object
%      hB = hdlcoder.Board;
%      
%      hB.BoardName    = 'My custom board';
%      
%      % FPGA device information
%      hB.FPGAVendor   = 'Xilinx';
%      hB.FPGAFamily   = 'Zynq';
%      hB.FPGADevice   = 'xc7z020';
%      hB.FPGAPackage  = 'clg484';
%      hB.FPGASpeed    = '-1';
% 
%      % Tool information
%      hB.SupportedTool = {'Xilinx Vivado', 'Xilinx ISE'};
% 
%      % FPGA JTAG chain position
%      hB.JTAGChainPosition = 2;
% 
%      %% Add interfaces
%      % Standard "External Port" interface
%      hB.addExternalPortInterface( ...
%          'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});
% 
%      % Custom board external I/O interface
%      hB.addExternalIOInterface( ...
%          'InterfaceID',    'LEDs General Purpose', ...
%          'InterfaceType',  'OUT', ...
%          'PortName',       'GPLEDs', ...
%          'PortWidth',      8, ...
%          'FPGAPin',        {'E15', 'D15', 'W17', 'W5', 'V7', 'W10', 'P18', 'P17'}, ...
%          'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});
% 
%      hB.addExternalIOInterface( ...
%          'InterfaceID',    'Push Buttons', ...
%          'InterfaceType',  'IN', ...
%          'PortName',       'PushButtons', ...
%          'PortWidth',      2, ...
%          'FPGAPin',        {'G19', 'F19'}, ...
%          'IOPadConstraint', {'IOSTANDARD = LVCMOS25'});
%
% See also hdlcoder.ReferenceDesign
%

%   Copyright 2014 The MathWorks, Inc.

function hBoard = Board(varargin)

hBoard = hdlturnkey.plugin.createBoard(varargin{:});

end

% LocalWords:  Enclustra ZX Zynq xc IOSTANDARD LVCMOS GPLE
