%% Defining and Extending Existing Tests Cases 
%
% This example shows how Simulink(R) Design Verifier(TM) can extend test 
% cases with additional time steps to efficiently generate complete test 
% suites.
%
% The example starts with a model containing time-delay 
% characteristics that make test generation challenging.  By creating a 
% default test harness model and manually authoring one test, the critical 
% obstacle to efficient test generation is removed.  Simulink Design 
% Verifier takes as input the logged values from the harness model and 
% efficiently extends this test to create a complete test suite.

% Copyright 2009-2021 The MathWorks, Inc.
%
%% Model Characteristics That Motivate Test Case Extension
%
% The <matlab:open_system('sldvdemo_sbr_extend_design') |sldvdemo_sbr_extend_design|> model includes the Stateflow(R) Chart <matlab:load_system('sldvdemo_sbr_extend_design');open_system('sldvdemo_sbr_extend_design/SBR') |SBR|> 
% that uses temporal logic so that very long test cases are required to make a 
% transition from the <matlab:load_system('sldvdemo_sbr_extend_design');sf('Open',sldvdemo_ssid_to_sfid('sldvdemo_sbr_extend_design/SBR',1)) |KEY_OFF|> state to the <matlab:load_system('sldvdemo_sbr_extend_design');sf('Open',sldvdemo_ssid_to_sfid('sldvdemo_sbr_extend_design/SBR',2)) |KEY_ON|> state. This type of time-delay 
% characteristic is common in designs where a delay is used to reject 
% spurious behavior or to wait for a physical system or user to respond. In 
% this design, satisfying the temporal logic in this <matlab:load_system('sldvdemo_sbr_extend_design');sf('Open',sldvdemo_ssid_to_sfid('sldvdemo_sbr_extend_design/SBR',11)) transition> is a common 
% obstacle to testing any of the states and transitions within the <matlab:load_system('sldvdemo_sbr_extend_design');sf('Open',sldvdemo_ssid_to_sfid('sldvdemo_sbr_extend_design/SBR',2)) |KEY_ON|> state.  
%
% Fortunately, this type of time-delay characteristic is usually easy to 
% identify and satisfy with a manually authored test case. 

open_system('sldvdemo_sbr_extend_design');
sf('Open',sldvdemo_ssid_to_sfid('sldvdemo_sbr_extend_design/SBR',11));

%% Creating a Harness Model and Defining Starting Tests
% The Simulink Design Verifier function <matlab:doc('sldvmakeharness') |sldvmakeharness|> creates a harness 
% model with a block that generates input values to the test model included 
% by way of a model reference block.
%
% You can modify the test data in a harness model by manually editing the 
% data values using the Signal Builder user interface.  You can also add 
% more test cases by creating new signal groups in the block. Alternatively, 
% you can use the <matlab:doc('signalbuilder') |signalbuilder|> command to programmatically accomplish 
% the same thing.  
%
% In this example, you specify a test case that keeps the system in the 
% <matlab:load_system('sldvdemo_sbr_extend_design');sf('Open',sldvdemo_ssid_to_sfid('sldvdemo_sbr_extend_design/SBR',1)) |KEY_OFF|> state for 5 seconds:

opts = sldvharnessopts;
opts.harnessSource = 'Signal Builder';
[~, harnessModelFilePath] = sldvmakeharness('sldvdemo_sbr_extend_design', [], opts);
[~, harnessModel] = fileparts(harnessModelFilePath);

startingTestTime = 0:0.5:5;
startingTestData = cell(3, 1);
lengthStartingTest = length(startingTestTime);
startingTestData{1} = zeros(1,lengthStartingTest);
startingTestData{2} = zeros(1,lengthStartingTest);
startingTestData{3} = ones(1,lengthStartingTest);

signalBuilderBlock = sldvdemo_signalbuilder_block(harnessModel);
signalbuilder(signalBuilderBlock,'Append',...
    startingTestTime, startingTestData,...
    {'Inputs.Speed','Inputs.SeatBeltFasten','Inputs.KEY'},'Starting Test Case');

signalbuilder(signalBuilderBlock, 'ActiveGroup', 2);
open_system(signalBuilderBlock);


%% Logging Starting Tests
% In order to leverage the starting test case defined above, you use the 
% <matlab:doc('sldvlogsignals') |sldvlogsignals|> function to capture the input values in the necessary 
% logged data format.
% 
% The first input to <matlab:doc('sldvlogsignals') |sldvlogsignals|> is the path to a Model block, and the second 
% input is the index of signal group(s) within the harness model. When you invoke 
% <matlab:doc('sldvlogsignals') |sldvlogsignals|>, the parent model that contains 
% the Model block is simulated.  
%
% The parent model is not restricted to Simulink Design Verifier harness 
% models. Alternatively, you might log data from a closed-loop simulation 
% model that uses a Model block to include the controller so that controller 
% test cases more realistically reflect the continuous time behavior 
% expected in the closed-loop system.
 
[~, modelBlock] = find_mdlrefs(harnessModel, false);
loggeddata = sldvlogsignals(modelBlock{1},2);

%% Extending Existing Tests During Test Generation
% Before you can use existing test data during test generation, the data 
% must be saved to a MAT-file. You enable test case extension 
% in the Test Generation pane of the Simulink Design Verifier configuration
% parameters. Select *Extend existing test cases*, 
% and specify the MAT file in the *Data file* field.
%
% Generated tests either extend one of the starting test cases with one or 
% more new time steps or will specify one or more time steps starting from 
% the initial, or default, configuration. 

save('existingtestcase.mat', 'loggeddata');

opts = sldvoptions;
opts.ExtendExistingTests = 'on';
opts.ExistingTestFile = 'existingtestcase.mat';
opts.SaveHarnessModel = 'off';
opts.SaveReport = 'off';
                  
[~, fileNames] = sldvrun('sldvdemo_sbr_extend_design', opts, true);

%% Verifying Complete Coverage
% The <matlab:doc('sldvruntest') |sldvruntest|> function verifies that the new test suite achieves complete 
% model coverage.  The <matlab:doc('cvhtml') |cvhtml|> function produces a coverage report that indicates 
% 100% Decision coverage is achieved with the generated test vectors.

[~, finalCov] = sldvruntest('sldvdemo_sbr_extend_design', fileNames.DataFile, [], true);
cvhtml('Final Coverage', finalCov);

%% Clean Up
% To complete the demo, close all models and remove the saved logged data 
% file.

close_system(harnessModel,0);
close_system('sldvdemo_sbr_extend_design');
delete('existingtestcase.mat');

displayEndOfDemoMessage(mfilename)
