Index of /nchou/s/matlab-2021b/examples/hdlcoder/data

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[IMG]AXI4_IP_with_readback.png2021-06-29 19:10 166K 
[IMG]AXI4_IP_with_readbackPipeline_CLI.png2021-06-29 19:10 80K 
[IMG]AXI4_IP_with_readbackPipeline_GUI.png2021-06-29 19:10 171K 
[IMG]AXI4_IP_with_readbackPipeline_HDLproperties.png2021-06-29 19:10 94K 
[IMG]AXI4_IP_with_readbackPipeline_options.png2021-06-29 19:10 68K 
[IMG]AXI4_IP_with_readbackPipeline_rightclick.png2021-06-29 19:10 157K 
[IMG]AXI4_IP_with_readbackPrototype1.PNG2021-06-29 19:10 97K 
[IMG]AXI4_IP_with_readbackPrototype2.PNG2021-06-29 19:10 3.7K 
[IMG]AXI4_IP_with_readbackPrototype3.PNG2021-06-29 19:10 134K 
[IMG]AXI4_IP_with_readbackPrototype4.PNG2021-06-29 19:10 97K 
[IMG]AXI4_IP_with_readbackPrototype5.PNG2021-06-29 19:10 98K 
[IMG]AXI4_IP_with_readback_AXImaster.png2021-06-29 19:10 128K 
[IMG]AXI4_IP_with_readback_devmemscal.png2021-06-29 19:10 89K 
[IMG]AXI4_IP_with_readback_devmemvec.png2021-06-29 19:10 125K 
[IMG]AXI4_IP_with_readback_interfacetable.png2021-06-29 19:10 243K 
[IMG]AXI4_IP_with_readback_optionCLI.png2021-06-29 19:10 57K 
[IMG]AXI4_IP_with_readback_optionGUI.png2021-06-29 19:10 162K 
[IMG]Bus_creator_signals_in_bus.png2020-07-16 12:20 14K 
[ ]DUT.v2018-10-05 15:21 1.1K 
[ ]FunkyDrums_48_stereo_25secs.mat2020-01-11 13:05 7.6M 
[IMG]GenerateHighlightScript.png2021-07-21 00:52 37K 
[IMG]HDL_DUT_virtual.png2019-01-11 11:28 8.5K 
[IMG]LUTMapToRAM_HighlightedModel.png2021-07-21 00:52 29K 
[IMG]MATLAB_Function_simple_multiplications.png2019-07-11 22:41 3.5K 
[IMG]NG1_implicit.png2019-01-18 14:47 13K 
[ ]NG1_implicit.v2019-01-18 14:47 162  
[IMG]Subsystem_Foreach_VHDL.png2016-12-19 10:07 6.2K 
[IMG]Synth_report_dspsubsys1.png2020-01-16 20:59 17K 
[IMG]Synth_report_dspsubsys2.png2020-01-16 20:59 18K 
[ ]Top.vhd2018-10-09 18:25 1.4K 
[ ]VerilogOperators.v2018-06-18 12:37 679  
[IMG]axi_master_ipcore.png2020-01-06 21:06 125K 
[IMG]axi_master_read_waveform.png2017-07-21 11:06 50K 
[ ]blackboxtop.v2018-06-28 07:24 412  
[IMG]blackboxtopmodule.v.png2018-06-28 07:25 15K 
[IMG]bus_data_type_address.png2020-12-10 14:07 77K 
[IMG]bus_data_type_initial_value_direct.png2020-12-10 14:07 17K 
[IMG]bus_example_initial_value_variable.png2020-12-10 14:07 11K 
[IMG]bus_example_target_interface.png2020-12-10 14:07 117K 
[IMG]bus_initial_value_in_IPCore_report.png2020-12-10 14:07 79K 
[ ]comparator.v2019-01-18 10:58 330  
[IMG]comparator.v.png2019-01-18 10:58 13K 
[IMG]compare_error_validationmodel.png2017-12-13 10:39 18K 
[IMG]compare_zeroerror_validationmodel.png2017-12-13 10:39 18K 
[ ]conditionalcomb.v2018-06-27 16:00 357  
[IMG]cosim_fil_sobel_screen1.png2021-03-03 15:28 16K 
[IMG]cosim_fil_sobel_screen2.png2021-03-03 15:28 31K 
[IMG]cosim_fil_sobel_screen3.png2021-03-03 15:28 30K 
[IMG]cpe_MLFB_MATLAB_Function.png2019-07-11 22:41 45K 
[IMG]distpipe_MLFB_MATLAB_Datapath1.png2019-07-11 22:41 25K 
[IMG]distpipe_MLFB_MATLAB_Datapath2.png2019-07-11 22:41 23K 
[IMG]distpipe_MLFB_MATLAB_Function1.png2019-07-11 22:41 23K 
[IMG]distpipe_MLFB_MATLAB_Function2.png2019-07-11 22:41 94K 
[IMG]distributed_pipelining_report_soe_vectors.png2018-09-04 10:07 65K 
[ ]example.v2018-06-18 11:00 385  
[IMG]example.v.png2019-01-18 12:13 26K 
[ ]example1.v2019-01-18 12:13 398  
[ ]example2.v2018-06-18 11:00 208  
[IMG]example_top.v.png2018-06-18 12:51 12K 
[IMG]filter_select_block_parameters.png2020-01-16 10:33 21K 
[IMG]foreach_subsystem_equivalent.png2016-12-19 10:07 39K 
[IMG]gm1_hdlcoder_nfp_delay_allocation.png2017-06-03 19:40 4.9K 
[IMG]gm1_hdlcoder_nfp_delay_allocation1.png2017-05-25 08:37 4.0K 
[IMG]gm_ap_off.png2021-01-12 10:55 40K 
[IMG]gm_ap_on.png2021-01-12 10:55 48K 
[IMG]gm_combine_operations.png2017-12-26 11:52 4.7K 
[IMG]gm_constant_folding.png2018-01-03 14:39 41K 
[IMG]gm_distpipe_mult_chain1.png2019-07-11 22:42 50K 
[IMG]gm_distpipe_mult_chain2.png2019-07-11 22:42 59K 
[IMG]gm_foreach_subsystem.png2017-03-28 09:44 36K 
[IMG]gm_foreach_subsystem_instance.png2017-03-28 09:44 26K 
[IMG]gm_hdlcoder_nfp_delay_allocation.png2017-06-03 19:40 6.2K 
[IMG]gm_hdlcoder_nfp_delay_allocation_custom.png2018-07-02 11:14 4.1K 
[IMG]gm_hdlcoder_test_points.png2018-01-09 16:13 63K 
[IMG]gm_matlab_datapath_MLFB_inside.png2019-07-11 22:41 8.5K 
[IMG]gm_model_pipeline_register_added.png2021-07-21 00:52 55K 
[IMG]gm_ram_mapping_matlab_datapath.png2019-07-11 22:41 37K 
[IMG]gm_strength_reduction.png2017-12-26 11:51 10K 
[IMG]guideline_synthesis_lut_noram.png2018-11-20 11:10 18K 
[IMG]guideline_synthesis_lut_ram.png2018-11-20 11:10 19K 
[IMG]hdl_check_report_mixed_types.png2017-06-05 15:51 17K 
[IMG]hdl_coder_external_memory_hw_zcu102_output.png2020-12-10 14:07 5.9K 
[IMG]hdl_coder_external_memory_simulation_output.png2020-12-10 14:07 5.5K 
[IMG]hdlcoder_DPIC_testbench_concept.png2020-05-14 14:48 44K 
[IMG]hdlcoder_IPCore_JTAGAXI_hdlwa2.png2021-06-29 19:10 55K 
[IMG]hdlcoder_IPCore_JTAGAXI_hdlwa4.png2021-06-29 19:10 78K 
[IMG]hdlcoder_deca_IPCore_JTAGAXI_hdlwa3.png2021-06-29 19:10 27K 
[IMG]hdlcoder_deca_IPCore_JTAGAXI_hdlwa4.png2021-06-29 19:10 42K 
[IMG]hdlcoder_deca_jtag_master_board.png2021-06-29 19:10 219K 
[IMG]hdlcoder_deca_jtag_master_completed_workflow_new.png2021-06-29 19:10 99K 
[IMG]hdlcoder_deca_jtag_master_diagram.png2021-06-29 19:10 35K 
[IMG]hdlcoder_deca_jtag_master_ipcore_report.png2021-06-29 19:10 204K 
[IMG]hdlcoder_deca_jtag_master_matlab_jtag_diagram.png2021-06-29 19:10 60K 
[IMG]hdlcoder_deca_jtag_master_qsys_connection_map.png2021-06-29 19:10 193K 
[IMG]hdlcoder_deca_jtag_master_qsys_jtag_diagram.png2021-06-29 19:10 45K 
[IMG]hdlcoder_deca_jtag_master_register_address_mapping.png2021-06-29 19:10 44K 
[IMG]hdlcoder_deca_jtag_master_system_console.png2021-06-29 19:10 42K 
[IMG]hdlcoder_external_memory_hw_output.png2020-12-30 09:36 3.2K 
[IMG]hdlcoder_external_memory_hw_output_ZCU102.png2020-12-30 09:36 3.5K 
[IMG]hdlcoder_external_memory_ip_block_diagram.png2020-12-30 09:36 9.2K 
[IMG]hdlcoder_external_memory_logic_analyzer.png2020-12-30 09:36 85K 
[IMG]hdlcoder_external_memory_matrix_vector_mult.png2020-12-30 09:36 12K 
[IMG]hdlcoder_external_memory_target_interface.png2020-12-30 09:36 71K 
[IMG]hdlcoder_gm_divide_delay_absorption.png2020-09-26 05:30 27K 
[IMG]hdlcoder_gm_high_rate_diff.png2017-10-12 11:36 47K 
[IMG]hdlcoder_gm_medium_rate_diff.png2017-10-12 12:41 46K 
[IMG]hdlcoder_gm_sharing_delay_absorption.png2020-09-26 05:30 29K 
[IMG]hdlcoder_gm_single_rate.png2017-10-12 11:48 33K 
[IMG]hdlcoder_gm_stream_vector_gain.png2020-09-29 12:42 31K 
[IMG]hdlcoder_high_rate_diff.png2017-10-12 11:36 37K 
[IMG]hdlcoder_kc705_jtag_master_block_diagram.png2021-06-29 19:10 166K 
[IMG]hdlcoder_kc705_jtag_master_board.png2021-06-29 19:10 507K 
[IMG]hdlcoder_kc705_jtag_master_diagram.png2021-06-29 19:10 34K 
[IMG]hdlcoder_kc705_jtag_master_ipcore_report.png2021-06-29 19:10 202K 
[IMG]hdlcoder_kc705_jtag_master_matlab_jtag_diagram.png2021-06-29 19:10 60K 
[IMG]hdlcoder_kc705_jtag_master_register_address_mapping.png2021-06-29 19:10 92K 
[IMG]hdlcoder_kc705_jtag_master_vivado_jtag_diagram.png2021-06-29 19:10 43K 
[IMG]hdlcoder_kc705_jtag_master_vivado_tcl_console_1.png2021-06-29 19:10 53K 
[IMG]hdlcoder_kc705_jtag_master_workflow_completion_new.png2021-06-29 19:10 226K 
[IMG]hdlcoder_makehdl_high_rate_diff.png2017-10-12 11:36 34K 
[IMG]hdlcoder_makehdl_medium_rate_diff.png2017-10-12 12:41 157K 
[IMG]hdlcoder_makehdl_single_rate.png2017-10-12 11:48 113K 
[IMG]hdlcoder_medium_rate_diff.png2017-10-12 12:41 37K 
[IMG]hdlcoder_nfp1_delay_allocation.png2017-06-03 19:40 13K 
[IMG]hdlcoder_nfp2_delay_allocation.png2017-06-03 19:40 12K 
[IMG]hdlcoder_nfp_delay_allocation.png2017-06-03 19:40 11K 
[IMG]hdlcoder_nfp_delay_allocation_oversampling.png2017-06-03 19:40 15K 
[IMG]hdlcoder_single_rate.png2017-10-12 11:48 34K 
[IMG]hdlcoder_tb_options.png2020-05-14 14:48 61K 
[IMG]hdlmodelchecker_sfir_single.png2019-10-16 10:38 47K 
[IMG]hparams_fields.png2018-04-11 13:09 13K 
[IMG]if_else_chart_verilog.png2019-09-04 11:07 16K 
[IMG]if_only_chart_verilog.png2019-09-04 11:07 13K 
[IMG]implicit_top.png2019-01-18 14:47 9.4K 
[ ]implicit_top.v2019-01-18 14:47 267  
[IMG]intel_fpga_dsp_arch_guideline.png2019-11-01 15:41 50K 
[ ]intelip.v2018-06-28 07:25 208  
[IMG]intelipmodule.v.png2018-06-28 07:25 5.3K 
[IMG]line_buffer_ml_code.png2019-07-11 22:41 16K 
[IMG]mlhdlc_filespec_dialog.png2021-01-05 12:49 52K 
[IMG]mlhdlc_ip_core_led_blinking_build_bitstream.png2021-07-13 04:05 89K 
[IMG]mlhdlc_ip_core_led_blinking_create_edk_project.png2021-07-13 04:05 99K 
[TXT]mlhdlc_ip_core_led_blinking_driver.c2021-07-13 04:05 2.3K 
[TXT]mlhdlc_ip_core_led_blinking_driver.h2021-07-13 04:05 321  
[IMG]mlhdlc_ip_core_led_blinking_fixed_point_conv.png2021-07-13 04:05 67K 
[IMG]mlhdlc_ip_core_led_blinking_program.png2021-07-13 04:05 89K 
[IMG]mlhdlc_ip_core_led_blinking_select_codegen_target.png2021-07-13 04:05 80K 
[IMG]mlhdlc_ip_core_led_blinking_set_target_interface.png2021-07-13 04:05 92K 
[IMG]mlhdlc_ip_core_led_blinking_software.png2021-07-13 04:05 12K 
[IMG]mult_chain_ml_code.png2019-07-11 22:42 8.5K 
[IMG]nfp_latency_strategy_model.png2017-05-25 08:37 31K 
[IMG]numeric_differences_sincos_optimization.png2020-07-16 13:04 22K 
[IMG]oversampling_factor_config_params.png2017-05-25 08:37 32K 
[IMG]persistent_MLFB_alg_loop.png2019-08-29 10:45 11K 
[IMG]ram_mapping_mappersistentvars_disabled.png2019-07-11 22:41 10K 
[IMG]ram_mapping_mappersistentvars_enabled.png2019-07-11 22:41 9.7K 
[ ]round_constant.v2019-01-18 14:47 123  
[IMG]scope_sw_model_multiple_streamchannels.png2020-01-11 13:05 63K 
[IMG]seq_comb.v.png2018-06-28 07:25 28K 
[ ]sequentialexp.v2018-06-27 16:00 335  
[IMG]set_target_device_synth_tool_mutiple_streamchannels.png2020-01-11 13:05 39K 
[IMG]set_target_frequency_mutiple_streamchannels.png2020-01-11 13:05 23K 
[IMG]set_target_interface_multiple_streamchannels.png2020-01-11 13:05 106K 
[IMG]set_target_reference_design_multiple_streamchannels.png2020-01-11 13:05 34K 
[IMG]sharing_MATLAB_Datapath_across.png2019-07-11 22:41 34K 
[IMG]sharing_MATLAB_Datapath_inside.png2019-07-11 22:41 36K 
[IMG]sharing_MLFB_MATLAB_Datapath.png2019-07-11 22:41 51K 
[IMG]sharing_MLFB_MATLAB_Function.png2019-07-11 22:41 49K 
[ ]simple_dual_port_ram.v2019-01-18 15:49 604  
[IMG]simple_dual_port_ram.v.png2019-01-18 15:49 23K 
[IMG]sschdl_tutorial_variable_resistor_sschdlfailure.png2021-07-06 20:46 62K 
[IMG]sschdl_tutorial_variable_resistor_sschdlsuccess.png2021-07-06 20:46 66K 
[IMG]sschdl_tutorial_variable_resistor_variableResistorControl.png2021-07-06 20:46 19K 
[IMG]sw_interface_model_multiple_streamchannels.png2020-01-11 13:05 117K 
[IMG]synthesis_result_ap_off.png2021-01-12 10:55 43K 
[IMG]synthesis_result_ap_on.png2021-01-12 10:55 38K 
[TXT]system.tcl2021-07-06 20:46 36K 
[IMG]system_architecture_audio_multiple_streamchannels.png2020-01-11 13:05 73K 
[IMG]target_platform_table_axi_stream.png2018-07-13 10:43 37K 
[IMG]target_platform_table_axi_video.png2018-07-13 10:43 44K 
[IMG]test_points_generated_code.png2017-06-02 16:22 12K 
[IMG]test_points_hdl_workflow.png2018-01-09 16:13 22K 
[IMG]test_points_ip_core_report.png2018-01-09 16:13 58K 
[IMG]test_points_report.png2018-01-09 16:13 43K 
[IMG]testpoint_dut_ip_core_interface.png2018-01-09 16:13 15K 
[IMG]testpoint_software_interface_model.png2018-01-09 16:13 43K 
[IMG]verilog_operators.v.png2018-06-18 12:37 24K 
[IMG]vivado_project_multiple_streamchannels.png2020-01-11 13:05 111K 
[ ]weightingTable.mat2020-01-11 13:05 11K 
[IMG]xilinx_fpga_dsp_arch_guideline.png2019-11-01 15:41 33K 
[IMG]zedboard_setup_multiple_streamchannels.png2020-01-11 13:05 556K