%% Authoring a Reference Design for Live Camera Integration with Deep Learning Processor IP Core
% This example shows how to create an HDL Coder(TM) reference design that
% contains a generated deep learning processor IP core.
%  The reference design receives a live camera input and uses a deployed 
% series network to classify the objects in the camera input.
% This figure is a high-level architectural diagram that shows the reference
% design that will be implemented on the Xilinx(TM) Zynq(TM)
% Ultrascale+(TM) MPsoC ZCU102 Evaluation Kit.
%
% <<../zcu102_reference_design_overview.png>>
%
% 
%%
% The user IP core block:
%%
%
% * Extracts the region of interest (ROI) based on ROI dimensions from the processing system (PS)
% (ARM).
% * Performs downsampling on the input image.
% * Zero-centers the input image.
% * Transfers the preprocessed image to the external DDR memory.
% * Triggers the deep learning processor IP core.
% * Notifies the PS(ARM) processor.
%
% The deep learning processor IP core accesses the preprocessed inputs,
% performs the object classification and loads the output results back into
% the external DDR memory.
%
% The PS (ARM):
%% 
% 
% * Takes the ROI dimensions and passes them to the user IP core.
% * Performs post-processing on the image data.
% * Annotates the object classification results from the deep learning
% processor IP core on the output video frame.
%
% You can also use MATLAB(R) to retrieve the classification results and
% verify the generated deep learning processor IP core.
% The user DUT for this reference design is the preprocessing algorithm (User IP Core).
% You can design the preprocessing DUT algorithm in Simulink(R), generate
% the DUT IP core, and integrate the generated DUT IP core into the larger system that contains the deep
% learning processor IP core. To learn how to generate the DUT IP core, see
% <docid:dlhdl_ug#mw_4c481c74-a7bf-494f-8d3e-b5ebc792419e Running a Deep
% Learning Network on FPGA with Live Camera Input>.
%% Generate Deep Learning Processor IP Core
% Follow these steps to configure and generate the
% deep learning processor IP core into the reference design.
%
% 1. Create a custom deep learning processor configuration.
%
%   hPC = dlhdl.ProcessorConfig
%
% To learn more about the deep learning processor architecture, see
% <docid:dlhdl_ug#mw_5e63c425-2c86-4e9e-8395-90f5d507be22 Deep Learning
% Processor Architecture>. To get information about the custom processor
% configuration parameters and modifying the parameters, see
% <docid:dlhdl_ref#mw_7558e39d-ea31-4164-9d01-585333c42763
% |getModuleProperty|> and
% <docid:dlhdl_ref#mw_fbe20c24-e092-4636-898f-a3c65d2aa206
% |setModuleProperty|>.
%
% 2. Generate the Deep Learning Processor IP core.
%
% To learn how to generate the custom deep learning processor IP, see
% <docid:dlhdl_ug#mw_6eeb279b-19a6-4667-b824-142021596a4f Generate Custom
% Processor IP>.
% The deep learning processor IP core is generated by using the HDL
% Coder(TM) IP core generation workflow. For more information, see <docid:hdlcoder_ug#bttvmwn Custom IP Core Generation>.
%
%   dlhdl.buildProcessor(hPC)
%
% The generated IP core files are located at |cwd\dlhdl_prj\ipcore|. |cwd| is
% the current working directory. The  |ipcore| folder contains an HTML
% report located at |cwd\dlhdl_prj\ipcore\DUT_ip_v1_0\doc|.
%
% <<../ipcore_generation_report.png>>
%
% The HTML report contains a description of the deep learning processor IP
% core, instructions for using the core and integrating the core into your
% Vivado(TM) reference design, and a list of AXI4 registers. You will need
% the AXI4 register list to enter addresses into the Vivado(TM) Address
% Mapping tool. For more information about the AXI4 registers, see
% <docid:dlhdl_ug#mw_c361b487-d242-47da-83fe-b72f66be4c5e Deep Learning
% Processor Register Map>.
%% Integrate the Generated Deep Learning Processor IP Core into the Reference Design
% Insert the generated deep learning processor IP core into your reference
% design. After inserting the generated deep learning processor IP core
% into the reference design, you must:
%
%%
% * Connect the generated deep learning processor IP core AXI4 slave interface
% to an AXI4 master device such as a JTAG AXI master IP core
% or a Zynq(TM) processing system (PS). Use the AXI4 master device to
% communicate with the deep learning processor IP core.
% * Connect the vendor provided external memory interface IP core
% to the three AXI4 master interfaces of the generated deep learning processor IP core.
%
% The deep learning processor IP core uses the external memory interface to
% access the external DDR memory.
% The image shows the deep learning processor IP core integrated into the
% Vivado(TM) reference design and connected to the DDR memory interface
% generator (MIG) IP.
%
% <<../vivado_live_video_DUT.jpg>>
%
%% Connect the External Memory Interface Generator
%
% In your Vivado(TM) reference design add an external memory interface
% generator (MIG) block and connect the generated deep learning processor
% IP core to the MIG module. The MIG module is connected to the processor IP core through
% an AXI interconnect module.
% The image shows the high level architectural design and the Vivado(TM)
% reference design implementation.
%
% <<../ipcore_integrated_reference_design.png>>
%
%% Create the Reference Design Definition File
%
% The following code describes the contents of the ZCU102 reference design
% definition file *plugin_rd.m* for the above Vivado(TM) reference design. For more
% details on how to define and register the custom board, refer to the
% <docid:hdlcoder_ug#example-hdlcoder_custom_board_ref_design_api Define
% Custom Board and reference Design for Zynq Workflow>.
%
%   function hRD = plugin_rd(varargin)
%  
%   % Parse config
%   config = ZynqVideoPSP.common.parse_config(...
%      'ToolVersion', '2019.1', ...
%      'Board', 'zcu102', ...
%       'Design', 'visionzynq_base', ...
%      'ColorSpace', 'RGB' ...
%   );
%   % Construct reference design object
%   hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado');
%   hRD.BoardName = ZynqVideoPSP.ZCU102Hdmicam.BoardName();
%   hRD.ReferenceDesignName = 'HDMI RGB with DL Processor';
%   % Tool information
%   hRD.SupportedToolVersion = {'2019.1'}
%   ...
%
%% Verify the Reference Design
%
% After creating the reference design, use the HDL Coder(TM) IP core
% generation workflow to generate the bitstream and program the ZCU102
% board. You can then use MATLAB(R) and a |dlhdl.Workflow| object to
% verify the deep learning processor IP core or you can use the HDL Coder(TM)
% workflow to prototype the entire system. To verify the reference design, see
% <docid:dlhdl_ug#mw_4c481c74-a7bf-494f-8d3e-b5ebc792419e Running a Deep
% Learning Network on FPGA with Live Camera Input>.
% 
% Copyright 2020 The MathWorks, Inc.
