%% Get Started with Deep Learning FPGA Deployment on Xilinx ZC706 SoC
% This example shows how to create, compile, and deploy a dlhdl.Workflow object that has a handwritten character detction series networkas the network object using the Deep Learning HDL Toolbox™ Support Package for Xilinx® FPGA and SoC. Use MATLAB® to retrieve the prediction results from the target device.
%% Prerequisites
% Xilinx® Zynq® ZC706 Evaluation Kit
% Deep Learning HDL Toolbox™ Support Package for Xilinx® FPGA and SoC
% Deep Learning Toolbox™
% Deep Learning HDL Toolbox™
%%
%
%% Load Pretrained Series Network
% Load the pretrained series network trained on the Modified National Institute of Standards and Technology (MNIST) database.

snet = getDigitsNetwork;

%
% View the layers of the pretrained series network, by using the analyzeNetwork function.

analyzeNetwork(snet)

%
%% Create Target Object
% Create a target object with a custom name for your target device and an interface to connect your target device to the host computer. Interface options are JTAG and Ethernet. To use JTAG, install Xilinx™ Vivado™ Design Suite 2019.2. To set the Xilinx Vivado toolpath, enter:

% hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2019.2\bin\vivado.bat');

%

hTarget = dlhdl.Target('Xilinx');

%
%% Create WorkFlow Object
% Create an object of the dlhdl.Workflow class. Specify the network and the bitstream name. Specify the saved pretrained MNIST neural network, snet, as the network. Make sure that the bitstream name matches the data type and the FPGA board that you are targeting. In this example the target FPGA board is the Xilinx Zynq ZC706 board. The bitstream uses a single data type.

hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'zc706_single','Target',hTarget);

%
%% Compile MNIST Series Network
% Run the compile function of the dlhdl.Workflow object, to compile the MNIST series network.

dn = hW.compile

%
%% Program Bitstream onto FPGA and Download Network Weights
% To deploy the network on the Xilinx ZC706 hardware, run the deploy function of the dlhdl.Workflow object. This function uses the output of the compile function to program the FPGA board by using the programming file. It also downloads the network weights and biases. The deploy function starts programming the FPGA device and displays progress messages and the time it takes to deploy the network.

hW.deploy

%
%% Load Example Image
% Load the example image.

inputImg = imread('five_28x28.pgm');
imshow(inputImg);

%
%% Run Prediction
% Execute the predict function of the dlhdl.Workflow object and display the prediction result and network performance.

[prediction, speed] = hW.predict(single(inputImg),'Profile','on');
[val, idx] = max(prediction);
fprintf('The prediction result is %d\n', idx-1);

% Copyright 2020 The MathWorks, Inc.