Random Access of External Memory

The example shows how to model external memory accesses from FPGA for rotating an ASCII art image. Many applications require FPGA to access memory in random fashion as per the requirements of algorithm. You will learn how to design memory address generation along with other AXI4 master signals to read and write specific regions of memory using SoC Blockset. You will simulate, implement and verify your design on hardware.

Design Task
Model Structure
Simulation
Implementation
Conclusion

Supported hardware platforms:

Artix® 7 35T Arty FPGA evaluation kit
Xilinx® Kintex® 7 KC705 development board
Xilinx Zynq® ZC706 evaluation kit
Xilinx Zynq UltraScale™+ MPSoC ZCU102 Evaluation Kit
Altera® Cyclone® V SoC development kit
Altera Arria® 10 SoC development kit

Design Task

The ASCII art image is encoded as 24-by-64 matrix of uint8 characters. The design task is to rotate the image by modeling AXI4 Master interfaces in FPGA logic for external memory access. By simulating the design with external memory model and the AXI4 protocol, you verify the behavior at application design time. This saves time otherwise spent in debugging the design on hardware during the implementation phase.

The overall dataflow is as described in figure below. The image is stored in the external memory at the memory region from address 0x00000000 to 0x000017FF. FPGA algorithm reads the image from this region and rotates it by writing it in the reverse order into the memory region from 0x00001800. Finally, the data is read back from the memory.

Model Structure

The models are structured using Model references. Top model 'soc_image_rotation' includes the FPGA model 'soc_image_rotation_fpga' using Model block as model reference.

The top model covers the following areas:

Testbench Input: It models the stimuli to set up the design for simulation. The AXI4 Master Source block initializes the input image data to the external memory. The Algorithm Start block sends a Start signal to the FPGA algorithm via Register Channel block. Open preload function soc_image_rotation_init.m to see how model parameters and input data are initialized.
Testbench Output: The AXI4 Master Sink block models the reading of the output image data from the external memory. The output data is saved in the variable AXI4MasterSinkContent in the workspace. Open stop function soc_image_rotation_post.m to see how input data and output data are plotted.
Memory: Memory system is modeled using one Memory Controller and two Memory Channel blocks. Input Read Memory Channel block models memory region 1 where input image is stored and Output Write Memory Channel block models memory region 2 where the rotated image is stored.
FPGA: This area instantiates the FPGA model reference which models the logic for AXI4 Master interfaces and data rotation.

FPGA model implements the algorithm in three subsystems, AXI4MasterRead, ReverseDataOrder and AXI4MasterWrite. Open FPGA subsystem for image rotation:

As the positive edge of start signal is detected, AXIMasterRead reads one line of image data and deliver it to ReverseDataOrder for reverses the order of data. The reversed data is then written to external memory by AXIMasterWrite subsystem. Once the data for one line is written, it sends a signal request_next_line to trigger reading of next line by AXIMasterRead. This cycle continues until all lines of the image are processed.

Open AXI4MasterReadController and AXI4MasterWriteController blocks to inspect the MATLAB® code for AXI4 Master interfaces. These blocks design the addressing logic for read and write operations as per AXI4 protocol. SoC Blockset supports AXI4 Master protocol and for timing diagrams of AXI4 signals, please refer to Model Design for AXI4 Master Interface Generation.

Simulation

Run the model and open the Logic analyzer from the FPGA model. Notice the following key points:

One line of data is written/read by masters in one burst. Since each line is 64 characters long; the burst length is 64 (0x400). Note this value on signals rd_len and wr_len.
Each character has 4 bytes as it is extended to unit32 data type, which makes the length of line 64x4 = 256 (0x100) bytes. Therefore, addresses increment/decrement by 0x100. Note this on rd_addr and wr_addr signals.
One read burst is followed by one write burst. Observe how rd_dvalid and wr_dvalid toggle alternatively.
request_next_line asserts after each write burst, which trigger the next read burst.

The input and output images are plotted at the end of simulation:

Implementation

Following products are required for this section:

HDL Coder™
SoC Blockset Support Package for Xilinx Devices, or
SoC Blockset Support Package for Intel® Devices

To implement the model on a supported FPGA board, use the SoC Builder application. Make sure you have installed required products and FPGA vendor software before implementation.

Open
<docid:soc_ref#mw_c7ffe7b7-da90-4248-9010-19b4413be7ab SoC Builder> from
the Tools menu and follow these steps:

Select 'Build Model' on 'Setup' screen. Click 'Next'.
Click 'View/Edit Memory Map' to view the memory map on 'Review Memory Map' screen. Notice that the base address 0x00000000 is assigned to Input Read Memory Channel block, and base address 0x00001800 is assigned to Output Write Memory Channel block. The AXI4 address is the sum of base address and address from FPGA algorithm. For example, wr_addr from FPGA algorithm starts with 0x1700. The output data will be written to the external memory from address 0x00001800 + 0x1700 = 0x00002F00. Refer to Model Design for AXI4 Master Interface Generation for more information about base address register calculation. Click 'Next'.
Specify project folder on 'Select Project Folder' screen. Click 'Next'.
Select 'Build, load and run' on 'Select Build Action' screen. Click 'Next'.
Click 'Validate' to check the compatibility of model for implementation on 'Validate Model' screen. Click 'Next'.
Click 'Build' to begin building of the model on 'Build Model' screen. An external shell will open when FPGA synthesis begins. Click 'Next' to 'Load Bitstream' screen.

The FPGA synthesis may take more than 30 minutes to complete. To save time, you may want to use the provided pre-generated bitstream by following these steps:

Close the external shell to terminate synthesis.
Copy pre-generated bitstream to your project folder by running the command below and then,
Click 'Load' button to load pre-generated bitstream.

>> copyfile(fullfile(matlabroot,'toolbox','soc','socexamples','bitstreams','soc_image_rotation-zc706.bit'), './soc_prj');

To run this example, copy the example test bench to your project folder.

>> copyfile(fullfile(matlabroot,'toolbox','soc','socexamples','soc_image_rotation_aximaster.m'), './soc_prj','f');

Enter the following command to run the test bench:

>> soc_image_rotation_aximaster

The test bench performs the following operations:

Initializes image rotation IP
Writes input image data to external memory
Starts the image rotation operation
Reads back and display output image data from external memory

If your FPGA board is not Xilinx Zynq ZC706 evaluation kit you need to do the following settings in the configuration parameters of the top model before launching the SoC Builder.

Select the 'Hardware board' under 'Hardware Implementation' panel to match your board.
Uncheck 'Include processing system' under 'Hardware Implementation -> Target hardware resources -> FPGA design (top-level)' panel.
Set 'Interconnect data width (bits)' to '32' under 'Hardware Implementation -> Target hardware resources -> FPGA design (mem channels)' panel.

Available pre-generated bitstreams are:

'soc_image_rotation-zc706.bit'
'soc_image_rotation-arty.bit'
'soc_image_rotation-kc705.bit'
'soc_image_rotation-a10soc.sof'

Modify the copyfile command and example test bench to match your board and selected project folder as appropriate. Note that pre-generated bitstream may not work if you customized the memory map.

Enter the following command to close the top model and FPGA model:

Conclusion