FIL Pixels To Frame

Convert pixel stream from FPGA-in-the-loop to frame-based video

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  • Library:

  • Vision HDL Toolbox / I/O Interfaces

  • FIL Pixels To Frame block

Description

The FIL Pixels To Frame block performs the same pixel-to-frame conversion as the Pixels To Frame block. In addition, you can configure the width of the input to be a single pixel, a line, or an entire frame per step. The block expects control signal input vectors of the same width as the pixel data. This optimization can speed up the communication link between the FPGA board and your Simulink® simulation when using FPGA-in-the-loop. To run FPGA-in-the-loop, you must have an HDL Verifier™ license.

When you generate a programming file for a FIL target in Simulink, the tool creates a model to compare the FIL simulation with your Simulink design. For Vision HDL Toolbox™ designs, the FIL block in that model replicates the pixel-streaming interface to send one pixel at a time to the FPGA. You can modify the autogenerated model to use the FIL Frame To Pixels and FIL Pixels To Frame blocks to improve communication bandwidth with the FPGA board by sending one frame at a time. For how to modify the autogenerated model, see FPGA-in-the-Loop.

Specify the same video format for the FIL Frames To Pixels block and the FIL Pixels To Frame block.

Ports

Input

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Image pixels, specified as a matrix of M-by-Number of pixels values, where M is the width of the Output vector format. There are N data ports, where N is the Number of components.

When you use multipixel streaming, the FIL DUT has Number of pixels data ports. You must recombine the output vectors from each port into a M-by-Number of pixels matrix. For details, see FPGA-in-the-Loop Simulation with Multipixel Streaming.

Similarly, when you use multicomponent-multipixel streaming, the FIL DUT has Number of pixels×Number of components data ports. Recombine the output vectors into a M-by-Number of pixels matrix for each component.

Data Types: single | double | int | uint | Boolean | fixed point

First pixel in a horizontal line of a frame, specified as a Boolean vector of M values.

For multipixel streaming, hStartIn applies to the pixel with the lowest index in the corresponding column.

Data Types: Boolean

Last pixel in a horizontal line of a frame, specified as a Boolean vector of M values.

For multipixel streaming, hEndIn applies to the pixel with the highest index in the corresponding column.

Data Types: Boolean

First pixel in the first (top) line of a frame, specified as a Boolean vector of M values.

For multipixel streaming, vStartIn applies to the pixel with the lowest index in the corresponding column.

Data Types: Boolean

Last pixel in the last (bottom) line of a frame, specified as a Boolean vector of M values.

For multipixel streaming, hEndIn applies to the pixel with the highest index in the corresponding column.

Data Types: Boolean

Valid pixel indicator, specified as a Boolean vector of M values.

For multipixel streaming, the pixels in the corresponding column are either all valid or all invalid.

Data Types: Boolean

Output

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Full image specified as a (Active pixels per line)-by-(Active video lines)-by-N matrix. Height and width are the dimensions of the active image specified in Video format. N is the Number of components used to express a single pixel. The data type is the same as data1,...,dataN.

A true (1) value indicates when output frame is successfully recompiled from the input stream.

Data Types: Boolean

Parameters

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Number of values used to represent each pixel. Each pixel can have 1, 3, or 4 components. Set this parameter to 1 for grayscale video. Set this parameter to 3 for color video, for example, {R,G,B} or {Y,Cb,Cr}. Set this parameter to 4 to use color with an alpha channel for transparency.

To process multicomponent streams for blocks that do not support multicomponent input, replicate the block for each component. The pixelcontrol bus for all components is identical, so you can connect the ctrl output of the Frame To Pixels block to each replicated block.

Number of pixels in each column of the input matrix, specified as 1, 4, or 8.

Each data port expects a M-by-Number of pixels matrix. You must recombine the FIL DUT output vectors to create this matrix. For details, see FPGA-in-the-Loop Simulation with Multipixel Streaming.

Size of the vector used to communicate with the FPGA subsystem. The block accepts input pixels and control signals in vectors of the same length. The block calculates the length of the vectors based on the Video format parameter.

  • Pixel — Accept scalar values for pixel and control signals.

  • Line — Accept input vectors containing Total pixels per line values.

  • Frame — Accept input vectors containing Total pixels per line × Total video lines values.

A larger value results in faster communication between the FPGA board and Simulink. Choose the largest option that the I/O and memory resources on your board can support.

For multipixel streaming, specify one of these options for input size.

  • Pixel — Accept a 1-by-(Number of pixels) vector of pixel values, and scalar control signals that apply to all the pixels in each vector.

  • Line — Accept a (Total pixels per line/Number of pixels)-by-Number of pixels matrix of pixel values, and a vector of control signals of length (Total pixels per line)/(Number of pixels).

  • Frame — Return a (Total pixels per line × Total video lines/Number of pixels)-by Number of pixels matrix of pixel values and a vector of control signals of length (Total pixels per line × Total video lines)/Number of pixels.

Dependencies

When Number of pixels and Number of components are both greater than 1, you must set Input vector format to Frame.

Dimensions of active regions of a video frame. To select a predefined format, use the Video format list. For a custom format, select Custom, and then specify the active frame dimensions as integers.

Video FormatActive Pixels Per LineActive Video Lines
240p320240
480p640480
480pH720480
576p720576
720p1280720
768p1024768
1024p12801024
1080p (default)19201080
1200p16001200
2KCinema20481080
4KUHDTV38402160
8KUHDTV76804320
CustomUser-
defined		User-
defined

Model Examples

FPGA-in-the-Loop Simulation with Vision HDL Toolbox Blocks

FPGA-in-the-Loop Simulation with Vision HDL Toolbox Blocks

Modify the generated FPGA-in-the-loop (FIL) model for more efficient simulation of the Vision HDL Toolbox™ streaming video protocol.

Extended Capabilities

See Also

Blocks

Topics

Introduced in R2015a

Vision HDL Toolbox Documentation

Support