Check Static Gap

Check that gap exists in signal's range of amplitudes

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  • Library:

  • Simulink / Model Verification

    HDL Coder / Model Verification

  • Check Static Gap block

Description

The Check Static Gap block checks that each element of the input signal is less than (or optionally equal to) a static lower bound or greater than (or optionally equal to) a static upper bound at the current time step. If the verification condition is true, the block does nothing. If not, the block halts the simulation, by default, and displays an error message.

Use the blocks in the Model Verification library to facilitate creation of self-validating models. For example, you can use model verification blocks to test that signals do not exceed specified limits during simulation. When you are satisfied that a model is correct, you can turn error checking off by disabling the verification blocks. You do not have to remove them from the model. If you need to modify a model, you can temporarily turn the verification blocks back on to ensure that your changes do not break the model.

Ports

Input

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Input signal the block checks if the signal value is less than a static lower bound or greater than a static upper bound.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Output

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Output signal at each time step that is true (1) if the assertion succeeds, and false (0) if the assertion fails. If, in the Configuration Parameters, you select Implement logic signals as Boolean data, then the output data type is a Boolean. Otherwise the data type of the signal is a double.

Dependencies

To enable this output port, set the Output assertion signal parameter check box.

Data Types: double | Boolean

Parameters

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Specify the upper bound on the range of amplitudes that the input signal can have.

Command-Line Information

Parameter: max
Type: character vector
Values: scalar | vector | matrix
Default: '0'

Select this check box to make the range of valid input amplitudes include the upper bound.

Command-Line Information

Parameter: max_included
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify the lower bound on the range of amplitudes that the input signal can have.

Command-Line Information

Parameter: min
Type: character vector
Values: scalar | vector | matrix
Default: '0'

Select this check box to make the range of valid input amplitudes include the lower bound.

Command-Line Information

Parameter: min_included
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Clearing this check box disables the block and causes the model to behave as if the block does not exist. You can set the Model Verification block enabling setting in the Configuration Parameters to enable or disable all model verification blocks in a model regardless of the setting of this option.

Command-Line Information

Parameter: enabled
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Command-Line Information

Parameter: callback
Type: character vector
Values: MATLAB expression
Default: ' '

Select this check box to indicate that the block halts simulation when the check fails. Clear to indicate that the software displays a warning and continues the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Selecting this check box causes the block to output a Boolean signal that is true (1) at each time step if the assertion succeeds and false (0) if the assertion fails. The data type of the output signal is Boolean if you have selected the Implement logic signals as Boolean data check box on the Configuration Parameters dialog box. Otherwise the data type of the output signal is double.

Command-Line Information

Parameter: export
Type: character vector
Values: 'on' | 'off'
Default: 'off'

Specify the type of icon used to display this block in a block diagram. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition. If the icon is too small to display the expression, the text icon displays an exclamation point. To see the expression, enlarge the block.

Command-Line Information

Parameter: icon
Type: character vector
Values: 'graphic' | 'text'
Default: 'graphic'

Block Characteristics

Data Types

Boolean | double | enumerated | fixed point | half | integer | single

Direct Feedthrough

no

Multidimensional Signals

yes

Variable-Size Signals

no

Zero-Crossing Detection

no

Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

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Introduced before R2006a

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