UVM Generation

Generate UVM components from Simulink® subsystems

Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.

  • Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.

  • Generate UVM test components, and integrate them into your existing UVM environment.

This feature requires Simulink Coder™.

Functions

uvmbuildGenerate UVM test bench from Simulink model

Objects

uvmcodegen.uvmconfigUVM configuration object

Topics

UVM Component Generation Overview

Generate a Universal Verification Methodology (UVM) from a Simulink model.

Customize Generated UVM Code

Customize file banners and HDL simulation timescale when generating a UVM test bench.

Generate SystemVerilog Assertions and Functional Coverage from verify Statement

Generate SystemVerilog DPI checks from a verify statement, and collect functional coverage information (requires Simulink Test™ license).

Use Tunable Parameters to Generalize UVM Simulation

Generate UVM parameters from Simulink tunable parameters.

Tunable Parameters in Sequence Subsystem

Generate random constraint parameters in UVM sequence from Simulink tunable parameters.

Tunable Parameters in Scoreboard Subsystem

Generate random constraint parameters in UVM scoreboard from Simulink tunable parameters.

Featured Examples

Generate Parameterized UVM Test Bench from Simulink

Generate Parameterized UVM Test Bench from Simulink

Develop a design and test bench in Simulink and generate an equivalent simulation for a Universal Verification Methodology (UVM) environment using uvmbuild. Related examples show how you can extend this test bench to refine your verification using protocol-specific drivers, constrained random sequences, and parameterized scoreboards.

Open Model
Replace Behavioral DUT with AXI-Based RTL DUT in UVM Test Bench

Replace Behavioral DUT with AXI-Based RTL DUT in UVM Test Bench

Move from a simple behavioral DUT interface to an RTL DUT interface which uses AXI Lite and AXI Stream bus protocols. Several of the UVM components must change such as the driver and monitor, but the original test bench structure and the sequence and scoreboard components can be re-used without modification.

Open Model
Add Random Constraints to Sequences in UVM Test Bench

Add Random Constraints to Sequences in UVM Test Bench

Add constrained random verification to a Universal Verification Methodology (UVM) test bench generated from Simulink. Both Simulink parameters and input ports to the stimulus generation results in randomizable sequence class data members in the UVM test bench. Through the use of standard UVM class inheritance and factory overrides, the design verification engineer can add new and valuable constrained random testcases to their UVM test suite.

Open Script
Change Parameters of Scoreboard in UVM Test Bench

Change Parameters of Scoreboard in UVM Test Bench

Control the parameters of the response checker in a UVM test bench generated from Simulink. Such parameterization helps the design verification engineer reuse the scoreboard under different testing scenarios. Simulink parameters to the checker will result in a configuration object whose values can be set in a derived test class (randomized or not) or directly via a command line plus arg.

Open Model
Include Driver and Monitor in UVM Test Bench

Include Driver and Monitor in UVM Test Bench

Uses the uvmbuild function to generate a Universal Verification Methodology (UVM) test bench, which includes a UVM driver and monitor from a Simulink® design and test bench.

Open Live Script

HDL Verifier Documentation

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