DPI Generation for Simulink Subsystem

Generate SystemVerilog DPI component from Simulink® subsystem

You can use a DPI component generated from a Simulink subsystem in two ways :

  • Export SystemVerilog DPI Component — You can integrate this component into your HDL simulation as a behavioral model. The component generator supports test points and tunable parameters. You can also generate a SystemVerilog test bench that verifies the generated DPI component against data vectors from your subsystem. See Generate SystemVerilog DPI Component.

  • Generate SystemVerilog DPI Test Bench (with HDL Coder™) — Use this test bench to verify your generated HDL code using C code generated from your entire Simulink model, including the DUT and data sources. See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).

See DPI Component Generation with Simulink. You must have a Simulink Coder™ license to use this feature.

Apps

HDL VerifierGenerate SystemVerilog DPI component from a Simulink subsystem

Blocks

AssertionGenerate SystemVerilog assertions from Simulink assertion

Topics

Generate and Verify a DPI Component

DPI Component Generation with Simulink

If you have a Simulink Coder license, you can generate SystemVerilog DPI components using one of two methods.

SystemVerilog DPI Test Benches

Choose between the two types of SVDPI test benches.

Generate SystemVerilog DPI Component

How to generate a SystemVerilog DPI component. This topic takes you through the workflow of generating a DPI component from Simulink, and explores various configuration parameters.

Use Generated DPI Functions in SystemVerilog

How to export the generated DPI component to a SystemVerilog environment.

Verify Generated Component Against Simulink Data

Start ModelSim® or Questa® in GUI mode.

Generate SystemVerilog Assertions from Simulink Test Bench

Generate SystemVerilog assertions from your Simulink environment.

Advanced DPI Options

Generate Cross-Platform DPI Components

Generate a DPI component for an operating system different from your MATLAB® host machine.

Customize Generated SystemVerilog Code

Describes how to customize the generated SystemVerilog code.

Tune Gain Parameter During Simulation

Generate a DPI component that provides tunable access to a parameter.

SystemVerilog DPI Component Test Point Access

You can designate internal signals in your model as test points and configure the SystemVerilog DPI generator to create one or more access functions.

Generate SystemVerilog Assertions and Functional Coverage from verify Statement

Generate SystemVerilog DPI checks from a verify statement, and collect functional coverage information (requires Simulink Test™ license).

Verify Generated HDL Code with SystemVerilog DPI Test Bench (requires HDL Coder license)

Verify HDL Design Using SystemVerilog DPI Test Bench

This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)

Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

Featured Examples

Building HDL Test Bench for QAM Transceiver Model

Building HDL Test Bench for QAM Transceiver Model

Build a behavioral test bench using SystemVerilog DPI-C component generation. This test bench is used for the verification of synthesizable HDL code of a 64-QAM transmitter and receiver.

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Generate Bit/Logic Vector Data Types

Generate Bit/Logic Vector Data Types

Generate bit or logic vector data types in the SystemVerilog interface of the DPI component. This capability is useful whenever having an exact width of the port is important to integrate the DPI component in your testbench.

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Getting Started with Customizing Generated SystemVerilog Code

Getting Started with Customizing Generated SystemVerilog Code

Customize the generated SystemVerilog code in the SystemVerilog DPI Component Generation process.

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Generate Native SystemVerilog Assertions from Simulink

Generate Native SystemVerilog Assertions from Simulink

Generate native SystemVerilog assertions from assertions in a Simulink model. This capability is useful whenever you need the same assertion behaviour in Simulink and in your HDL testing environment.

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Generating Functional Coverage in SystemVerilog from System Test verify Calls

Generating Functional Coverage in SystemVerilog from System Test verify Calls

Demonstrates how to test a projector control system using model simulation, and how to generate a SystemVerilog DPI component for some of the controller's high level requirements that are specified in a Test Sequence block. This will allow the requirement verification used for model simulation to be reused in the HDL simulator with minimal effort.

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HDL Verifier Documentation

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