A timing controller entity generates the required rates from a single master clock, using one or more counters to create multiple clock enables. The master clock rate is the fastest rate in the model in single clock mode. In multiple clock mode, it can be any clock in the DUT. The outputs of the timing controller are clock enable signals running at rates an integer multiple slower than the timing controller's master clock
When using single clock mode, HDL code generated from multirate models employs a single master clock that corresponds to the base rate of the DUT. When using multiple clock mode, HDL code generated from multirate models employs one clock input for each rate in the DUT. The number of timing controllers generated in multiple clock mode depends on the design in the DUT.
Each timing controller entity definition is written to a separate
code file. The timing controller file and entity names derive from
the name of the subsystem that is selected for code generation (the
DUT). To form the timing controller name, HDL Coder™ appends the
value of the TimingControllerPostfix property
to the DUT name.