This page describes configuration parameters that reside in the HDL Code Generation > EDA Tool Scripts > Simulation Script tab of the Configuration Parameters dialog box.
Specify a postfix to append to the DUT or test bench name to form the simulation script file name.
Default:
_sim.do
For example, if the name of the device under test or test bench is
my_design, HDL Coder™ adds the postfix _sim.do to form the name
my_design_sim.do.
Property:
HDLSimFilePostfix |
| Type: character vector |
Default:
'_sim.do' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
Format name passed to fprintf to write the initialization
section of the simulation script.
Default: The default is
['onbreak resume\nonerror resume\n']
The Init phase of the script performs required setup
actions, such as creating a design library or a project file.
Property:
HDLSimInit |
| Type: character vector |
Default:
['onbreak resume\nonerror resume\n']
|
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
Format name passed to fprintf to write the simulation
command.
Default:
vsim -voptargs=+acc %s.%s\n
The first implicit argument, %s, is the library name. The
second implicit argument is the top-level module or entity name. If your target
language is VHDL®, the library name is the value of VHDL library name. If your target language is Verilog®, the library name is 'work' and cannot be
changed.
If you compile your filter design with code from other libraries, update VHDL library name to avoid library name conflicts.
Note
Prior to R2020b, the default simulation command was vsim -novopt
%s.%s\n.
Mentor Graphics®
ModelSim® versions prior to 10.7 support the former
syntax. If you use a more recent
Mentor Graphics
ModelSim version, use the vsim -voptargs=+acc
%s.%s\n syntax.
Property:
HDLSimCmd |
| Type: character vector |
Default:
'vsim -novopt %s.%s\n' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
Specify the waveform viewing command written to simulation script.
Default:
add wave sim:%s\n
The implicit argument, %s, adds the signal paths for the DUT top-level input, output, and output reference signals.
Property:
HDLSimViewWaveCmd |
| Type: character vector |
Default:
'add wave sim:%s\n' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
Format name passed to fprintf to write the termination
portion of the simulation script.
Default:
run -all\n
The termination phase (Term) is the final execution phase
of the script. One application of this phase is to execute a simulation of HDL
code that was compiled in the Cmd phase. The
Term phase does not take arguments.
Property:
HDLSimTerm |
| Type: character vector |
Default:
'run -all\n' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
Specify simulator flags to apply to generated compilation scripts.
Default:
'' (no simulator flags)
Specify simulator flags to apply to generated compilation scripts as a
character vector. The simulator flags are specific to your application and the
simulator you are using. For example, if you must use the 1076–1993 VHDL compiler, specify the flag -93.
The flags you specify with this option are added to the compilation command in
generated compilation scripts. The simulation command is specified by the
HDLCompileVHDLCmd or
HDLCompileVerilogCmd properties.
Property:
SimulatorFlags |
| Type: character vector |
Default:
'' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.