RTL Style Parameters

This page describes parameters that reside in the HDL Code Generation > Global Settings > Coding Style tab of the Configuration Parameters dialog box.

Use “rising_edge/falling_edge” style for registers

Specify whether generated code uses the VHDL^® rising_edge or falling_edge function to detect clock transitions.

Settings

Default: Off

On

Generated code uses the VHDL rising_edge or falling_edge function.

For example, the following code, generated from a Unit Delay block, uses rising_edge to detect positive clock transitions:

Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF rising_edge(clk) THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

Off

Generated code uses the 'event syntax.

For example, the following code, generated from a Unit Delay block, uses clk'event AND clk = '1' to detect positive clock transitions:

Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

Dependency

This option is enabled when the target language is VHDL.

Command-Line Information

Property: UseRisingEdge

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Minimize intermediate signals

Specify whether to optimize HDL code for debuggability or code coverage.

Settings

Default: Off

On

Optimize for code coverage by minimizing intermediate signals. For example, suppose that the generated code with this setting off is:

const3 <= to_signed(24, 7);
subtractor_sub_cast <= resize(const3, 8);
subtractor_sub_cast_1 <= resize(delayout, 8);
subtractor_sub_temp <= subtractor_sub_cast - subtractor_sub_cast_1;

With this setting on, HDL Coder™ optimizes the output to:

subtractor_sub_temp <= 24 - (resize(delayout, 8));

The code generator removes the intermediate signals const3, subtractor_sub_cast, and subtractor_sub_cast_1.

Off

Optimize for debuggability by preserving intermediate signals.

Command-Line Information

Property: MinimizeIntermediateSignals

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Unroll for Generate Loops in VHDL code

Specify whether VHDL FOR and GENERATE loops are unrolled and omitted from generated VHDL code.

Settings

Default: Off

On: Unroll and omit FOR and GENERATE loops from the generated VHDL code. (In Verilog^® code, loops are always unrolled.)
Off: Include FOR and GENERATE loops in the generated VHDL code.

Tip

If you are using an electronic design automation (EDA) tool that does not support GENERATE loops, select this option to omit loops from your generated VHDL code.
Setting this option does not affect results obtained from simulation or synthesis of generated VHDL code.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

Property: LoopUnrolling

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Generate parameterized HDL code from masked subsystem

Generate reusable HDL code for subsystems with the same tunable mask parameters, but with different values.

Settings

Default: Off

On

Generate one reusable HDL file for multiple masked subsystems with different values for the mask parameters. HDL Coder automatically detects subsystems with tunable mask parameters that are sharable.

Inside the subsystem, you can use the mask parameter only in the following blocks and parameters.

Block	Parameter	Limitation
Constant	Constant value on the Main tab of the dialog box	None
Gain	Gain on the Main tab of the dialog box	Parameter data type must be the same for all Gain blocks.

Off

Generate a separate HDL file for each masked subsystem.

Command-Line Information

Property: MaskParameterAsGeneric

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Enumerated Type Encoding Scheme

Specify the encoding scheme to represent enumeration types in the generated HDL code.

Settings

Default: default

Use default, onehot, twohot, or binary encoding scheme to represent enumerated types in the generated HDL code.

default

The code generator uses decimal encoding in Verilog and VHDL-native enumerated types in VHDL. This example shows the verilog code snippet of this encoding scheme for a Stateflow^® Chart that has four states.

parameter 
is_Chart_IN_s_idle = 2'd0, 
is_Chart_IN_s_rx = 2'd1, 
is_Chart_IN_s_wait_0 = 2'd2, 
is_Chart_IN_s_wait_tb = 2'd3;

onehot

The code generator uses a one-hot encoding scheme where a single bit is high to represent each enumeration value. This example shows the verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 4'b0001, 
is_Chart_IN_s_rx = 4'b0010, 
is_Chart_IN_s_wait_0 = 4'b0100, 
is_Chart_IN_s_wait_tb = 4'b1000;

This encoding scheme does not support more than 64 enumeration values or number of states.

twohot

The code generator uses a two-hot encoding scheme where two bits are high to represent each enumeration value. This example shows the verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 4'b0011, 
is_Chart_IN_s_rx = 4'b0101, 
is_Chart_IN_s_wait_0 = 4'b0110, 
is_Chart_IN_s_wait_tb = 4'b1001;

binary

The code generator uses a binary encoding scheme to represent each enumeration value. This example shows the verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 2'b00, 
is_Chart_IN_s_rx = 2'b01, 
is_Chart_IN_s_wait_0 = 2'b10, 
is_Chart_IN_s_wait_tb = 2'b11;

In VHDL, the generated code uses CONSTANT types to encode nondefault enumeration values in the generated code. For example, this code snippet shows the generated VHDL code when you use the two-hot state encoding for a Stateflow Chart that has four states.

 PACKAGE s_pkg IS
  -- Constants
  -- Two-hot encoded enumeration values for type state_type_is_Chart
  CONSTANT IN_s_idle         : std_logic_vector(3 DOWNTO 0) := 
    "0011";
  CONSTANT IN_s_rx           : std_logic_vector(3 DOWNTO 0) := 
    "0101";
  CONSTANT IN_s_wait_0       : std_logic_vector(3 DOWNTO 0) := 
    "0110";
  CONSTANT IN_s_wait_tb      : std_logic_vector(3 DOWNTO 0) := 
    "1001";

END s_pkg;

Command-Line Information

Property: EnumEncodingScheme

Type: character vector

Value: 'default' | 'onehot' | 'twohot''binary'

Default: 'default'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

Documentation