The MATLAB to HDL Workflow task in the HDL Workflow Advisor generates HDL code from fixed-point MATLAB® code, and simulates and verifies the HDL against the fixed-point algorithm. HDL Coder™ then runs synthesis, and optionally runs place and route to generate a circuit description suitable for programming an ASIC or FPGA.
Select target hardware and language and required outputs.
Target hardware. Select from the list:
| Generic ASIC/FPGA |
| Xilinx |
| Altera |
| Simulation |
Select the language (VHDL® or Verilog®) in which code is generated. The selected language is referred to as the target language.
Default: VHDL
Enable HDL conformance checking.
Default: Off
Enable generation of HDL code for the fixed-point MATLAB algorithm.
Default: On
Enable generation of HDL code for the fixed-point test bench.
Default: Off
Enable generation of script files for third-party electronic design automation (EDA) tools. These scripts let you compile and simulate generated HDL code and synthesize generated HDL code.
Default: On
Parameters that affect the style of the generated code.
Include MATLAB code comments in generated code.
Default: On
Include MATLAB source code as comments in the generated code. The comments precede the associated generated code. Includes the function signature in the function banner.
Default: On
Enable a code generation report.
Default: Off
Specify the file name extension for generated VHDL files.
Default: .vhd
Specify the file name extension for generated Verilog files.
Default: .v
Specify comment lines in header of generated HDL and test bench files.
Default: None
Text entered in this field as a character vector generates a comment line in the header of the generated code. The code generator adds leading comment characters for the target language. When newlines or linefeeds are included in the text, the code generator emits single-line comments for each newline.
HDL Coder applies this option only if a package file is required for the design.
Default: _pkg
Specify the character vector to resolve duplicate VHDL entity or Verilog module names in generated code.
Default: _block
Specify a character vector to append to value names, postfix values, or labels that are VHDL or Verilog reserved words.
Default: _rsvd
Specify a character vector to append to HDL clock process names.
Default: _process
Specify a character vector to append to real part of complex signal names.
Default: '_re'
Specify a character vector to append to imaginary part of complex signal names.
Default: '_im'
Specify a character vector to append to names of input or output pipeline registers.
Default: '_pipe'
Specify the base name as a character vector for internal clock enables and other flow control signals in generated code.
Default: 'enb'
Clock and port settings
Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers.
Default: Asynchronous
Specify whether the asserted (active) level of reset input signal is active-high or active-low.
Default: Active-high
Enter the name for the reset input port in generated HDL code.
Default: reset
Specify the name for the clock input port in generated HDL code.
Default: clk
Specify the name for the clock enable input port in generated HDL code.
Default: clk
Specify frequency of global oversampling clock as a multiple of the design under test (DUT) base rate (1).
Default: 1
Specify the HDL data type for input ports.
For VHDL, the options are:
std_logic_vector
Specifies VHDL type STD_LOGIC_VECTOR
signed/unsigned
Specifies VHDL type SIGNED or UNSIGNED
Default: std_logic_vector
For Verilog, the options are:
In generated Verilog code, the data type for all ports is ‘wire’. Therefore, Input data type is disabled when the target language is Verilog.
Default: wire
Specify the HDL data type for output data types.
For VHDL, the options are:
Same as input data type
Specifies that output ports have the same type specified by Input data type.
std_logic_vector
Specifies VHDL type STD_LOGIC_VECTOR
signed/unsigned
Specifies VHDL type SIGNED or UNSIGNED
Default: Same as input data type
For Verilog, the options are:
In generated Verilog code, the data type for all ports is ‘wire’. Therefore, Output data type is disabled when the target language is Verilog.
Default: wire
Specify the name for the clock enable input port in generated HDL code.
Default: clk_enable
Test bench settings.
Specify a character vector appended to names of reference signals generated in test bench code.
Default: '_tb’
Specify whether the test bench forces clock enable input signals.
Default: On
Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1).
Default: 5
Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0).
Default: 5
Specify a hold time, in nanoseconds, for input signals and forced reset input signals.
Default: 2 (given the default clock period of 10 ns)
Display setup time for data input signals.
Default: 0
Specify whether the test bench forces clock enable input signals.
Default: On
Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable.
Default: 1
Specify whether the test bench forces reset input signals.
Default: On
Define length of time (in clock cycles) during which reset is asserted.
Default: 2
Specify how long subrate signal values are held in valid state.
Default: On
Specify initial value driven on test bench inputs before data is asserted to device under test (DUT).
Default: Off
Divide generated test bench into helper functions, data, and HDL test bench code files.
Default: Off
Specify suffix added to test bench data file name when generating multi-file test bench.
Default: '_data’
Specify a character vector to append to names of reference signals generated in test bench code.
Default: '_ref'
Specify number of samples during which output data checking is suppressed.
Default: 0
To generate a test bench, HDL Coder simulates the original MATLAB code.
Use the Fixed-Point Designer™ fiaccel function
to accelerate this simulation and accelerate test bench logging.
Default: On
Optimization settings
Select to map persistent array variables to RAMs instead of mapping to shift registers.
Default: Off
Dependencies:
RAM Mapping Threshold
Persistent variable names for RAM Mapping
Specify the minimum RAM size required for mapping persistent array variables to RAMs.
Default: 256
Provide the names of the persistent variables to map to RAMs.
Default: None
Specify number of pipeline registers to insert at top level input ports. Can improve performance and help to meet timing constraints.
Default: 0
Specify number of pipeline registers to insert at top level output ports. Can improve performance and help to meet timing constraints.
Default: 0
Reduces critical path by changing placement of registers in design. Operates on all registers, including those inserted using the Input Pipelining and Output Pipelining parameters, and internal design registers.
Default: Off
Number of additional sources that can share a single resource, such as a multiplier. To share resources, set Sharing Factor to 2 or higher; a value of 0 or 1 turns off sharing.
In a design that performs identical multiplication operations, HDL Coder can reduce the number of multipliers by the sharing factor. This can significantly reduce area.
Default: 0
Simulates the generated HDL code using the selected simulation tool.
Lists the available simulation tools.
Default: None
Default: Off
| Conditions | Recommended Action |
|---|---|
| No simulation tool available on system path. | Add your simulation tool path to the MATLAB system path, then restart MATLAB. For more information, see Synthesis Tool Path Setup. |
This folder contains tasks to create a synthesis project for the HDL code. The task then runs the synthesis and, optionally, runs place and route to generate a circuit description suitable for programming an ASIC or FPGA.
Default: Off
Skip this step if you are interested only in simulation or you do not have a synthesis tool.
Create synthesis project for supported synthesis tool.
Description. This task creates a synthesis project for the selected synthesis tool and loads the project with the HDL code generated for your MATLAB algorithm.
You can select the family, device, package, and speed that you want.
When the project creation is complete, the HDL Workflow Advisor displays a link to the project in the right pane. Click this link to view the project in the synthesis tool's project window.
Input Parameters
Select from the list:
Altera Quartus II
Generate a synthesis project for Altera® Quartus II. When you select this option, HDL Coder sets:
Chip Family to Stratix
II
Device Name to EP2S60F1020C4
You can manually change these settings.
Xilinx ISE
Generate a synthesis project for Xilinx® ISE. When you select this option, HDL Coder:
Sets Chip Family to Virtex4
Sets Device Name to xc4vsx35
Sets Package Name to ff6...
Sets Speed Value to —...
You can manually change these settings.
Default: No
Synthesis Tool Specified
When you select No
Synthesis Tool Specified, HDL Coder does not generate
a synthesis project. It clears and disables the fields in the Synthesis
Tool Selection pane.
Target device family.
Default: None
Specific target device, within selected family.
Default: None
Available package choices. The family and device determine these choices.
Default: None
Available speed choices. The family, device, and package determine these choices.
Default: None
Results and Recommended Actions
| Conditions | Recommended Action |
|---|---|
| Synthesis tool fails to create project. | Read the error message returned by synthesis tool, then check the synthesis tool version, and check that you have write permission for the project folder. |
| Synthesis tool does not appear in dropdown list. | Add your synthesis tool path to the MATLAB system path, then restart MATLAB. For more information, see Synthesis Tool Path Setup. |
Launch selected synthesis tool and synthesize the generated HDL code.
Description. This task:
Launches the synthesis tool in the background.
Opens the previously generated synthesis project, compiles HDL code, synthesizes the design, and emits netlists and related files.
Displays a synthesis log in the Result subpane.
Results and Recommended Actions
| Conditions | Recommended Action |
|---|---|
| Synthesis tool fails when running place and route. | Read the error message returned by the synthesis tool, modify the MATLAB code, then rerun from the beginning of the HDL Coder workflow. |
Launches the synthesis tool in the background and runs a Place and Route process.
Description. This task:
Launches the synthesis tool in the background.
Runs a Place and Route process that takes the circuit description produced by the previous mapping process, and emits a circuit description suitable for programming an FPGA.
Displays a log in the Result subpane.
Input Parameters
If you select Skip this step, the HDL Workflow Advisor executes the workflow, but omits the Perform Place and Route, marking it Passed. You might want to select Skip this step if you prefer to do place and route work manually.
Default: Off
Results and Recommended Actions
| Conditions | Recommended Action |
|---|---|
| Synthesis tool fails when running place and route. | Read the error message returned by the synthesis tool, modify the MATLAB code, then rerun from the beginning of the HDL Coder workflow. |