You can use one or more DocBlock blocks to integrate custom HDL code into your design.
If you want to keep the HDL code with your model, instead of as a separate file, use a DocBlock to integrate custom HDL code. The text in the DocBlock is your custom VHDL® or Verilog® code.
You include each DocBlock that contains custom HDL code by placing it in a black box subsystem, and including the black box subsystem in your DUT. One HDL file is generated per black box subsystem.
If you want to keep your custom HDL code separate from your model, such as when the custom code is IP or a library from a third party, use a black box subsystem or black box model reference.
In your DUT, at any level of hierarchy, add a Subsystem block.
For the Subsystem block, in the HDL Block Properties dialog box:
Set Architecture to BlackBox.
Customize the black box subsystem interface so that it matches your custom HDL code interface. To learn more about customizing the black box interface, see Customize Black Box or HDL Cosimulation Interface.
In the subsystem, add a DocBlock block.
For the DocBlock, in the HDL Block Properties dialog box:
Set Architecture to HDLText.
Set TargetLanguage to your target
language, either Verilog or VHDL˙.
In the DocBlock, enter the HDL code
for your custom Verilog module or VHDL entity.
The language must match the DocBlock TargetLanguage setting.
The black box subsystem that contains the DocBlock cannot be the top-level DUT.
You can have a maximum of two DocBlock blocks in the
black box subsystem. If you have two DocBlock blocks,
one must have TargetLanguage set to VHDL,
and the other must have TargetLanguage set to Verilog.
When generating code, HDL Coder™ only integrates the code from the DocBlock that matches the target language for code generation.
The hdlcoderIncludeCustomHdlUsingDocBlockExample model shows how to integrate custom VHDL and Verilog code into your design with the DocBlock block.