Get Started with Simscape Hardware-in-the-Loop Workflow

To perform hardware-in-the-loop (HIL) simulation with smaller timesteps and increased accuracy, deploy the Simscape™ plant models to the FPGAs on board the Speedgoat I/O modules.

Generate an HDL implementation model by using the Simscape HDL Workflow Advisor. The implementation model is a Simulink^® model that replaces the Simscape components with HDL-compatible Simulink blocks.
Generate HDL code for the implementation model, and then deploy the generated code to generic FPGAs, SoCs, or FPGAs on board Speedgoat FPGA I/O modules by using the HDL Workflow Advisor.

By using this capability, you can model and deploy complex physical systems in Simscape that previously took long time to model by using Simulink blocks.

Simscape Example Models for HDL Code Generation

For HDL code generation, you can design your own Simscape algorithm or choose from a list of example models that are created in Simscape. The example models include:

Boost converter
Bridge rectifier
Buck converter
Half-wave rectifier
Three phase rectifier
Two level converter ideal
Two level converter IGBT
Solar power inverter model
Swiss rectifier
Vienna rectifier

All examples are prefixed with sschdlex and postfixed with Example. For example, to open the boost converter model, at the MATLAB^® command prompt, enter:

load_system('sschdlexBoostConverterExample')
open_system('sschdlexBoostConverterExample/Simscape_system')

Guidelines for Modeling Simscape for HDL Compatibility

Follow these guidelines when designing your Simscape algorithm for compatibility with Simscape HDL Workflow Advisor. To replace the subsystem that uses Simscape blocks with the corresponding state-space algorithm, follow these additional guidelines as described in Modeling Guidelines for Simscape Subsystem Replacement.

Use Linear and Switched Linear Blocks

Create a Simscape model by using linear and switched linear blocks. Linear blocks are blocks that are defined by a linear relationship such as resistors. Switched linear blocks are blocks such as diodes and switches. These blocks are also defined by a linear relationship such as V = IR where R can switch between two or more values depending on the state of the diodes or switches.

Nonlinear blocks are not supported. To verify that the Simscape model does not contain nonlinear blocks, use the simscape.findNonlinearBlocks (Simscape) function. Provide the path to your Simscape model as an argument to this function.

simscape.findNonlinearBlocks('current_model')

Alternatively, to verify that the model does not contain nonlinear blocks, run the Check switched linear task of the Simscape HDL Workflow Advisor.

Specify Backward Euler Solver with Discrete Sample Time

Configure the solver options for HDL code generation by using a Solver Configuration (Simscape) block.

In the Block Parameters dialog box of this block:

Select Use local solver.
Use Backward Euler as the Solver type.
Specify a discrete sample time, Ts.

To verify that the solver settings are specified correctly, run the Check solver configuration task of the Simscape HDL Workflow Advisor.

Run hdlsetup function

After creating the model, configure the model for HDL code generation by running the hdlsetup function. hdlsetup configures the solver settings such as using a fixed-step solver, specifies the simulation start and stop times, and so on. To run the command for your current_model:

hdlsetup('current_model')

Restrictions for HDL Code Generation from Simscape Models

HDL Coder™ does not support code generation from Simscape networks that contain:

Events
Mode charts
Delays
Runtime parameters
Periodic sources
Simscape Multibody™ blocks
Simscape Electrical™ Specialized Power Systems blocks
Nonlinear and time-varying Simscape blocks. Time-varying blocks include blocks such as Variable Inductor and Variable Capacitor.
Nonscalar states or inputs to the network. Split nonscalar inputs into scalar inputs and reduce the second operand of the colon operator by one for error caused by nonscalar states. For example:
```
% Suppose this code generates an error
tmp1 = u(1:4); 

% Fix the error by reducing second operand by 1
tmp1 = u(1:3);
```

Documentation