Float Typecast

Typecast a floating-point type to an unsigned integer or vice versa

Library:
HDL Coder / HDL Floating Point Operations

Description

The block casts the underlying bits of the input to the corresponding fixed-point or floating point representation. The input and output of the block contain the same number of bits.

Input Data Type	Output Data Type
`single`	`uint32`
`double`	`ufix64`
`uint32`	`single`
`ufix64`	`double`

This figure shows how the block mask, behavior, and output data type changes dynamically depending on the input data type that you specify.

Ports

Input

expand all

`Port_1(u)` — Input signal
`scalar` | `vector`

Port to provide input to the block.

Data Types: single | double | uint32 | fixed point

Output

expand all

`Port_1(y)` — Output signal
`scalar` | `vector`

Port to obtain calculated output from the block.

Data Types: single | double | uint32 | fixed point

Model Examples

Simulate and Generate HDL Code for the Float Typecast Block

Use Float Typecast block to cast input to floating-point or fixed-point.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

The block supports HDL code generation in the Native Floating Point mode. To use this mode, specify single or uint32 data types as input to the block. With the HDL Code Advisor, you can replace Data Type Conversion blocks that use the Stored Integer (SI) mode and convert between floating-point and fixed-point data types.

The block supports code generation for complex signals.

Documentation

Float Typecast

Description

Ports

Input

`Port_1(u)` — Input signal
`scalar` | `vector`

Output

`Port_1(y)` — Output signal
`scalar` | `vector`

Model Examples

Simulate and Generate HDL Code for the Float Typecast Block

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Functions

Topics

HDL Coder Documentation

Support

Documentation

Float Typecast

Description

Ports

Input

Port_1(u) — Input signal scalar | vector

Output

Port_1(y) — Output signal scalar | vector

Model Examples

Simulate and Generate HDL Code for the Float Typecast Block

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

See Also

Functions

Topics

HDL Coder Documentation

Support

`Port_1(u)` — Input signal
`scalar` | `vector`

`Port_1(y)` — Output signal
`scalar` | `vector`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.