%% FPGA-in-the-Loop Simulation with Vision HDL Toolbox Blocks 
% This example shows how to modify the generated FPGA-in-the-loop (FIL) model
% for more efficient simulation of the Vision HDL Toolbox(TM) streaming video protocol. 

%% Autogenerated FIL Model
% When you generate a programming file for a FIL target in Simulink, the 
% HDL Workflow Advisor creates a model to compare the FIL simulation with your Simulink design.
% For details of how to generate FIL artifacts for a Simulink model, see <docid:hdlv_ug.bt0_qtw-2 FIL Simulation with HDL Workflow Advisor for Simulink>. 
%
% For Vision HDL Toolbox designs, the FIL block in the generated model replicates
% the pixel-streaming interface and sends one pixel at a time to the FPGA. 
% The model shown was generated from the example model in <docid:visionhdl_gs.buouzn9-1 Design Video Processing Algorithms for HDL in Simulink>.
%
% <<../FILSimulinkWithVHT_gm_model.png>>
%
% The top part of the model replicates your Simulink design. The generated 
% FIL block at the bottom communicates with the FPGA. ToFILSrc subsystem 
% copies the pixel-stream input of the HDL Algorithm block to the FromFILSrc
% subsystem. The ToFILSink subsystem copies the pixel-stream output of the 
% HDL Algorithm block into the Compare subsystem, where it is compared with
% the output of the HDL Algorithm_fil block. For image and video processing,
% this setup is slow because the model sends only a single pixel, and its 
% associated control signals, in each packet to and from the FPGA board.
%
%% Modified FIL Model for Pixel Streaming
% To improve the communication bandwidth with the FPGA board, you can use the 
% generated FIL block with vector input rather than streaming. This example
% includes a model, <matlab:open_system('FILSimulinkWithVHTExample') FILSimulinkWithVHTExample.slx>, created by modifying the generated FIL model. 
% The modified model uses the FIL Frame To Pixels and FIL Pixels To Frame 
% blocks to send one frame at a time to the generated FIL block. You cannot
% run this model as is. You must generate your own FIL block and bitstream 
% file that use your board and connection settings.   
% 
modelname = 'FILSimulinkWithVHTExample';
open_system(modelname);
set_param(modelname, 'SampleTimeColors', 'on');
set_param(modelname,'SimulationCommand','Update');
set_param(modelname, 'Open', 'on');
set(allchild(0),'Visible', 'off');

%% 
% To convert from the generated model to the modified model: 
% 
% # Remove the ToFILSrc, FromFILSrc, ToFILSink, and Compare subsystems, and create a branch at the frame input of the Frame To Pixels block.
% # Insert the FIL Frame To Pixels block before the HDL Algorithm_fil block. Insert the FIL Pixels To Frame block after the HDL Algorithm_fil block.
% # Branch the frame output of the Pixels To Frame block for comparison. You can compare the entire frame at once with a Diff block. Compare the |validOut| signals using an XOR block.
% # In the FIL Frame To Pixels and FIL Pixels To Frame blocks, set the Video format parameter to match the video format of the Frame To Pixels and Pixels To Frame blocks.
% # Set the *Vector size* in the FIL Frame To Pixels and FIL Pixels To Frame blocks to |Frame| or |Line|. The size of the FIL Frame To Pixels vector output must match the size of the FIL Pixels To Frame vector input. The vector size of the FIL block interfaces does not modify the generated HDL code. It affects only the packet size of the communication between the simulator and the FPGA board.
% 
% The modified model sends an entire frame to the FPGA board in each packet, 
% significantly improving the efficiency of the communication link.

%% 
% Copyright 2012 The MathWorks, Inc.