%% ------------------------------------------------------------------------
% This script contains the model, target settings, interface mapping, and 
% the Workflow Configuration settings for generating HDL code for the HDL
% implementation model generated for the buck converter model, and for
% deploying the code to the FPGA on board the Speedgoat IO334-325K module.
%% -----------------------------------------------------------------------

%% Set Parameters for HDL Code Generation 

% Model HDL parameters
% -------------------------------------------------------------------------
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'FloatingPointTargetConfiguration', hdlcoder.createFloatingPointTargetConfig('NativeFloatingPoint', 'LatencyStrategy', 'MIN'));
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'HDLSubsystem', 'gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'Oversampling', 100);
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'ScalarizePorts', 'DUTLevel');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'TargetFrequency', 200);
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'Workflow', 'Simulink Real-Time FPGA I/O');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'TargetPlatform', 'Speedgoat IO334-325k');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte', 'AdaptivePipelining', 'off');

%% Map DUT Ports to Target Interfaces

% Input port mapping
% -------------------------------------------------------------------------
% All input signals to the "FPGA" subsystem are mapped to the PCIe
% interface. I.e. these signals will be transferred from the CPU of the
% real-time target machine to the IO334 FPGA over the PCIe bus.

hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/PWM Period', 'IOInterface', 'PCIe Interface');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/Duty Cycle', 'IOInterface', 'PCIe Interface');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DC Input Voltage', 'IOInterface', 'PCIe Interface');

% Output port mapping
% -------------------------------------------------------------------------
% The scaled output signals of the converter are mapped to the analog
% output interface of the IO334. 

hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC V Out', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC V Out', 'IOInterfaceMapping', 'Channel 01');

hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC V Diode', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC V Diode', 'IOInterfaceMapping', 'Channel 02');

hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC I Inductor', 'IOInterface', 'IO334 AO Data [0:15]');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC I Inductor', 'IOInterfaceMapping', 'Channel 03');

hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC Trigger', 'IOInterface', 'IO334 AO Trigger [0:1]');
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/DAC Trigger', 'IOInterfaceMapping', 'Channel 01 to 08');

% The signal frames are mapped to PCIe registers. They are read by the CPU for data logging.
hdlset_param('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA/PCIe Out', 'IOInterface', 'PCIe Interface');

%% Workflow Configuration Settings

% HDL Workflow Advisor is opened with the following settings.
hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','Simulink Real-Time FPGA I/O');

% Specify the top level project directory.
hWC.ProjectFolder = 'hdl_prj';
hWC.ReferenceDesignToolVersion = '2019.2';

% Set Workflow tasks to run.
hWC.RunTaskGenerateRTLCodeAndIPCore = true;
hWC.RunTaskCreateProject = true;
hWC.RunTaskBuildFPGABitstream = true;
hWC.RunTaskGenerateSimulinkRealTimeInterface = true;

%% Run the Workflow
hdlcoder.runWorkflow('gmStateSpaceHDL_sschdlex_IO334_BuckConverte/FPGA', hWC);