%% FPGA Programming and Configuration on Speedgoat Simulink-Programmable I/O Modules
% This example shows how to implement a Simulink(R) algorithm on a
% Speedgoat Simulink-programmable I/O module by using the HDL Workflow Advisor. 
% You run the |Simulink Real-Time FPGA IO| workflow to:
%
% # Specify an FPGA I/O module and its interfaces.
% # Synthesize the Simulink algorithm for FPGA programming.
% # Generate a Simulink(R) Real-Time(TM) interface subsystem model.
%
% The interface subsystem model contains blocks to program the FPGA and
% communicate with the FPGA module through the PCIe bus during real-time 
% application execution. You add the generated subsystem to your Simulink
% Real-Time domain model.
%
% This example uses the Speedgoat IO397-50k module. See <docid:hdlcoder_ug#bsuyo3n-1>.
%
% Copyright 2020 The MathWorks, Inc.

%% Setup and Configuration
% 
% Before deploying your algorithm on the Speedgoat IO module:
%
% 1. Install the latest version of Xilinx(R) Vivado(R) as listed in 
% <docid:hdlcoder_gs#btp_jaq>. 
%
% Then, set the tool path to the installed Xilinx Vivado executable by using 
% the <docid:hdlcoder_ref#burmn3j-1> function.
%
%   hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2019.2\bin\vivado.bat')
%
% 2. For real-time simulation, set up the development environment and target
% computer settings. See <docid:slrealtime_doccenter#gscat>.
%
% 3. Install the Speedgoat Library and the Speedgoat HDL Coder Integration
% packages. See <https://www.speedgoat.com/help/hdlcoder/page/refentry_workflow 
% Install Speedgoat HDL Coder Integration Packages>.

%% HDL Workflow Advisor
% 
% The HDL Workflow Advisor guides you through HDL code generation and the 
% FPGA design process. Use the Advisor to:
%
% * Check the model for HDL code generation compatibility and
%  fix incompatible settings.
% * Generate HDL code, test bench, and scripts to build and run the
% code and test bench.
% * Perform synthesis and timing analysis.
% * Deploy the generated code on SoCs, FPGAs, and Speedgoat I/O modules.
%
% To open the HDL Workflow Advisor for a subsystem inside the model, use the 
% <docid:hdlcoder_ref#bsgdu85> function.
%
%   load_system('sschdlexTwoLevelConverterIgbtExample')
%   hdladvisor('sschdlexTwoLevelConverterIgbtExample/Simscape_system')
%
%%
% The left pane of the Advisor contains folders that represent a group of related 
% tasks. Expanding the folders and selecting a task displays 
% information about that task in the right pane. The right pane
% contains simple controls for running the task to advanced parameters 
% and option settings that control HDL code and test bench generation. 
% To learn more about each task, right-click that task, and select *What's This?*. 
% See <docid:hdlcoder_ug#bse5hm4>.

%% Simulink Loopback Domain Model
% The Simulink domain model has a subsystem that contains the algorithm
% to program onto the FPGA chip. Use this model to test your FPGA
% algorithm in a simulation environment before you download the algorithm
% to an FPGA board. In this case, the model is a loopback test. 
%
%   open_system('dslrtSGFPGAloopback_fpga')
%
% This model is your FPGA domain model. It represents the simulation sample
% rate of the clock on your FPGA board. The |loopback| subsystem contains
% the algorithm to load on the FPGA. The data type and the number of
% input and output lines of the model are configured to fit the 
% |Speedgoat IO397-50k| platform. 
open_system('hdlcoder_slrt_loopback')
set_param('hdlcoder_slrt_loopback', 'SimulationCommand', 'Update')

%% Generate Simulink Real-Time Interface Model for Speedgoat IO397 Platform
% 1. Open the HDL Workflow Advisor for the |loopback| subsystem. This
% subsystem is loaded on the FPGA.
%
%   hdladvisor('hdlcoder_slrt_loopback/loopback')
%%
% 2. Expand the *Set Target* folder. In the *Set Target Device and Synthesis Tool*
% task, specify *Target workflow* as |Simulink Real-Time FPGA I/O| and 
% *Target platform* as |Speedgoat IO397-50k|. Right-click the
% *Set Target Reference Design* task and select *Run to Selected Task*.
%
% <<../loopback_set_target_device_synth_tool.png>>
% 
% 3. In the *Set Target Interface* task, map ports |hwIn| and |hwOut| to
% |IO397_TTL [0:13]| and |pciRead C0-C4| and |pciWrite C0-C4| to |PCIe interface|.
% Click *Run This Task*. 
%
% <<../loopback_set_target_interface.png>>
% 
% 4. Run the *Set Target Frequency* task with the default value set for
% *Target Frequency (MHz)*. The target frequency must be in the range 
% *Frequency Range (MHz)*.
%
% 5. Expand the *Download to Target* task. Right-click the *Generate 
% Simulink Real-Time interface* task and select *Run to
% Selected Task*. 
%
% This task generates RTL code and IP core, FPGA bitstream, and the
% Simulink Real-Time Interface model. In the *Create Project* task, 
% open the Vivado project to see the implemented block design. 

%% Real-Time Subsystem Integration and Execution
% After the *Generate Simulink Real-Time interface* task passes, click the 
% link to open the Simulink Real-Time interface model.
%
% <<../loopback_hdlcoder_slrt_model.png>>
%
% The Simulink-Real Time Interface model contains a masked subsystem that 
% has the same name as the subsystem in the Simulink FPGA domain model. 
% This subsystem is the Simulink Real-Time Interface subsystem that 
% contains the algorithm which is loaded onto the FPGA. Use the generated 
% Simulink Real-Time Interface model or create a Simulink Real-Time Domain 
% model and copy the Simulink Real-Time Interface subsystem into that model
% to simulate your FPGA algorithm on the Speedgoat target machine.
%
% In the Simulink Real-Time interface subsystem mask, set three parameters:
%
% * Device index
% * PCI slot
% * Sample time
%
% When the target has a single FPGA I/O board, leave the device index to
% the default value. For multiple FPGA I/O boards, specify a unique device
% index. If two or more boards are of the same type, specify the PCI slot
% for each board.
%
% For real-time testing, you can log the signals and view the simulation
% results on the Simulation Data Inspector. 
%
% # On the *REAL-TIME* tab, open the Simulink Real-Time Explorer and specify
% the target interface connection settings. For an example, see
% <docid:hdlcoder_ug#example-sschil_speedgoat>.
% # On the *REAL-TIME* tab, click *Run on Target* to build and download the 
% Simulink Real-Time application. The real-time application loads onto the 
% Speedgoat target machine and the FPGA algorithm bitstream loads onto the 
% FPGA. 
%
% You can then view the simulation results on the Simulation Data Inspector.